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Uniform aluminum deposits on large non-planar and planar polyimide substrates by physical vapor deposition
756
World Abstracts on Microelectronics and Reliability
Plasma enhanced CVD in a novel LPCVD-type system. RICHARD S. ROSLER and GEORGE M. ENGLE. Solid-St. Technol. 172 (April 1981). The design of an innovative high throughput plasma-enhanced CVD production system is described. Load sizes of 108 3", 70 100mm, or 30 125ram wafers are held vertically on graphite slabs within a hot-wall diffusion-type system. Process parameters for the uniform deposition of silicon nitride and undoped, phosphorus and arsenic doped silicon dioxide and amorphous and polycrystalline silicon are presented. Properties of these films arc also discussed. Multi-scan electron beam sintering of AI Si OHMIC contacts. M. FINETTI, S. SOLM1 and G. SONCINI. Solid-St. Electron. 24, 539 (1981). Experiments on sintering of A1 Si ohmic contacts by scanning electron beam annealing are presented and discussed. Special test patterns have been used to measure the contact resistivity, while diode reverse current density has been checked to evaluate the junction leakage induced by the aluminum silicon interaction during sintering. Electron beam annealing allows to obtain contact resistivities of the order of 10-Sf~cm 2, i.e. typical of conventional thermal sintering, while avoiding or strongly reducing the interdiffusion at the metal-silicon interface. High quality aluminum contacts on 0.3/~m phosphorus diffused junctions have been made by 20 keV electron beam sintering at 0.25A/cm 2 current density with negligible increase in junction leakage, while conventional thermal sintering, carried out for comparison, failed as expected due to heavy leakage induced by localized interdiffusion. Anisotropic etching in chlorine-containing plasmas. VINCENT M. DONNELLY and DANIEL L. FLAMM.Solid-St. TechnoL 161 (April 1981 ). Current theories of anisotropic plasma etching of semiconductor materials are reviewed, with emphasis on chlorine-containing plasmas. Manipulation of pressure, applied frequency and mixture chemistry for etch rate and profile control are analyzed. Some examples illustrate the use of these parameters to obtain desirable etch rates, profiles and selectivity with Si, At, and III-V compounds. Individual wafer metallization utilizing load-locked, closecoupled conical magnetron sputtering. VANCE E. HOFFMAN and HELEN M. CHANG. Solid-St. Technol. 105 (February 1981). Aluminum and aluminum alloy metallization of individual wafers is accomplished on a cassette to cassette basis. The wafer after metallization is returned to the very same cassette position as before metallization. Along with the newly designed high rate conical magnetron sputtering source which deposits 12,000 A/min, the cassette to cassette wafer coater provides a throughput of one wafer a minute. The high-deposition rate helps to produce films that are sufficiently gas free so that large grain size metallizations can be chemically etched without evidence of over etch at grain boundaries. Such gas free metallizations permit better step coverage and are smoother (less hillocks). The new substrate heater heats a wafer to 350°C in one minute. Sustained heat during deposition is available for growing larger grained (30/z) films if desired. This sustained heating option extends the range of parameters to tailor wafer processing. Uniform aluminum deposits on large non-planar and planar polyimide substrates by physical vapor deposition. GERALD J. HALE. Solid-St. Technol. 141 (February 1981). A physical vapor deposition process with an electron beam gun vapor source was developed to deposit 10- to 12-#m thick pure aluminum films with better than 2 percent thickness uniformity (standard deviation/average thickness) over a surface area of greater than 2000cm 2. A precision shaped shadow mask is inserted between the substrate and vapor source during deposition to provide a uniform deposition rate over the entire surface of these substrates. The shadow
mask is generated with the aid of a computer-reduced plot obtained from beta-backscatter thickness data that were measured on the deposit from a previous deposition run. With this method, thickness uniformities of 9.7 and 24.7 percent acquired for the initial nonplanar and planar deposits were improved to 1.07 and 1.80 percent, respectively. Further improvement is expected on the planar substrate deposit with additional iterations to optimize the mask configuration.
Safety in chemical vapor deposition. M. L. HAMMOND. SolidSt. Technol. 104 (December 1980). Safety is an essential part of semiconductor CVD. Key areas of CVD safety arc identified and recommendations for action are given for each area. CVD technology can be handled in a safe manner provided the users understand the hazards involved and take appropriate action. Reverse CMOS processing. Roy L. MADDOX. Solid-St. Technol. 128 (February 1981). Conventional bulk CMOS device processing is generally based upon the PMOS process structure. However, since the optimal device process in production today is NMOS, a reverse CMOS structure process is needed to complement the NMOS technology. Present uses for reverse CMOS could include the input-output drivers for NMOS memories and/or on-chip clocks to reduce power consumption. The reverse CMOS layout, bipolar parasitics, N-well design constraints, and the results of an experimental reverse CMOS device fabrication lot are discussed. This configuration is compared to conventional CMOS and is shown to be superior with respect to bipolar parasitic effects (lower 13) and is also compatible with standard isoplanar, N + p o l y NMOS processing. Wafer-etching systems line up. LINDA LOWE. Electronics 183 i24 February 1981). To meet exacting LSI and VLSI production demands, new systems follow trend toward dry etching and increased control of process variables. Automated semiconductor line speeds custom chip production. R. H. BRUNNER,E. J. HOLDEN, J. C. LUBER,D. T. MOZER and NING-GAU Wu. Electronics 121 (27 January 1981). Computerized wafer routing under distributed control aids in customizing master slice wafers moving on an air track. Strip architecture fits microcomputer into less silicon. JOHN HAYN, KEVIN McDoNOUGH and JEFFREYBELLAY.Electronics 107 (27 January 1981). Most 8-bit microcomputer families, which arc based on existing microprocessors, are gaining members by bringing more and more features on chip while keeping the processor unchanged. Because all the chip's subunits are designed separately and fitted together only at the last minute, the resulting maze of interconnections has meant a tremendous waste of silicon. But now a one-chip microcomputer has been designed from the ground up, with its architecture for the first time oriented to take the most advantage of available silicon. Post-characterization of GaAs field effect transistors and integrated circuits on test patterns. M. ROCCHI. Acta Electron. 23 (1) 63 (1980) (in French). Characterization facilities are a must to fabricate gallium arsenide discrete devices or integrated circuits efficiently. A very fast feed-back of the results is required to improve on the quality of the substrate, on that of the active layer and on the fabrication process itself. That is what the automated post-characterization is meant for. First, the various physical and electrical parameters of the post-characterization (once the fabrication process completed) are presented, then the measuring methods are analysed and the precision on the results is evaluated. Finally, a detailed description of the automated measuring bench is given.
World Abstracts on Microelectronics and Reliability
Plasma enhanced CVD in a novel LPCVD-type system. RICHARD S. ROSLER and GEORGE M. ENGLE. Solid-St. Technol. 172 (April 1981). The design of an innovative high throughput plasma-enhanced CVD production system is described. Load sizes of 108 3", 70 100mm, or 30 125ram wafers are held vertically on graphite slabs within a hot-wall diffusion-type system. Process parameters for the uniform deposition of silicon nitride and undoped, phosphorus and arsenic doped silicon dioxide and amorphous and polycrystalline silicon are presented. Properties of these films arc also discussed. Multi-scan electron beam sintering of AI Si OHMIC contacts. M. FINETTI, S. SOLM1 and G. SONCINI. Solid-St. Electron. 24, 539 (1981). Experiments on sintering of A1 Si ohmic contacts by scanning electron beam annealing are presented and discussed. Special test patterns have been used to measure the contact resistivity, while diode reverse current density has been checked to evaluate the junction leakage induced by the aluminum silicon interaction during sintering. Electron beam annealing allows to obtain contact resistivities of the order of 10-Sf~cm 2, i.e. typical of conventional thermal sintering, while avoiding or strongly reducing the interdiffusion at the metal-silicon interface. High quality aluminum contacts on 0.3/~m phosphorus diffused junctions have been made by 20 keV electron beam sintering at 0.25A/cm 2 current density with negligible increase in junction leakage, while conventional thermal sintering, carried out for comparison, failed as expected due to heavy leakage induced by localized interdiffusion. Anisotropic etching in chlorine-containing plasmas. VINCENT M. DONNELLY and DANIEL L. FLAMM.Solid-St. TechnoL 161 (April 1981 ). Current theories of anisotropic plasma etching of semiconductor materials are reviewed, with emphasis on chlorine-containing plasmas. Manipulation of pressure, applied frequency and mixture chemistry for etch rate and profile control are analyzed. Some examples illustrate the use of these parameters to obtain desirable etch rates, profiles and selectivity with Si, At, and III-V compounds. Individual wafer metallization utilizing load-locked, closecoupled conical magnetron sputtering. VANCE E. HOFFMAN and HELEN M. CHANG. Solid-St. Technol. 105 (February 1981). Aluminum and aluminum alloy metallization of individual wafers is accomplished on a cassette to cassette basis. The wafer after metallization is returned to the very same cassette position as before metallization. Along with the newly designed high rate conical magnetron sputtering source which deposits 12,000 A/min, the cassette to cassette wafer coater provides a throughput of one wafer a minute. The high-deposition rate helps to produce films that are sufficiently gas free so that large grain size metallizations can be chemically etched without evidence of over etch at grain boundaries. Such gas free metallizations permit better step coverage and are smoother (less hillocks). The new substrate heater heats a wafer to 350°C in one minute. Sustained heat during deposition is available for growing larger grained (30/z) films if desired. This sustained heating option extends the range of parameters to tailor wafer processing. Uniform aluminum deposits on large non-planar and planar polyimide substrates by physical vapor deposition. GERALD J. HALE. Solid-St. Technol. 141 (February 1981). A physical vapor deposition process with an electron beam gun vapor source was developed to deposit 10- to 12-#m thick pure aluminum films with better than 2 percent thickness uniformity (standard deviation/average thickness) over a surface area of greater than 2000cm 2. A precision shaped shadow mask is inserted between the substrate and vapor source during deposition to provide a uniform deposition rate over the entire surface of these substrates. The shadow
mask is generated with the aid of a computer-reduced plot obtained from beta-backscatter thickness data that were measured on the deposit from a previous deposition run. With this method, thickness uniformities of 9.7 and 24.7 percent acquired for the initial nonplanar and planar deposits were improved to 1.07 and 1.80 percent, respectively. Further improvement is expected on the planar substrate deposit with additional iterations to optimize the mask configuration.
Safety in chemical vapor deposition. M. L. HAMMOND. SolidSt. Technol. 104 (December 1980). Safety is an essential part of semiconductor CVD. Key areas of CVD safety arc identified and recommendations for action are given for each area. CVD technology can be handled in a safe manner provided the users understand the hazards involved and take appropriate action. Reverse CMOS processing. Roy L. MADDOX. Solid-St. Technol. 128 (February 1981). Conventional bulk CMOS device processing is generally based upon the PMOS process structure. However, since the optimal device process in production today is NMOS, a reverse CMOS structure process is needed to complement the NMOS technology. Present uses for reverse CMOS could include the input-output drivers for NMOS memories and/or on-chip clocks to reduce power consumption. The reverse CMOS layout, bipolar parasitics, N-well design constraints, and the results of an experimental reverse CMOS device fabrication lot are discussed. This configuration is compared to conventional CMOS and is shown to be superior with respect to bipolar parasitic effects (lower 13) and is also compatible with standard isoplanar, N + p o l y NMOS processing. Wafer-etching systems line up. LINDA LOWE. Electronics 183 i24 February 1981). To meet exacting LSI and VLSI production demands, new systems follow trend toward dry etching and increased control of process variables. Automated semiconductor line speeds custom chip production. R. H. BRUNNER,E. J. HOLDEN, J. C. LUBER,D. T. MOZER and NING-GAU Wu. Electronics 121 (27 January 1981). Computerized wafer routing under distributed control aids in customizing master slice wafers moving on an air track. Strip architecture fits microcomputer into less silicon. JOHN HAYN, KEVIN McDoNOUGH and JEFFREYBELLAY.Electronics 107 (27 January 1981). Most 8-bit microcomputer families, which arc based on existing microprocessors, are gaining members by bringing more and more features on chip while keeping the processor unchanged. Because all the chip's subunits are designed separately and fitted together only at the last minute, the resulting maze of interconnections has meant a tremendous waste of silicon. But now a one-chip microcomputer has been designed from the ground up, with its architecture for the first time oriented to take the most advantage of available silicon. Post-characterization of GaAs field effect transistors and integrated circuits on test patterns. M. ROCCHI. Acta Electron. 23 (1) 63 (1980) (in French). Characterization facilities are a must to fabricate gallium arsenide discrete devices or integrated circuits efficiently. A very fast feed-back of the results is required to improve on the quality of the substrate, on that of the active layer and on the fabrication process itself. That is what the automated post-characterization is meant for. First, the various physical and electrical parameters of the post-characterization (once the fabrication process completed) are presented, then the measuring methods are analysed and the precision on the results is evaluated. Finally, a detailed description of the automated measuring bench is given.