- Email: [email protected]
V-shaped metal–oxide–semiconductor transistor probe with nano tip for surface electric properties
ARTICLE IN PRESS Ultramicroscopy 108 (2008) 1094– 1100
Contents lists available at ScienceDirect
Ultramicroscopy journal homepage: www.elsevier.com/locate/ultramic
V-shaped metal– oxide– semiconductor transistor probe with nano tip for surface electric properties Sang H. Lee a, Geunbae Lim b, Wonkyu Moon b,, Hyunjung Shin c, Cheong-Wol Kim d a
Department of Automotive Engineering, Seoul National University of Technology, Republic of Korea Department of Mechanical Engineering, Pohang University of Science and Technology (POSTECH), Republic of Korea School of Advanced Materials Engineering, Kookmin University, Republic of Korea d Department of Information Technology and Electronics Education, Andong National University, Republic of Korea b c
a r t i c l e in f o
PACS: 85.85.+j 07.79.Lh 68.37.Ps 85.30.Tv Keywords: Scanning probe microscopy Metal–oxide–semiconductor transistor V-shaped cantilever Focused ion beam Parallel beam approximation
a b s t r a c t We design and fabricate a V-shaped metal–oxide–semiconductor (MOS) transistor probe with the focused-ion-beam (FIB) nano tip to measure surface electric properties. The V-shaped structure is selected for its better lateral stiffness, and the specific dimensions are determined using the parallel beam approximation (PBA). The deposition conditions for the nano tip are also investigated for better tip sharpness. The high working frequency of the MOS transistor improves the scanning speed and the high sensitivity reduces the additional equipment required. The detection properties of the device are investigated with PZT poling patterns. The measured results show well-defined patterns, promising that the device can detect surface electric properties with high sensitivity and high working frequency. & 2008 Elsevier B.V. All rights reserved.
1. Introduction Recently, electrostatic force microscopy (EFM), one of the scanning probe microscopy (SPM) family, has been widely used to measure surface electric properties [1–5]. Considering that many kinds of electronic devices have been invented and developed based on the semiconductor technologies, the detection of surface electric properties has become more important. However, although EFM system detects various surface properties like the surface charge distribution [4] and material conductivity [5], it has some drawbacks: it has a limited scanning speed and requires additional equipments like a lock-in-amplifier (Fig. 1). To overcome these difficulties, metal–oxide–semiconductor (MOS) transistor-embedded probes have been investigated [6,7]. They could allow fast scanning and system minimization, but new difficulties arise in fabrication due to the three-dimensional (3-d) tip shape of the MOS transistor. Therefore, we proposed and fabricated a novel SPM probe with a planar MOS transistor and focused-ion-beam (FIB) nano tip in previous research [8]. This process was easier than that for a 3-d tip, which is an advantage in mass production. The fabricated device was applied to a patterned metal structure, showing that
Corresponding author. Tel.: +82 54 279 2184; fax: +82 54 279 5899.
E-mail address: [email protected] (W. Moon). 0304-3991/$ - see front matter & 2008 Elsevier B.V. All rights reserved. doi:10.1016/j.ultramic.2008.04.034
the probe could detect surface electric properties with high speed. However, the device had poor lateral stiffness due to the rectangular structure. Moreover, the device had a small working angle, so the cantilever end contacted the sample surface instead of the tip during the measuring process. In this paper, the V-shaped MOS transistor probe with a nano tip is designed, fabricated and evaluated for surface electric properties as shown in Fig. 2. The V-shaped cantilever has improved lateral stiffness in comparison to the rectangular cantilever [9], and has advantages in accurate measurements and applications. The fabricated device is evaluated with the ferroelectric material, PZT, and the results show promising aspects of the detection of surface electric properties.
2. Experiment 2.1. Design The proposed MOS transistor probe detects the surface electric properties with a FIB metal tip. The sensitivity of the device can be improved by reducing the distance between the tip and the surface, since the electrical properties are inversely proportional to the distance. Therefore, the device is designed for contact mode operation, so the lower spring constant is required.
ARTICLE IN PRESS S.H. Lee et al. / Ultramicroscopy 108 (2008) 1094–1100
Lock-in Amp. Lock-in Amp.
2w
1995 shows less than 2% error with respect to the measured values [10]. This equation gives the spring constant, k as follows:
w k¼
~
1095
Vac sin wt K¼
Vdc
Et3 d 2L3
(
kDL¼DL ¼ kDL¼0
)1
3
cos y 1 þ
4d
3
b
ð3 cos y 2Þ
(1)
3 L L DL
(2)
where E, t, d, b, L and y are the Young’s modulus of silicon, device thickness, arm width, cantilever base width, length, and angle, respectively. As shown in Fig. 3, DL is the distance between the cantilever end and tip, so a reduced DL results in a smaller spring constant, K. Various structure dimensions such as arm width, angle and length are determined with Eq. (1). The metal line patterns require over 30 mm wide vertical arm width (d cos y). Usually, conventional SPM probes have a 40–451 angle, and the arm width (d) becomes over 40 mm at these angles. For a lower spring constant, smaller thickness and larger length are preferred. However, considering fabrication convenience, at least 3 mm thickness is required. From these considerations, lengths of 300, 400, and 500 mm are selected for spring constants less than 5 N/m, as shown in Fig. 4. The figure shows that a spring constant less than 1 N/m is obtained when the arm angle is over 451 and the device is more than 400 mm long.
Feedback Control
Fig. 1. Schematic view of a commercial EFM system.
Nano tip
k (N/m)
3 Fig. 2. Proposed V-shaped MOS transistor probe with nano tip.
500
2 1
450
ΔL
400
L(
10 20 30 40 θ (d egre e)
L
μm )
0
350 50
300 60
L 2
L1
300 μm
3 2.5
400 μm
d
d b
Fig. 3. Dimensions of V-shaped MOS transistor probe with nano tip.
The V-shaped cantilever has quite a complex structure, as shown in Fig. 3, and the approximation technique is applied to evaluate the structural variables. Many parallel beam approximation (PBA) equations have been reported for the spring constant of a V-shaped cantilever, and they show the good agreement with measured data. Among these, the equation by John E. Sader in
k (N/m)
2 1.5
500 μm
1 0.5
20
30
40
50
60
θ (degree) Fig. 4. Graphs of the spring constant with device variables (generated by Mathematica), (a) spring constant graph with respect to various lengths: (b) spring constant graph with respect to specific lengths and arm angles.
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SiO2 Cr/Au Phos. doping Gate oxide Varied oxide Fig. 5. Fabrication process of V-shaped MOS transistor probe with nano tip: (a) source–drain doping, (b) gate oxide growing, (c) viahole etching, (d) metal patterning, (e) top side define, (f) cantilever release, (g) nano tip growth, (h) fabricated device.
2.2. Fabrication: fabrication process
2.3. Fabrication: circuit diagram
Fig. 5 shows the fabrication process of the V-shaped MOS transistor probe. It starts with (1 0 0) SOI wafers with a 400 mm thick back substrate, 1 mm thick oxide layer, and 3 and 5 mm thick device layers. The operation speed of the NMOS transistor is faster than that of PMOS, so p-type SOI wafer is selected. The MOS transistor structure is fabricated with common CMOS processes. After defining the source and drain regions, phosphorus ions are implanted with 80 keV power and 1015 cm2 dose. During a drive-in process at 1050 1C for 1 h, an oxide layer is grown to protect the doping area from the remaining processes. After defining the gate area, a dry oxidation process is performed at 1100 1C for 3 min to give an oxide layer with 30 nm thickness. After the via-holes are patterned, 30/300 nm thick Cr/Au layers are deposited for the metal electrode and the nano tip basement. The cantilever structure is released with deep-Si etching. The nano tip is grown by a FIB system (Nova 200, FEI company) with a platinum source. The target tip shape is a cone-like structure, and the diameter decreases with the height. The successive deposition process is used since the tip diameters are related with the deposition conditions. The large base of the cone uses the normal beam current, 30 pA. In contrast, the tip end uses the smallest beam current, 1 pA. FIB nano tips over 5 mm high are fabricated with these successive depositions.
Fig. 6 shows the circuit diagram for the measurement of the current between source and drain. The circuit is a kind of currentto-voltage converter, which solves the limitation on the sampling time and measuring frequency of the commercial semiconductor analyzer. Moreover, this circuit can be minimized with IC components, so the whole system can be compact, and various applications are possible. The circuit has additional sub-units such as amplifying unit, voltage source unit, and zero point calibration unit. The output current variations are very small with the order of a few micro amperes, so the amplifying unit is required. And, for applying the various drain voltages, the 0–10 V voltage source unit is also integrated with the variable resistance. The output voltage may have a DC offset, so the zero point calibration unit is added for the precision measurement.
3. Results and discussion 3.1. Fabrication results Fig. 7 shows the fabricated device. Fig. 7(a) is the device after the phosphorus doping process, where the source and drain
ARTICLE IN PRESS S.H. Lee et al. / Ultramicroscopy 108 (2008) 1094–1100
Zero point calibration unit
1097
Amplification unit
R1
+15V
-15V
R4 +
+ -
Output voltage
+15V -15V +15V
R2 Voltage source unit MOS transistor probe
R3
Fig. 6. Circuit diagram for source-drain current measurement.
Fig. 7. Photos of fabricated V-shaped MOS transistor probe with nano tip: (a) doping region etching, (b) gate region etching, (c) metal line define, (d) released devices, (e) released cantilever, (f) FIB nano tip.
regions are clearly defined. The gate region and the electrode patterns are shown in Fig. 7(b) and (c), respectively. Fig. 7(d) and (e) shows the released device. From Fig. 7(d), we can see the cantilever device arrays are safely released. Fig. 7(e) is an SEM photo of the tip. The FIB nano tip is fabricated at the end of the cantilever, which has better approaching property during measurements. Moreover, the device has a better spring constant due to the minimized DL. Figs. 8 and 9 show the fabricated FIB nano tips with different deposition conditions. All nano tips are designed as cone shapes which are composed of circular rods with gradually
reduced diameters. The FIB nano tip in Fig. 8(a) is deposited with 30 pA current for the entire process, which has over 220 nm diameter at the tip end. Moreover, an undesired pattern is observed at the end of the tip. This phenomenon is due to two reasons. First, the etching phenomenon happens along with the deposition phenomenon, because the 30 pA current is too strong for the deposition of the tip end. This feature is dominant at the tip end. The other reason is the deposition mechanism. The injected gas flows from one side to the other as seen in Fig. 8(b). As seen in Fig. 8(c), the height of the tip in gas injection direction is higher than that in opposite direction. This means the
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Fig. 9. Successive FIB tip deposition with varied deposition currents: (a) tip base part under 30 pA deposition current, (b) tip middle part under 10 pA deposition current, (c) Final tip end under 1 pA deposition current. Fig. 8. FIB tip deposition and problem at 30 pA deposition current: (a) FIB nano tip with 30 pA deposition current, (b) Schematic diagram of FIB assisted deposition, (c) Directional dependent phenomenon of FIB tip deposition.
previously deposited material prevents later deposition. For this reason, tip deposition is not performed in one step, and the device should be rotated 1801 for uniform deposition. However, in spite of the rotation during deposition, the tip is still not sharp enough since too much metal is deposited at the same time due to the strong current. Therefore, the current is reduced for the decreased diameters as shown in Fig. 9. In the first part, the deposition area is quite large and 30 pA current is applied. This current gives fast deposition and is used from the 1.3 to the 0.8 mm diameter as seen in Fig. 9(a). From 0.7 mm diameter, 10 pA current is applied as in Fig. 9(b). Although smaller diameters can be made at 10 pA, the etching phenomena still occurs at less than 0.2 mm diameter. Thus,
at less than 0.2 mm diameters, 1 pA current, the smallest current given by FIB system is applied. The resulting nano tip shows a well-defined cone shape as shown in Fig. 9(c). The tip end has a 170 nm tip diameter, which is 50 nm smaller than the 220 nm diameter at 30 pA. The deposited metal spreads around the patterns in the FIB deposition process, and the pattern uncertainty inevitably happens although very small patterns are designed. At this time, the deposition conditions are being studied, and sharpening by etching is also under investigation.
3.2. Measurement results The I–V characteristics of the fabricated MOS transistor are measured with a conductive plate. The device contacts plate, and output signals are detected with a semiconductor analyzer
ARTICLE IN PRESS S.H. Lee et al. / Ultramicroscopy 108 (2008) 1094–1100
1099
Fig. 10. Characterization of fabricated MOS transistor probe: (a) I–V characteristics of fabricated device, (b) simulation result of fabricated MOS transistor (by Silvaco program).
(HP 4146B). Fig. 10(a) shows the source–drain current flows at a 0 gate voltage. This current is due to the slight doping of the gate region from the source–drain region. This phenomenon is proven with the simulation result from commercial semiconductor fabrication simulator (Silvaco program) in Fig. 10(b). This result is very important for the surface electric properties since the surface has negative signals as well as positive signals. Common MOS transistors have no current at gate voltages less than 0, and cannot detect negative electric signals. In contrast, since our device has current flows at 0 gate voltage, it can detect negative electric signals as well as positive ones. The PZT poling patterns are used to evaluate the device. The 60 nm thick PZT layer is deposited with epitaxial layer deposition, and the test pattern is formed with a conductive SPM probe. As shown in Fig. 11(a), a 8 V signal is applied for the poling of the whole 5 5 mm2 region and a +8 V for the inner 2.5 2.5 mm2 region. Fig. 11(b) and (c) shows the measurement results of the poling region with the fabricated device and circuit. Since the PZT
surface is very flat, there is no pattern observed in the topology result in Fig. 11(b). In contrast, the poling patterns are clearly observed in Fig. 11(c). In the case of the 8 V poling patterns, negative charges are induced at the top of PZT. These charges repel electrons, and the channel region of the device becomes small. Therefore, the output current decreases, and in consequence, a dark pattern is shown. The opposite phenomenon happens in +8 V poling patterns. The spatial resolution is not clearly defined. However, considering the oblique region between the plus and minus poling regions has about 300 nm length, the spatial resolution is around 300 nm. Considering that the resolution of commercial EFM system is a few tens of nm, this value is quite large. This is probably due to the dull tip radius. As mentioned in the previous section, the minimum tip radius is around 200 nm from the FIB system. In the ideal case, the spatial resolution can also be 200 nm, but is more in reality. Therefore, the spatial resolution can be improved by sharpening the tip radius. The tip sharpening process with FIB etching is being studied.
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Fig. 11. Measurement of PZT poling pattern with fabricated device: (a) schematic measurement diagram of PZT poling patterns, (b) topology measurement result, (c) poling pattern measurement result.
4. Conclusion This paper describes the fabrication of a V-shaped MOS transistor probe with nano tip for surface electric properties. The V-shaped device structure is designed with PBA equation, and fabricated with standard CMOS process. The nano tip is grown by FIB system, and tip deposition conditions are investigated for better tip sharpness. The fabricated device successfully measures the PZT poling patterns, which shows the possibility for the surface electric properties.
Acknowledgments This work was supported by MOST/KOSEF (Project number: R11-2005-048-00000-0 and R01-2005-000-11172-0) and MOCIE
(Project number: 10024719), Korea. We also thank Kyungjin Park in NNFC for the FIB experiments. References [1] D.-M. Chiang, W.-L. Liu, J.-L. Chen, R. Susuki, Chem. Phys. Lett. 412 (2005) 50. [2] S.M. Gheno, H.L. Hasegawa, P.I. Paulin Filho, Scr. Mater. 56 (2007) 545. [3] O. Douhe´ret, A. Swinnen, M. Breselge, I. Van Severen, L. Lutsen, D. Vanderzande, J. Manca, Microelectron. Eng. 84 (2007) 431. [4] Y.J. Oh, J.H. Lee, W. Jo, Ultramicroscopy 106 (2006) 779. [5] C.H. Lei, A. Das, M. Elliott, J.E. Macdonald, Appl. Phys. Lett. 83 (2003) 482. [6] H. Park, J. Jung, D.-K. Min, S. Kim, S. Hong, H. Shin, Appl. Phys. Lett. 84 (2004) 1734. [7] S.H. Lee, P.K. Kim, G. Lim, W. Moon, Microsyst. Technol. 13 (2007) 579. [8] S.H. Lee, G. Lim, W. Moon in: T. Michalske, M. Grunze, N. Shinn (Eds.), in: AVS 53rd International Symposium and Exhibition, San Francisco, USA, 2006. [9] T.R. Albrecht, S. Akamine, T.E. Carver, C.F. Quate, J. Vac. Sci. Technol. A 8 (1990) 3386. [10] J.E. Sader, Rev. Sci. Instrum. 66 (1995) 4583.
Contents lists available at ScienceDirect
Ultramicroscopy journal homepage: www.elsevier.com/locate/ultramic
V-shaped metal– oxide– semiconductor transistor probe with nano tip for surface electric properties Sang H. Lee a, Geunbae Lim b, Wonkyu Moon b,, Hyunjung Shin c, Cheong-Wol Kim d a
Department of Automotive Engineering, Seoul National University of Technology, Republic of Korea Department of Mechanical Engineering, Pohang University of Science and Technology (POSTECH), Republic of Korea School of Advanced Materials Engineering, Kookmin University, Republic of Korea d Department of Information Technology and Electronics Education, Andong National University, Republic of Korea b c
a r t i c l e in f o
PACS: 85.85.+j 07.79.Lh 68.37.Ps 85.30.Tv Keywords: Scanning probe microscopy Metal–oxide–semiconductor transistor V-shaped cantilever Focused ion beam Parallel beam approximation
a b s t r a c t We design and fabricate a V-shaped metal–oxide–semiconductor (MOS) transistor probe with the focused-ion-beam (FIB) nano tip to measure surface electric properties. The V-shaped structure is selected for its better lateral stiffness, and the specific dimensions are determined using the parallel beam approximation (PBA). The deposition conditions for the nano tip are also investigated for better tip sharpness. The high working frequency of the MOS transistor improves the scanning speed and the high sensitivity reduces the additional equipment required. The detection properties of the device are investigated with PZT poling patterns. The measured results show well-defined patterns, promising that the device can detect surface electric properties with high sensitivity and high working frequency. & 2008 Elsevier B.V. All rights reserved.
1. Introduction Recently, electrostatic force microscopy (EFM), one of the scanning probe microscopy (SPM) family, has been widely used to measure surface electric properties [1–5]. Considering that many kinds of electronic devices have been invented and developed based on the semiconductor technologies, the detection of surface electric properties has become more important. However, although EFM system detects various surface properties like the surface charge distribution [4] and material conductivity [5], it has some drawbacks: it has a limited scanning speed and requires additional equipments like a lock-in-amplifier (Fig. 1). To overcome these difficulties, metal–oxide–semiconductor (MOS) transistor-embedded probes have been investigated [6,7]. They could allow fast scanning and system minimization, but new difficulties arise in fabrication due to the three-dimensional (3-d) tip shape of the MOS transistor. Therefore, we proposed and fabricated a novel SPM probe with a planar MOS transistor and focused-ion-beam (FIB) nano tip in previous research [8]. This process was easier than that for a 3-d tip, which is an advantage in mass production. The fabricated device was applied to a patterned metal structure, showing that
Corresponding author. Tel.: +82 54 279 2184; fax: +82 54 279 5899.
E-mail address: [email protected] (W. Moon). 0304-3991/$ - see front matter & 2008 Elsevier B.V. All rights reserved. doi:10.1016/j.ultramic.2008.04.034
the probe could detect surface electric properties with high speed. However, the device had poor lateral stiffness due to the rectangular structure. Moreover, the device had a small working angle, so the cantilever end contacted the sample surface instead of the tip during the measuring process. In this paper, the V-shaped MOS transistor probe with a nano tip is designed, fabricated and evaluated for surface electric properties as shown in Fig. 2. The V-shaped cantilever has improved lateral stiffness in comparison to the rectangular cantilever [9], and has advantages in accurate measurements and applications. The fabricated device is evaluated with the ferroelectric material, PZT, and the results show promising aspects of the detection of surface electric properties.
2. Experiment 2.1. Design The proposed MOS transistor probe detects the surface electric properties with a FIB metal tip. The sensitivity of the device can be improved by reducing the distance between the tip and the surface, since the electrical properties are inversely proportional to the distance. Therefore, the device is designed for contact mode operation, so the lower spring constant is required.
ARTICLE IN PRESS S.H. Lee et al. / Ultramicroscopy 108 (2008) 1094–1100
Lock-in Amp. Lock-in Amp.
2w
1995 shows less than 2% error with respect to the measured values [10]. This equation gives the spring constant, k as follows:
w k¼
~
1095
Vac sin wt K¼
Vdc
Et3 d 2L3
(
kDL¼DL ¼ kDL¼0
)1
3
cos y 1 þ
4d
3
b
ð3 cos y 2Þ
(1)
3 L L DL
(2)
where E, t, d, b, L and y are the Young’s modulus of silicon, device thickness, arm width, cantilever base width, length, and angle, respectively. As shown in Fig. 3, DL is the distance between the cantilever end and tip, so a reduced DL results in a smaller spring constant, K. Various structure dimensions such as arm width, angle and length are determined with Eq. (1). The metal line patterns require over 30 mm wide vertical arm width (d cos y). Usually, conventional SPM probes have a 40–451 angle, and the arm width (d) becomes over 40 mm at these angles. For a lower spring constant, smaller thickness and larger length are preferred. However, considering fabrication convenience, at least 3 mm thickness is required. From these considerations, lengths of 300, 400, and 500 mm are selected for spring constants less than 5 N/m, as shown in Fig. 4. The figure shows that a spring constant less than 1 N/m is obtained when the arm angle is over 451 and the device is more than 400 mm long.
Feedback Control
Fig. 1. Schematic view of a commercial EFM system.
Nano tip
k (N/m)
3 Fig. 2. Proposed V-shaped MOS transistor probe with nano tip.
500
2 1
450
ΔL
400
L(
10 20 30 40 θ (d egre e)
L
μm )
0
350 50
300 60
L 2
L1
300 μm
3 2.5
400 μm
d
d b
Fig. 3. Dimensions of V-shaped MOS transistor probe with nano tip.
The V-shaped cantilever has quite a complex structure, as shown in Fig. 3, and the approximation technique is applied to evaluate the structural variables. Many parallel beam approximation (PBA) equations have been reported for the spring constant of a V-shaped cantilever, and they show the good agreement with measured data. Among these, the equation by John E. Sader in
k (N/m)
2 1.5
500 μm
1 0.5
20
30
40
50
60
θ (degree) Fig. 4. Graphs of the spring constant with device variables (generated by Mathematica), (a) spring constant graph with respect to various lengths: (b) spring constant graph with respect to specific lengths and arm angles.
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SiO2 Cr/Au Phos. doping Gate oxide Varied oxide Fig. 5. Fabrication process of V-shaped MOS transistor probe with nano tip: (a) source–drain doping, (b) gate oxide growing, (c) viahole etching, (d) metal patterning, (e) top side define, (f) cantilever release, (g) nano tip growth, (h) fabricated device.
2.2. Fabrication: fabrication process
2.3. Fabrication: circuit diagram
Fig. 5 shows the fabrication process of the V-shaped MOS transistor probe. It starts with (1 0 0) SOI wafers with a 400 mm thick back substrate, 1 mm thick oxide layer, and 3 and 5 mm thick device layers. The operation speed of the NMOS transistor is faster than that of PMOS, so p-type SOI wafer is selected. The MOS transistor structure is fabricated with common CMOS processes. After defining the source and drain regions, phosphorus ions are implanted with 80 keV power and 1015 cm2 dose. During a drive-in process at 1050 1C for 1 h, an oxide layer is grown to protect the doping area from the remaining processes. After defining the gate area, a dry oxidation process is performed at 1100 1C for 3 min to give an oxide layer with 30 nm thickness. After the via-holes are patterned, 30/300 nm thick Cr/Au layers are deposited for the metal electrode and the nano tip basement. The cantilever structure is released with deep-Si etching. The nano tip is grown by a FIB system (Nova 200, FEI company) with a platinum source. The target tip shape is a cone-like structure, and the diameter decreases with the height. The successive deposition process is used since the tip diameters are related with the deposition conditions. The large base of the cone uses the normal beam current, 30 pA. In contrast, the tip end uses the smallest beam current, 1 pA. FIB nano tips over 5 mm high are fabricated with these successive depositions.
Fig. 6 shows the circuit diagram for the measurement of the current between source and drain. The circuit is a kind of currentto-voltage converter, which solves the limitation on the sampling time and measuring frequency of the commercial semiconductor analyzer. Moreover, this circuit can be minimized with IC components, so the whole system can be compact, and various applications are possible. The circuit has additional sub-units such as amplifying unit, voltage source unit, and zero point calibration unit. The output current variations are very small with the order of a few micro amperes, so the amplifying unit is required. And, for applying the various drain voltages, the 0–10 V voltage source unit is also integrated with the variable resistance. The output voltage may have a DC offset, so the zero point calibration unit is added for the precision measurement.
3. Results and discussion 3.1. Fabrication results Fig. 7 shows the fabricated device. Fig. 7(a) is the device after the phosphorus doping process, where the source and drain
ARTICLE IN PRESS S.H. Lee et al. / Ultramicroscopy 108 (2008) 1094–1100
Zero point calibration unit
1097
Amplification unit
R1
+15V
-15V
R4 +
+ -
Output voltage
+15V -15V +15V
R2 Voltage source unit MOS transistor probe
R3
Fig. 6. Circuit diagram for source-drain current measurement.
Fig. 7. Photos of fabricated V-shaped MOS transistor probe with nano tip: (a) doping region etching, (b) gate region etching, (c) metal line define, (d) released devices, (e) released cantilever, (f) FIB nano tip.
regions are clearly defined. The gate region and the electrode patterns are shown in Fig. 7(b) and (c), respectively. Fig. 7(d) and (e) shows the released device. From Fig. 7(d), we can see the cantilever device arrays are safely released. Fig. 7(e) is an SEM photo of the tip. The FIB nano tip is fabricated at the end of the cantilever, which has better approaching property during measurements. Moreover, the device has a better spring constant due to the minimized DL. Figs. 8 and 9 show the fabricated FIB nano tips with different deposition conditions. All nano tips are designed as cone shapes which are composed of circular rods with gradually
reduced diameters. The FIB nano tip in Fig. 8(a) is deposited with 30 pA current for the entire process, which has over 220 nm diameter at the tip end. Moreover, an undesired pattern is observed at the end of the tip. This phenomenon is due to two reasons. First, the etching phenomenon happens along with the deposition phenomenon, because the 30 pA current is too strong for the deposition of the tip end. This feature is dominant at the tip end. The other reason is the deposition mechanism. The injected gas flows from one side to the other as seen in Fig. 8(b). As seen in Fig. 8(c), the height of the tip in gas injection direction is higher than that in opposite direction. This means the
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Fig. 9. Successive FIB tip deposition with varied deposition currents: (a) tip base part under 30 pA deposition current, (b) tip middle part under 10 pA deposition current, (c) Final tip end under 1 pA deposition current. Fig. 8. FIB tip deposition and problem at 30 pA deposition current: (a) FIB nano tip with 30 pA deposition current, (b) Schematic diagram of FIB assisted deposition, (c) Directional dependent phenomenon of FIB tip deposition.
previously deposited material prevents later deposition. For this reason, tip deposition is not performed in one step, and the device should be rotated 1801 for uniform deposition. However, in spite of the rotation during deposition, the tip is still not sharp enough since too much metal is deposited at the same time due to the strong current. Therefore, the current is reduced for the decreased diameters as shown in Fig. 9. In the first part, the deposition area is quite large and 30 pA current is applied. This current gives fast deposition and is used from the 1.3 to the 0.8 mm diameter as seen in Fig. 9(a). From 0.7 mm diameter, 10 pA current is applied as in Fig. 9(b). Although smaller diameters can be made at 10 pA, the etching phenomena still occurs at less than 0.2 mm diameter. Thus,
at less than 0.2 mm diameters, 1 pA current, the smallest current given by FIB system is applied. The resulting nano tip shows a well-defined cone shape as shown in Fig. 9(c). The tip end has a 170 nm tip diameter, which is 50 nm smaller than the 220 nm diameter at 30 pA. The deposited metal spreads around the patterns in the FIB deposition process, and the pattern uncertainty inevitably happens although very small patterns are designed. At this time, the deposition conditions are being studied, and sharpening by etching is also under investigation.
3.2. Measurement results The I–V characteristics of the fabricated MOS transistor are measured with a conductive plate. The device contacts plate, and output signals are detected with a semiconductor analyzer
ARTICLE IN PRESS S.H. Lee et al. / Ultramicroscopy 108 (2008) 1094–1100
1099
Fig. 10. Characterization of fabricated MOS transistor probe: (a) I–V characteristics of fabricated device, (b) simulation result of fabricated MOS transistor (by Silvaco program).
(HP 4146B). Fig. 10(a) shows the source–drain current flows at a 0 gate voltage. This current is due to the slight doping of the gate region from the source–drain region. This phenomenon is proven with the simulation result from commercial semiconductor fabrication simulator (Silvaco program) in Fig. 10(b). This result is very important for the surface electric properties since the surface has negative signals as well as positive signals. Common MOS transistors have no current at gate voltages less than 0, and cannot detect negative electric signals. In contrast, since our device has current flows at 0 gate voltage, it can detect negative electric signals as well as positive ones. The PZT poling patterns are used to evaluate the device. The 60 nm thick PZT layer is deposited with epitaxial layer deposition, and the test pattern is formed with a conductive SPM probe. As shown in Fig. 11(a), a 8 V signal is applied for the poling of the whole 5 5 mm2 region and a +8 V for the inner 2.5 2.5 mm2 region. Fig. 11(b) and (c) shows the measurement results of the poling region with the fabricated device and circuit. Since the PZT
surface is very flat, there is no pattern observed in the topology result in Fig. 11(b). In contrast, the poling patterns are clearly observed in Fig. 11(c). In the case of the 8 V poling patterns, negative charges are induced at the top of PZT. These charges repel electrons, and the channel region of the device becomes small. Therefore, the output current decreases, and in consequence, a dark pattern is shown. The opposite phenomenon happens in +8 V poling patterns. The spatial resolution is not clearly defined. However, considering the oblique region between the plus and minus poling regions has about 300 nm length, the spatial resolution is around 300 nm. Considering that the resolution of commercial EFM system is a few tens of nm, this value is quite large. This is probably due to the dull tip radius. As mentioned in the previous section, the minimum tip radius is around 200 nm from the FIB system. In the ideal case, the spatial resolution can also be 200 nm, but is more in reality. Therefore, the spatial resolution can be improved by sharpening the tip radius. The tip sharpening process with FIB etching is being studied.
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Fig. 11. Measurement of PZT poling pattern with fabricated device: (a) schematic measurement diagram of PZT poling patterns, (b) topology measurement result, (c) poling pattern measurement result.
4. Conclusion This paper describes the fabrication of a V-shaped MOS transistor probe with nano tip for surface electric properties. The V-shaped device structure is designed with PBA equation, and fabricated with standard CMOS process. The nano tip is grown by FIB system, and tip deposition conditions are investigated for better tip sharpness. The fabricated device successfully measures the PZT poling patterns, which shows the possibility for the surface electric properties.
Acknowledgments This work was supported by MOST/KOSEF (Project number: R11-2005-048-00000-0 and R01-2005-000-11172-0) and MOCIE
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