VDD scalability of FinFET SRAMs: Robustness of different design options against LER-induced variations

Solid-State Electronics 54 (2010) 909–918

Contents lists available at ScienceDirect

Solid-State Electronics journal homepage: www.elsevier.com/locate/sse

VDD scalability of FinFET SRAMs: Robustness of different design options against LER-induced variations Emanuele Baravelli *, Luca De Marchi, Nicolò Speciale ARCES/DEIS – University of Bologna, Viale Risorgimento 2, 40136 Bologna, Italy

a r t i c l e

i n f o

Article history: Available online 20 May 2010 The review of this paper was arranged by Prof. S. Cristoloveanu Keywords: SRAM FinFET Line-edge roughness Device simulation Ensemble Monte Carlo Static noise margin

a b s t r a c t Replacing the conventional MOSFET architecture with multiple gate structures like the FinFET can improve scalability of SRAM circuits, especially in low-voltage/low-power applications. The impact of fin line-edge roughness (LER) on noise margins of LSTP- and LOP-32 nm compatible FinFET SRAMs is systematically investigated at different supply voltages to assess VDD scalability of these cells. Read and write noise margins are computed by performing mixed-mode simulations featuring quantum-corrected hydrodynamic transport models on large Monte Carlo ensembles. A restrictive yield criterion is used to compare several design options, including transistor sizing, mobility changes as a result of crystal orientation, fin patterning and gate stack, and VT tuning through work function (WF) engineering. Confidence intervals are provided to account for ensemble size related statistical noise. Based on simulation results and comparison with published measurements, guidelines are provided to trade-off design options for improved LER robustness and VDD scalability of FinFET SRAMs. Ó 2010 Elsevier Ltd. All rights reserved.

1. Introduction Embedded memory constitutes an increasingly large portion of modern Systems on Chip (SoC). Since SRAM is the most common choice for these applications, it is considered as the focus of technology scaling. However, shrinking SRAM size is increasingly challenging due to a difficult control over process fluctuations, especially in sub-45 nm nodes [1]. Variability issues are exacerbated in this circuit block because the stringent area constraints induce conflicting requirements both at the single cell and system levels. The first trade-off is between the accurate matching of transistor pairs needed for correct functionality and the employment of minimum-size devices to reduce cell area. At the system level, typical yield requirements translate into extremely low failure probability specifications due to the large number of cells in modern arrays; unlike logic blocks, memory cannot even rely on self-averaging across multiple stages to mitigate these issues [2]. Threshold voltage (VT) variability mainly caused by random dopant fluctuations (RD) in bulk CMOS transistors is regarded as the main concern for SRAM stability [3]. Although alleviated by the recent introduction of high-j/metal gate (HK/MG) technology [4,5], this issue collides with scaling requirements for both voltage and doping. The dependence of SRAM static noise margin (SNM) on supply voltage has led to an improper VDD scaling to prevent cell instabilities in sub-100 nm technologies [6], as shown in Fig. 1. * Corresponding author. Tel.: +39 051 2093775; fax: +39 051 2093779. E-mail address: [email protected] (E. Baravelli). 0038-1101/$ - see front matter Ó 2010 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2010.04.035

Furthermore, the increasingly high doping concentration required to set the threshold in conventional MOSFETs is bound to exacerbate random dopant fluctuations. Therefore, alternative solutions are sought both to alleviated RD issues and to escape the current 1 V VDD plateau (Fig. 1). Replacing the planar transistor architecture with a multiplegate device is expected to provide considerable advantages. The fin-shaped Field Effect Transistor (FinFET) structure [7] is particularly attractive because of its improved immunity to both randomdopant-induced variability [8,9] and short-channel effects (SCE) [7]. Moreover, the use of a 3D architecture has the potential to increase area efficiency. The interest in FinFET-based SRAMs for the 32 nm node and beyond is confirmed by many experimental works [10–14]. TCAD simulations have been employed to investigate several design aspects, including circuit optimization and cell sizing [15–18], as well as crystal orientation [17,19]. Process variations in these papers have been mainly addressed through a SPICE-based approach including worst-case or sensitivity analysis [16,19]. Alternatively, mixed-mode device/circuit simulations have been performed with a simplified drift–diffusion model [17] and relatively small statistical ensembles [18] have been considered for Monte Carlo (MC) evaluation of SRAM variability. Fluctuation of the fin thickness in cell devices due to line-edge roughness (LER) is widely recognized as a major issue to the stability of FinFET SRAMs. Although a spacer-defined approach for fin patterning might reduce the LER, this technique still suffers from process maturity, cost and throughput concerns [20]. In addition to line-edge roughness, a new source of variability is emerging in

910

E. Baravelli et al. / Solid-State Electronics 54 (2010) 909–918

Fig. 2. 6T-SRAM cell schematic.

Fig. 1. Evolution of supply voltage in low-standby power (LSTP) applications [6].

technologies implementing HK/MG stacks, due to the dependence of the gate work-function (WF) on the orientation of metal grains which compose the gate electrode [21,22]. This might have severe circuit implications [21,23]. Our recent comparison of LER and work-function variability (WFV) in FinFETs with TiN gates highlighted a strong impact of the latter contribution on threshold voltage fluctuations, including a reduced mean value and considerably enhanced spread in VT distributions [24]. This paper is particularly focussed on line-edge roughness issues and aims to provide a systematic estimation of LER impact on the read and write stability of FinFET SRAMs as the supply voltage is scaled down, thus extending the work presented in [25]. Starting from a similar cell to those fabricated at IMEC [13], several design options are investigated, including cell sizing as well as the effects of crystal orientation and gate stack on FinFET mobility and threshold voltage. Sensitivity analysis was found to provide a poor representation of LER-induced fluctuations in device electrical parameters [26]: therefore, a statistical MC approach is adopted instead, which involves mixed-mode simulation of microscopically different cells. A quantum-corrected hydrodynamic model is used to improve accuracy of the resulting transfer curves. Moreover, statistical issues related to the sample size are addressed by (i) considering relatively large ensembles ranging from 200 up to 300 cells in each case and (ii) providing confidence intervals for the obtained results. Although WFV is not directly addressed in this work, the VT lowering effect associated to multiple metal grain orientations is partially included in the gate stack related analysis, while the restrictive criterion used for SRAM stability assessment precisely aims at providing relatively robust guidelines even in the presence of additional fluctuation sources, including WFV. The paper is organized as follows. Section 2 describes SRAM design constraints when using FinFETs and illustrates the considered scenarios. The simulation methodology and statistical approach are better elucidated in Section 3, where the impact of LER on cell devices with different features is also compared. Sections 4–6 present the effect of cell sizing, crystal orientation and gate stack choices on SRAM stability, while correlations between noise margins and geometrical fluctuations of cell devices are highlighted in Section 7. This provides design guidelines for mainstream employment of FinFET SRAMs in low-voltage/low-power applications at and beyond the 32 nm node, as summarized in Section 8. 2. FinFET SRAM design and stability issues The schematic of a 6-T SRAM cell is shown in Fig. 2. Stability during read operation is typically expressed in terms of the static noise margin (SNM) [27], which is defined as the minimum noise voltage needed to flip the cell state. Graphically, the SNM is represented by the edge of the largest square that can be inscribed be-

Fig. 3. Voltage transfer characteristics of a 6-T SRAM during read and write. Corresponding noise margins are indicated in the figure.

tween butterfly curves f1 and f2 shown in Fig. 3. Since the cell is generally not perfectly symmetric, the minimum between squares within the left and right portions of the curves is retained, i.e. SNM = min(SNML,SNMR). Conversely, a correct write operation consists in flipping the cell state: Therefore, write noise margin (WNM) is the minimum DC noise that prevents a state change and is measured as the width of the smallest square that can be embedded between the lower-right half of curves f1 and f3, or the upper-left half of f2 and f4, in Fig. 3 [28]. The minimum between these two possible choices is considered in asymmetric cells. To improve stability during read operation, driver transistors MnDR,i (see Fig. 2) are typically designed to be stronger than access FETs MnAX,i (i.e. cell ratio CR = bDR/bAX > 1). However, the CR cannot be set arbitrarily when using FinFETs with high aspect ratio, as the device width is quantized in multiples of the fin height. A common solution is to design driver transistors with two fins, while access and load FETs have one fin [16], but this leads to area penalty when fins are patterned through a resist-defined technique. Since area is critical in SRAMs, single-fins are often used even in driver devices [13], although this may penalize the SNM. In turn, access transistors should be more conductive than their load counterparts MpLD,i so that the correct value can be stored in the cell during write (i.e. pull-up ratio PR = bLD/bAX < 1). This is typically verified in bulk MOSFETs due to the lower mobility of p-channel w.r.t. n-channel devices in (1 0 0) conduction. However, sidewall transport in FinFETs occurs in the (1 1 0) plane whenever standard (1 0 0) wafers are used as a substrate. This is expected to enhance hole mobility while depressing electron mobility [29], thus affecting PR requirements. n-channel FinFETs (especially MnAX,i) are sometimes designed with 45°-rotated fins to recover (1 0 0) conduction and avoid WNM degradation, at the expense of a larger cell area and possibly enhanced process variations due to additional lithography difficulties [17]. However, sidewall transport is strongly influenced

E. Baravelli et al. / Solid-State Electronics 54 (2010) 909–918

911

by the fin patterning technique, including hard mask, corner rounding and H2 anneal, as well as the gate stack. Different process options may even lead to opposite trends for top/sidewall mobility ratios w.r.t. theory [30]. Moreover, implementation of the high-j/ metal gate stack in multi-gate devices is often challenging, posing difficulties to the accurate control of n- and p-FET VT. To account for different options in FinFET SRAM design, five scenarios have been considered, as described in Table 1. The basic building block of these circuits is a device with gate length Lg = 30 nm and fin width Wfin = 10 nm, as in fabricated cells [13]. The nominal FinFET was designed to achieve similar electrical performance to low standby power (LSTP) specifications for the 32 nm technology node [1] (VT,sat = 0.36 V, ION = 750 lA/lm for the n-type FET). The first SRAM (S1) has driver transistors with two fins and the same ln/lp ratio as in (1 0 0) conduction. This represents the best case for SRAM stability; the considered mobility conditions may be the result of fin rotation and/or the fin and gate formation process. The second cell (S2) is a minimum-area version of the former, with all single-fin devices. The impact of sidewall transport in the (1 1 0) plane is addressed in the third cell (S3) by decreasing ln and increasing lp in the low-field mobility model used for TCAD simulation [31]. Modifications w.r.t. standard (1 0 0) parameters have been made according to percentage mobility variations reported in [29]. The last two scenarios explore the impact of a lower threshold voltage (VT ’ 0.2 V, as in ITRS low operating power (LOP) specifications) on the cells with 1- and 2-fin driver FETs (S4 and S5, respectively), which might be either the result of a different gate stack and work function engineering or an unwanted consequence of WFV [24].

lines, i.e. VBL = VBLB = VDD for the read mode, VBL = VDD and VBLB = 0 V or vice-versa for write operation. As current driveability of each device in a cell contributes to setting the noise margins, a hydrodynamic model has been used to improve accuracy, while accounting for quantum effects through a density-gradient approximation (DGA). Mobility degradation in the presence of high electric fields has also been considered [31]. Nominal Ids–Vgs characteristics of single-fin devices used to build cells S2, S3 and S4 of Table 1 are shown in Fig. 4. In particular, it can be seen that the difference between (1 0 0) and (1 1 0) drive currents is attenuated at high Vds, due to velocity saturation phenomena [19]. Fig. 5a–e display butterfly curves obtained through mixed-mode simulation for the nominal cells S1–S5, respectively. The comparison of resulting SNMs in Fig. 5f indicates S1 as the most robust design, as expected, while S2, S3 and S5 exhibit a similar behavior; poor read stability is observed in cell S4. In order to evaluate the impact of line-edge roughness on the considered SRAM scenarios, a Fourier synthesis technique has been used to generate long LER sequences with the statistical properties of a gaussian autocorrelation process (rms amplitude D = 1.5 nm, correlation length K = 20 nm, in line with reported measurements [20,32] and with the ITRS guideline recommending the use of long lines (L > 2 lm) for LER characterization [1]). Although LER can affect several printed features in FinFETs, roughness of the fin edges was found to be the most critical source of electrical fluctuations in high aspect-ratio devices [9]. Therefore, the calculated LER sequences were subsequently split to define different fin shapes for the six transistors of each considered cell, resulting in FinFET instances similar to those in Fig. 6a and b for 1-fin and 2-fin devices, respectively. Pelgrom plots [33] in Fig. 7 illustrate the simulated impact of LER on electrical performance of cell transistors. Linear trends in this figure are due to the fact that the active device area is proportional to the number of fins. It can be seen that mobility modifications in the (1 1 0) case do not change the amount of relative fluctuations appreciably, while WF modulation emphasizes threshold voltage variability (Fig. 7a and b). Therefore, design S4 is expected to be especially vulnerable to LER issues due to a combination of small noise margins in the nominal cell and enhanced variability of individual devices.

3. Simulation approach and statistical analysis

3.2. Statistical assessment of SRAM stability

3.1. LER simulation at device and circuit level

SRAM instability is a source of yield loss in memory arrays. The maximum tolerated failure probability compatible with a target yield YT for SRAM matrices of size dim is calculated as

Table 1 Considered SRAM designs. Design

Driver FET sizing

Conduction

Nominal VT (V)

S1 S2 S3 S4 S5

2 1 1 1 2

(1 0 0) (1 0 0) (1 1 0) (1 0 0) (1 0 0)

0.36 0.36 0.36 0.2 0.2

fins fin fin fin fins

Mixed-mode device/circuit simulations [31] have been performed to compute voltage transfer characteristics for the considered cells. Typical bias conditions [3] have been applied to the bit

a

PFAIL ¼ ð1  Y T Þ=dim

ð1Þ

b

Fig. 4. Simulated Ids–Vgs characteristics in (a) linear and (b) saturated regime of n- and p-type single-fin devices used for SRAM cells. ‘‘(1 1 0)” curves were obtained by modifying mobility models to emulate sidewall conduction, while ‘‘mod. WF” curves present a lower threshold voltage due to work function modulation.

912

E. Baravelli et al. / Solid-State Electronics 54 (2010) 909–918

a

b

c

d

e

f

Fig. 5. (a)–(e) Nominal butterfly curves of cells S1–S5 (Table 1), at VDD = 1 V, 0.8 V and 0.6 V. (f) Comparison of resulting static noise margins.

Fig. 6. Instances of (a) single-fin and (b) 2-fin devices with fin-LER (D = 1.5 nm, K = 20 nm).

In this work, a tight target YT = 99.9% and a large SRAM size dim = 10 Mbit are assumed for evaluation of modern SoC applications [34,35], resulting in a very strict failure specification PFAIL = 1010. Considering the read operation, this requirement can be used to set a tolerance margin TM for SNM statistics, such that [36]:

lSNM  TM  rSNM P SNMcrit

ð2Þ

where lSNM and rSNM represent the mean and standard deviation of SNM, respectively, while SNMcrit is the onset of cell instability. Assuming a gaussian distribution for the static noise margin, PFAIL = 1010 corresponds to TM = 6.4, i.e. the probability to find an

SRAM cell with a SNM smaller than lSNM  6.4rSNM is less than PFAIL. Since a read failure is characterized by a negative SNM value, SNMcrit = 0 V is commonly assumed [34]. However, in our analysis this parameter was set to 4%VDD, following [37]. This provides a safer guideline, while identifying a supply voltage dependent critical zone 0 V < SNM < 4%VDD where SRAM stability is not guaranteed, especially in the presence of additional fluctuation sources (e.g. WFV) beside the considered ones. As a low failure probability corresponds to a far tail of the SNM distribution, very large MC ensembles should be considered to achieve sufficient accuracy. In our approach the sample size varies between 200 and 300 cells, which is larger than commonly

E. Baravelli et al. / Solid-State Electronics 54 (2010) 909–918

a

b

c

d

913

Fig. 7. LER-induced variability of (a) and (c) n-type and (b) and (d) p-type FinFETs used to build cells S2 ((1 0 0) conduction), S3 ((1 1 0) conduction) and S4 (lower VT due to WF modification) in Table 1. Variability is expressed as the ratio between standard deviation r and mean value l of (a) and (b) saturation threshold voltage VT,sat and (c) and (d) on-state current ION. Statistics is based on ensembles ranging from 200 up to 300 devices.

reported for mixed-mode simulations [18], but still quite small for MC extrapolation down to 6.4r. Further increasing the ensemble size was not possible due to computational resources limitations; instead, confidence intervals (CI) have been calculated to compensate for statistical noise in SNM mean and variance estimation. A conventional formula based on the Student’s t distribution [38] has been used to compute CI for lSNM:

CI1a ½lSNM  ¼ lSNM  t a=2 rl

ð3Þ

where ta/2 is the critical two-tailed value of the t distribution with N  1 degrees of freedom (being N the ensemble size) pffiffiffiffi and the standard deviation of lSNM is estimated as rl ¼ rSNM = N . a represents the accepted tolerance; in this work, 95% confidence intervals have been considered, i.e. a = 0.05. As errors in the estimation of SNM variance can severely affect l  6.4r statistics, a more careful approach has been adopted for this parameter, in order to account for deviations from normality in the SNM distribution. By exploiting Eq. (4) in [39], a 95% confidence interval for rSNM is obtained, which should be robust under moderate nonnormality even for small samples:

CI1a ½rSNM  ¼

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2 elnðcrSNM Þza=2 se

ð4Þ

In (4), a variance-stabilizing logarithmic transformation is adopted; za/2 is the two-sided critical z-value, se and the small sample adjustment parameter c are given by

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi N3 ; se ¼ c c4  NðN  1Þ

c¼

N N  za=2

better normality properties. However, these works are based on SPICE simulation, thus allowing for larger (>1 K) ensemble sizes. We did not follow this approach because we observed, both from our experiments and from [41], that it can lead to overly pessimistic results with only few hundreds of data, since SNML and SNMR have a larger variance than SNM. Nevertheless, one of the simulated datasets has been extended to over 1000 cells to verify consistency of confidence interval estimation based on smaller sample sizes. It can be seen from Fig. 8 that, even with additional simulations, l  6.4r statistics of SNM remains within the computed CI at N = 200. As expected, increasing N to 300 cells provides a reduced uncertainty. The combination of (i) SNMcrit choice, (ii) use of the largest ensemble sizes allowed by computational resources, and (iii) definition of confidence intervals is believed to result in a sufficiently robust statistical approach to compare stability properties of the considered SRAM designs under the influence of line-edge roughness. The same methodology described for the SNM has been applied to WNM when analyzing write operation of these cells.

4. LER impact vs. cell sizing Design options S1 and S2 are first compared to investigate robustness to LER for SRAMs with different cell ratios. Simulated

ð5Þ

where the kurtosis is estimated as

PN

c4 ¼ N P

i¼1 ðSNMi

N i¼1 ðSNMi

 mÞ2

 lSNM Þ2

2

ð6Þ

being m ffia trimmed mean of SNMi with trim proportion pffiffiffiffiffiffiffiffiffiffiffiffi 1=ð2 N  4Þ. Some authors [34,40] compensate for the non-gaussian behavior of SNM by remapping PFAIL into an equivalent failure probability for the left or right static noise margins enclosed by the two eyes of butterfly curves, i.e. SNML, SNMR, which are expected to exhibit

Fig. 8. l  6.4r of SNM for design S2 at VDD = 1 V, plotted as a function of the ensemble size. The dashed lines indicate confidence intervals truncated at N = 200 and N = 300 cells.

914

E. Baravelli et al. / Solid-State Electronics 54 (2010) 909–918

transfer characteristics at VDD = 1 V are reported in Fig. 9, together with WNM and SNM histograms and corresponding gaussian fits. The spread in both butterfly curves and histograms reveal an enhanced variability for the cells with single-fin driver FETs. This is mainly caused by the smaller area, and hence larger electrical fluctuations, of these devices w.r.t. their 2-fin counterparts, as shown by Pelgrom plots in Fig. 7. SNM statistics in the hold mode of cell operation was found to be mostly determined by variations in driver transistors [42]: Fig. 9 indicates a strong SRAM sensitivity to LER in these devices during read operation as well. Mean value and spread of SNM histograms in Fig. 9b and d indicate how the outlined enhanced variability further degrades the inherently poorer stability of S2 cells due to a smaller CR w.r.t. S1 design. As a result, SRAM arrays with all single-fin devices may not comply with yield requirements when operated at 1 V supply voltage.

a

b

c

d

Fig. 10 provides a quantitative assessment of these considerations and shows the effect of VDD scaling. Mean value, standard deviation and l  6.4r statistics of both SNM and WNM are plotted in this figure as a function of VDD for the considered design cases. Error bars represent 95% confidence intervals calculated as described in Section 3.2 (bars for the mean noise margin values in Fig. 10a and d are hardly visible due to the very small relative amplitude of corresponding intervals). As expected, l  6.4r statistics of SNM for minimum-area cells S2 is found to lay in the highlighted critical zone at VDD = 1 V (see Fig. 10c). However, it can also be inferred from this figure that supply voltage scaling allows S2 SRAMs to recover sufficient read stability; statistical noise is not expected to compromise this prediction. Fig. 10d–f indicate that write operation of these cells is not significantly affected by LER issues. On the other hand, design S1 exhibits a satisfactory

Fig. 9. (a) and (c) Butterfly curves of SRAMs with 2-fin and 1-fin driver FETs. (b) and (d) Resulting WNM and SNM histograms. All cell FinFETs have fin-LER with D = 1.5 nm, K = 20 nm.

a

b

c

d

e

f

Fig. 10. Mean value and standard deviation of SNM (a) and (b) as well as WNM (d) and (e) as a function of VDD, for cases S1 and S2. (c) and (f) Corresponding l  6.4r statistics. Error bars represent 95% confidence intervals, while the highlighted region in (c) is the critical zone bounded by 4%VDD.

E. Baravelli et al. / Solid-State Electronics 54 (2010) 909–918

behavior in both read and write mode within the considered supply voltage range. Therefore, FinFET SRAMs with 2-fin drivers represent a safe design option; nevertheless, single-fin drivers can also be used to improve cell area in low-voltage applications.

5. LER impact vs. mobility changes due to crystal orientation and gate stack Accurate assessment of top and sidewall carrier mobility in FinFETs is difficult as this quantity is influenced by many factors. For example, the fin patterning technique often results in surface roughness of the sidewalls, whose magnitude is related to the hard mask used. Depending on the process (e.g. H2 anneal or soft sputter etch), corner rounding can smoothen this roughness, but also damage the top surface, thus changing mobility in the two transport planes. The composition of dielectric stack further influences ln and lp. Although carrier mobility is expected to change significantly in (1 1 0) vs. (1 0 0) crystal orientation [29], several measurements reveal a smaller variation as a result of the outlined causes [30]. Moreover, the corresponding change in device current is much weaker, especially at high Vds, as shown in Fig. 4. The impact of fin-LER on the stability of SRAMs featuring singlefin devices with (1 0 0) and (1 1 0) carrier transport is compared in Fig. 11. In particular, Fig. 11a and b indicate that the enhanced strength of p-type FETs in (1 1 0) conduction slightly increases the mean SNM, without significantly affecting its standard deviation. This improves l  6.4r statistics of the SNM in cells S3, providing better read stability even at VDD = 1 V, although the lower bound of the corresponding confidence interval still crosses the critical zone in Fig. 11c. As a trade-off, WNM statistics is degraded by the stronger pull-up vs. access devices, as shown in Fig. 11d–f, but overall write operation is not severely affected. It is therefore concluded that sidewall conduction may improve, rather than compromise, SRAM stability, since the measured change in Id,n/Id,p ratio w.r.t. (1 0 0) conduction is typically slighter than theoretical ln/lp modifications. This helps relaxing supply voltage constraints. Confidence on simulation results is boosted by the observation of a good agreement between lSNM values in Fig. 11a and measurements performed on fabricated SRAMs [13] featuring single-fin devices with Lg = 30 nm, Wfin = 10 nm.

915

6. LER impact vs. threshold voltage of cell devices The relatively high threshold voltage (VT ’ 0.36 V) of devices in SRAMs S1–S3 is suitable for low standby power applications. The impact of a lower VT, compatible with ITRS-LOP specifications [1], has been investigated in the last two design scenarios by tuning the WF of cell transistors, while keeping the same mobility as in cases S1 and S2. This may be practically obtained through a different gate stack; besides, this analysis provides some hints on LER impact in adverse situations where threshold voltage lowering is an undesired effect produced by metal granularity. Butterfly curves reported in Fig. 12a for SRAMs S4 with all single-fin devices indicate LER-induced read instability at VDD = 1 V. For example, transfer characteristics of a failing cell are highlighted in the figure. The unacceptable SNM degradation due to a lower transistor threshold w.r.t. case S2 is confirmed by histograms in Fig. 12b. Looking at the impact of supply voltage scaling in Fig. 13, it is clear that these cells cannot achieve sufficient yield within the considered VDD range. However, lowering the operating voltage rapidly improves SNM statistics, allowing the l  6.4r figure of merit to cross the 0 V boundary between failure and critical zone at VDD = 0.6 V, as shown in Fig. 13c. Therefore, further VDD reduction might provide sufficient read margins for cells S4, although extrapolation from Fig. 13f suggests that difficulties could start to arise during write operation. In order to improve the read performance of FinFET SRAMs for low operating power applications, the cell ratio has been increased by doubling the number of fins in driver transistors (S5 design). The benefits of this approach are evident from butterfly curves in Fig. 12c. The corresponding SNM distribution at VDD = 1 V is shifted to considerably higher values, although not as high as those provided by cells S1 with 2-fin drivers and larger VT (see Fig. 12d). Statistical noise due to the limited MC ensemble does not allow reaching 95% confidence on safe read operation for design S5 at VDD = 1 V, as indicated by error bars in Fig. 14c. However, supply voltage scaling is found to provide sufficient SNM and the read performance of these cells becomes comparable to that of their highVT counterparts S1 at VDD = 0.6 V. Although the WNM is negatively influenced by the stronger pull-down devices in SRAMs S5, Fig. 14f suggests that write oper-

a

b

c

d

e

f

Fig. 11. Mean value and standard deviation of SNM (a) and (b) as well as WNM (d) and (e) as a function of VDD, for cases S2 and S3. (c) and (f) Corresponding l  6.4r statistics. Error bars represent 95% confidence intervals, while the highlighted region in (c) is the critical zone bounded by 4%VDD. Measurements performed on fabricated cells [13] are also reported in (a) for comparison.

916

E. Baravelli et al. / Solid-State Electronics 54 (2010) 909–918

a

b

c

d

Fig. 12. (a) Butterfly curves of S4 cells affected by LER. A read failure is highlighted. (b) SNM histograms at VDD = 1 V for S4 and S2 SRAMs. (c) Butterfly curves of S5 cells affected by LER. One case with relatively small WNM is highlighted. (d) SNM histograms at VDD = 1 V for S5 and S1 SRAMs.

a

b

c

d

e

f

Fig. 13. Mean value and standard deviation of SNM (a) and (b) as well as WNM (d) and (e) as a function of VDD, for cases S2 and S4. (c) and (f) Corresponding l  6.4r statistics. Error bars represent 95% confidence intervals. Highlighted in (c) are the critical zone bounded by 4%VDD and the failure region l  6.4r < 0 V.

ation should not be compromised. Nevertheless, sensitivity to LER is considerably enhanced for these cells and WNM distributions exhibit strongly non-gaussian features. For example, a few corner cases, featuring access devices with extremely pronounced thinning of the fin down to 2 nm, are responsible for anomalous transfer curves like the ones highlighted in Fig. 12c. This is the reason for the large error bars of S5 WNM statistics in Fig. 14e and f. The impact of anomalous cells on write operation is, however, reduced when VDD is lowered, as indicated by the decreasing amplitude of confidence bounds. Scaling down the device threshold is thus seen to dangerously affect read stability of SRAM cells due to fin-LER. However, sufficient SNM can be achieved at the expense of a larger cell area with 2-fin drivers. Although requiring a careful trade-off between read and write margins, this allows successful application of FinFETs in LOP SRAM technologies.

7. SRAM correlation analysis Monte Carlo assessment of LER-induced instability in SRAMs is extremely expensive from the computational standpoint and alternative approaches would be preferred. Intrinsic parameter fluctuations in FinFETs were shown to be highly related to representative geometrical quantities. In particular, a strong correlation was found between the threshold voltage and the average fin width in the channel (hWfin ich) of these devices [9]. Moreover, an equivalent fin width Wequiv was determined, based on a weighted sum of thicknesses in some key points of the fin, which provided a significant correlation to drain current in each FinFET instance [26]. Therefore, further investigations have been carried on to check for possible correlations between SRAM noise margins and meaningful combinations of these parameters in cell devices.

E. Baravelli et al. / Solid-State Electronics 54 (2010) 909–918

a

b

c

d

e

f

917

Fig. 14. Mean value and standard deviation of SNM (a) and (b) as well as WNM (d) and (e) as a function of VDD, for cases S1 and S5 (respectively, high-VT and low-VT SRAMs with 2-fin drivers). (c) and (f) Corresponding l  6.4r statistics. Error bars represent 95% confidence intervals, while the highlighted region in (c) is the critical zone bounded by 4%VDD.

a

b

Fig. 15. (a) SNMR as a function of CRequiv,1 at VDD = 1 V, for designs S2 and S4. (b) Correlation coefficient of SNMR vs. CRequiv,1 for designs S2 and S4, as a function of VDD.

Several analytical models have been proposed in literature for the SNM, all of which exhibiting complicated dependencies on various parameters of cell transistors [27,43]. However, it is known that read stability is particularly related to the cell ratio, which depends on driveability of the pull-down and access FETs (see Section 2). As drain current fluctuations due to LER can be approximately described by the equivalent fin width Wequiv, corresponding changes in the CR of each SRAM instance are expected to be related to the ratio of the values assumed by this parameter for the driver and access FinFETs, respectively. Therefore, an equivalent cell ratio has been defined as

CRequiv ;i ¼ W equiv ;DR;i =W equiv ;AX;i

ð7Þ

whose value in each half-cell should be related to the noise margin extracted from the corresponding portion of butterfly curves, i.e. SNML and SNMR. Scatter plots of SNMR as a function of CRequiv,1 at VDD = 1 V are shown in Fig. 15a for designs S2 and S4. The correlation is found to be significant both for the high-VT and low-VT cases, thus highlighting one of the basic mechanisms through which the fin roughness affects SRAM stability. However, the spread is still quite large, especially at the tails of the distributions. Similar trends have been observed in SNML vs. CRequiv,2 plots. Therefore, SNM estimation based on corner data, following a similar approach as the one de-

scribed in [9,26] for device-level variability, would not provide acceptable accuracy. Moreover, Fig. 15b shows that the correlation rapidly decreases as the supply voltage is scaled down. This indicates that the way LER affects SRAM performance is strongly dependent on VDD: while drive current fluctuation in MnDR,i and MnAX,i is the dominant issue at relatively high operating voltages, other factors come into play as VDD is decreased, as also confirmed by the changing shapes of butterfly curves in Fig. 5, making the dependence of cell stability on geometrical variations more complicated. Even though more sophisticated combinations of representative device parameters are being investigated, feasibility of the correlation approach for SRAM variability analysis is probably undermined by the outlined supply voltage influence.

8. Conclusions Read stability as well as write-ability of FinFET-based SRAMs, suitable for low-voltage/low-power applications at the 32 nm technology node, have been extensively investigated in the presence of line-edge roughness. Noise margins at different supply voltages have been evaluated through mixed mode simulations coupled with Monte Carlo statistical analysis of relatively large ensembles (200–300 cells each). Several design options, related to cell sizing, crystal orientation and gate stack, have been com-

918

E. Baravelli et al. / Solid-State Electronics 54 (2010) 909–918

pared based on a restrictive criterion for 99.9% yield in 10 Mbit SRAM arrays, providing confidence bounds to compensate for statistical noise. It was found that LSTP-compatible cells with relatively high device VT of 0.36 V exhibit satisfactory read and write stability when driver FETs are designed with two fins. Instead, optimizing SRAM area through single-fin pull-down transistors is not expected to provide sufficient yield at VDD = 1 V. Acceptable read margins are however recovered at lower supply voltages, indicating FinFET as a good candidate for minimum-size SRAMs operating at low VDD. Sidewall transport on the (1 1 0) plane in these devices is not predicted to compromise cell stability. Depending on fin patterning and gate stack formation as well as velocity saturation phenomena, effective changes in Id,n/Id,p ratio w.r.t. (1 0 0) conduction can be much smaller than theoretical mobility modifications, thus resulting in a similar variability of both individual devices and SRAM circuits due to LER. Read upsets are instead observed when VT is tuned down to 0.2 V through work function engineering, in order to make minimum-area cells suitable for LOP applications. This is due to the combination of a degraded read performance of the nominal cell and enhanced LER-induced variability in devices with low threshold voltage. Increasing the cell ratio through upsized driver FETs with two fins is essential to recover read stability and should also provide considerable mitigation of work-function variability associated to metal gate granularity, VT lowering being one of the undesired consequences of this issue. Although the WNM is sensibly reduced in the last two design cases, write operation is not expected to be compromised by LER with any of the considered SRAM options. A correlation analysis indicated that SNM dependence on the variability of individual cell transistors becomes more and more complicated as VDD is scaled down. This undermines the exploration of correlation-based alternatives to the expensive MC approach for the estimation of LER issues in these circuit blocks. Nevertheless, lowering the supply voltage was seen to be beneficial for SRAM stability down to 0.6 V. Our simulation results are in a good agreement with measurements performed on fabricated cells with similar features and demonstrate good VDD scalability of FinFET SRAMs even in the presence of fin-LER-induced fluctuations. Acknowledgments The authors would like to thank Malgorzata Jurczak and Nadine Collaert for their support. References [1] ITRS 2007 Edition. . [2] Chang L, Fried DM, Hergenrother J, et al. Stable SRAM cell design for the 32 nm node and beyond. In: VLSI tech dig; 2005. p. 128–9. [3] Cheng B, Roy S, Asenov A. CMOS 6-T SRAM cell design subject to ‘‘atomistic” fluctuations. Solid-State Electron 2007;51(4):565–71. [4] Mistry K, Allen C, Auth C, et al. A 45 nm logic technology with High-k+metal gate transistors, strained silicon, 9 Cu interconnect layers, 193 nm dry patterning, and 100% Pb-free packaging. In: IEDM tech dig; 2007. p. 247–50. [5] Arnaud F, Liu J, Lee YM, et al. 32 nm general purpose bulk CMOS technology for high performance applications at low voltage. In: IEDM tech dig; 2008. [6] Skotnicki T, Fenouillet-Beranger C, Gallon C, et al. Innovative materials, devices, and CMOS technologies for low-power mobile multimedia. IEEE Trans Electron Dev 2008;55(1):96–130. [7] Yu B, Chang L, Ahmed S, et al. FinFET scaling to 10 nm gate length. In: IEDM tech dig; 2002. p. 251–4. [8] Cathignol A, Cros A, Harrison S, et al. High threshold voltage matching performance on gate-all-around MOSFET. In: Proc ESSDERC; 2006. p. 379–82. [9] Baravelli E, Jurczak M, Speciale N, De Meyer K, Dixit A. Impact of LER and random dopant fluctuations on FinFET matching performance. IEEE Trans Nanotechnol 2008;7(3):291–8. [10] Kawasaki H, Okano K, Kaneko A, et al. Embedded bulk FinFET SRAM cell technology with planar FET peripheral circuit for hp32 nm node and beyond. In: VLSI tech dig; 2006.

[11] Kawasaki H, Khater M, Guillorn M, et al. Demonstration of highly scaled FinFET SRAM cells with high-j/metal gate and investigation of characteristic variability for the 32 nm node and beyond. In: IEDM tech dig; 2008. [12] Endo K, Ouchi S, Ishikawa Y, et al. Independent-gate four-terminal FinFET SRAM for drastic leakage current reduction. In: Proc. ICICDT, June 2008. p. 63– 6. [13] Collaert N, von Arnim K, Rooyackers R, et al. Low-voltage 6T FinFET SRAM cell with high SNM using HfSiON/TiN gate stack, fin widths down to 10 nm and 30 nm gate length. In: Proc ICICDT, June 2008. p. 59–62. [14] Veloso A, Demuynck S, Ercke M, et al. Full-field EUV and immersion lithography integration in 0.186 lm2 FinFET 6T-SRAM cell. In: IEDM tech dig; 2008. [15] Song SC, Abu-Rahma M, Han BM, et al. Systematic approach of FinFET based SRAM bitcell design for 32 nm node and below. In: Proc ICICDT, May 2009. p. 165–8. [16] Lekshmanan D, Bansal A, Roy K. FinFET SRAM: optimizing silicon fin thickness and fin ratio to improve stability at iso area. In: Proc CICC; 2007. p. 623–26. [17] Guo Z, Balasubramanian S, Zlatanovici R, King TJ, Nikolic B. FinFET-based SRAM design. In: Proc ISLPED, August 2005. p. 2–7. [18] Yu S, Zhao Y, Du G, et al. The impact of line edge roughness on the stability of a FinFET SRAM. Semicond Sci Technol 2009;24(2). [19] Gangwal S, Mukhopadhyay S, Roy K. Optimization of surface orientation for high-performance, low-power and robust FinFET SRAM. In: Proc CICC; 2006. p. 433–6. [20] Baravelli E, Dixit A, Rooyackers R, et al. Impact of line-edge roughness on FinFET matching performance. IEEE Trans Electron Dev 2007;54(9):2466–74. [21] Dadgour H, De V, Banerjee K. Statistical modeling of metal-gate work-function variability in emerging device technologies and implications for circuit design. In: Proc ICCAD; 2008. p. 270–7. [22] Matsukawa T, O’uchi S, Endo K, et al. Comprehensive analysis of variability sources of FinFET characteristics. In: VLSI tech dig; 2009. p. 118–9. [23] Zhang X, Li J, Grubbs M, et al. Physical model of the impact of metal grain work function variability on emerging dual metal gate MOSFETs and its implications for SRAM reliability. In: IEDM tech dig; 2009. p. 3.4.1–4. [24] Baravelli E, De Marchi L, Speciale N. Physical insight and Monte Carlo statistical analysis of work-function variability in FinFETs based on 2D slice composition. In: Proc ULIS; 2010. p. 49–52. [25] Baravelli E, De Marchi L, Speciale N. LER-induced limitations to VDD scalability of FinFET-based SRAMs with different design options. In: Proc ESSDERC; 2009. p. 415–8. [26] Baravelli E, De Marchi L, Speciale N. Fin shape fluctuations in FinFET: correlation to electrical variability and impact on 6-T SRAM noise margins. Solid-State Electron 2009;53(12):1303–12. [27] Seevinck E, List FJ, Lohstorn J. Static-noise margin analysis of MOS SRAM cells. IEEE J Solid-State Circ 1987;SC-22(5):748–54. [28] Wang W, Nalam S, Calhoun BH. Analyzing static and dynamic write margin for nanometer SRAMs. In: Proc ISLPED, August 2008. p. 129–34. [29] Yang M, Gusev EP, Ieong M, et al. Performance dependence of CMOS on silicon substrate orientation for ultrathin oxynitride and HfO2 gate dielectrics. IEEE Electron Dev Lett 2003;24(5):339–41. [30] Iyengar VV, Kottantharayil A, Tranjan FM, Jurczak M, De Meyer K. Extraction of the top and sidewall mobility in FinFETs and the impact of fin-patterning processes and gate dielectrics on mobility. IEEE Trans Electron Dev 2007;54(5):1177–84. [31] Sentaurus device manual version Z-2007.3. Synopsys, Inc. [32] Asenov A, Kaya S, Brown AR. Intrinsic parameter fluctuations in decananometer MOSFETs induced by gate line edge roughness. IEEE Trans Electron Dev 2003;50(5):1254–60. [33] Pelgrom AJM, Duinmaijer ACJ, Welbers APG. Matching properties of MOS transistors. IEEE J Solid-State Circ 1989;24(5):1433–40. [34] Doorn TS, ter Maten EJW, Croon JA, Bucchianico AD, Wittich O. Importance sampling Monte Carlo simulations for accurate estimation of SRAM yield. In: Proc ESSCIRC; 2008. p. 230–3. [35] Mérelle T, Curatola G, Nackaert A, et al. First observation of FinFET specific mismatch behavior and optimization guidelines for SRAM scaling. In: IEDM tech dig; 2008. [36] Grossar E, Technology-aware design of SRAM memory circuits. Ph.D. dissertation. Katholieke Universiteit Leuven; 2007. [37] Stolk PA, Tuinhout HP, Duffy R, et al. CMOS device optimization for mixedsignal technologies. In: IEDM tech dig; 2001. p. 10.2.1–4. [38] Sheskin DJ. Handbook of parametric and nonparametric statistical procedures. 3rd ed. Chapman & Hall/CRC; 2003. [39] Bonett DG. Approximate confidence interval for standard deviation of nonnormal distributions. Comput Stat Data Anal 2006;50(3):775–82. [40] Lu DD, Lin CH, Yao S, et al. Design of FinFET SRAM cells using a statistical compact model. In: Proc SISPAD, September 2009. [41] Calhoun BH, Chandrakasan AP. Static noise margin variation for sub-threshold SRAM in 65-nm CMOS. IEEE J Solid-State Circ 2006;41(7):1673–9. [42] Baravelli E, Speciale N, Dixit A, Jurczak M. TCAD modeling and characterization of short-range variations in multiple-gate devices and circuit blocks. In: 15th int conf on mixed design (MIXDES), June 2008b. p. 85–90. [43] Bhavnagarwala AJ, Tang X, Meindl JD. The impact of intrinsic device fluctuations on CMOS SRAM cell stability. IEEE J Solid-State Circ 2001;36(4):658–65.