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Wafer level Cu–Cu direct bonding for 3D integration
Microelectronic Engineering xxx (2015) xxx–xxx
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Wafer level Cu–Cu direct bonding for 3D integration Sarah Eunkyung Kim a, Sungdong Kim b,⇑ a b
Graduate School of NID Fusion Technology, Seoul National University of Science and Technology, Seoul 139-743, Republic of Korea Dept. of Mechanical System Design Eng., Seoul National University of Science and Technology, Seoul 139-743, Republic of Korea
a r t i c l e
i n f o
Article history: Received 1 July 2014 Received in revised form 31 October 2014 Accepted 18 December 2014 Available online xxxx Keywords: 3D IC Wafer-to-wafer Wafer level stacking Warpage Thermo-compression bonding
a b s t r a c t Wafer level bonding and stacking process for 3D stacked IC was proposed and technical issues were discussed. Cu bumps surrounded by recessed SiO2 were thermo-compression bonded and electrically evaluated using Kelvin structures. Defects at the bonding interface such as voids were responsible for electrical resistance distribution. Wafer alignment during stacking process was found to be affected by several factors like non-uniform bump height, the spacers in a bonding fixture and wafer warpage. Step by step warpage measurement revealed that the wafer warpage was dependent on process steps and worsened at bonding step. Ó 2014 Elsevier B.V. All rights reserved.
1. Introduction Semiconductor industry has been focusing on downscaling transistors for high performance, small form factor and low production costs. Moore’s law representing these efforts, however, is facing its limit recently as transistor has been scaled down to its physical limit. A lot of efforts such as improving photolithography like EUV [1] or adopting new materials like CNT [2], are underway to keep Moore’s law continue but there are many complications that must be solved before implementing these technologies. As shrinking transistor in two dimensional area becomes difficult, building up chips into three dimension was proposed as a solution. 3D stacked IC can take advantages of small form factor and high performance by stacking chips vertically and shortening interconnection length with through silicon via (TSV), respectively. Since the idea of 3D stacked IC was first proposed, there have been many research activities on TSV fabrication technologies, for example, etching holes having high aspect ratio [3], uniform deposition of seed/barrier material, filling up the holes without defects [4]. However, recent research focus has been moved to reliability issues such as TSV stress [5] and thermal management [6] as well as design and test issues [7]. This movement implies that 3D stacked IC is ready for mass production phase. Before mass production of 3D stacked IC becomes mainstream, there are several technical and reliability concerns that must be solved, for instance, thin wafer handling and wafer bonding and stacking. Especially, ⇑ Corresponding author. E-mail address: [email protected] (S. Kim).
wafer bonding and stacking are a key technology for building up chips in three dimension. While there are many options for wafer bonding, for example, direct wafer bonding [8], surface activated bonding (SAB) [9], Cu–Cu thermo-compression bonding [10], solid liquid inter-diffusion bonding (SLID) [11] and metal/dielectric hybrid bonding [12], it becomes important to achieve low bonding temperature and to use Cu as a main bonding material. As for stacking method, there are three ways of stacking chips; chip-to-chip, chip-to-wafer, wafer-to-wafer. Due to technical accessibility and yield issue, chipto-chip stacking process is now popular in semiconductor industry, but wafer-to-wafer stacking approach is inevitable for a mass production. In this paper, we assessed various technical issues in the waferto-wafer stacking process where direct Cu–Cu thermo-compression bonding was applied. Misalignment between stacked wafers was critical for high manufacturing yield and origin of misalignment was investigated using specially designed wafer sets. Overall bonding quality was evaluated and mapped by measuring electrical resistance of bonded bumps. 2. Experimental procedure Substrate preparation and bonding process were illustrated in Fig. 1 where it should be noted that wafers were face-to-face bonded prior to thinning process. After the bonding process, TSV wafer could be thinned without temporary bonding/debonding (TBDB) since substrate wafer could play a role of carrier wafer. This approach could reduce the number of process steps by removing
http://dx.doi.org/10.1016/j.mee.2014.12.012 0167-9317/Ó 2014 Elsevier B.V. All rights reserved.
Please cite this article in press as: S.E. Kim, S. Kim, Microelectron. Eng. (2015), http://dx.doi.org/10.1016/j.mee.2014.12.012
2
S.E. Kim, S. Kim / Microelectronic Engineering xxx (2015) xxx–xxx
Fig. 1. Wafer level stacking process flow.
TBDB and increase the yield by solving thin wafer handling issues. When required, more wafers can be back-to-face stacked on top of this bonded wafer set [13]. As shown in Fig. 1, two types of 8 inch Si wafers were prepared; one is substrate wafer and the other is TSV wafer. Cu redistribution line (RDL) and bumps were fabricated on both wafers by lift off and damascene process, respectively. Fig. 2(a) and (b) shows Cu RDL and bump images, where bump diameter was 50 lm and bump pitch was 200 lm. All Cu layers have underlying Cr buffer layer for adhesion improvement. TSVs of 8 lm diameter were fabricated through conventional preparation sequences, i.e., via formation by deep reactive ion etching
(DRIE) followed by sputtering Cu seed layer and via filling by electro-deposition of Cu. After Cu bump fabrication was completed, two wafers were cleaned by immersion in diluted H2SO4 solution to remove surface Cu oxide and bonded in a wafer bonder (SB8e, SUSS Microtec) using Cu–Cu thermo-compression bonding technique. Bonding temperature was 415 °C and bonding pressure was 890 kPa. Subsequent vacuum annealing process was performed at 450 °C for 1 h. It should be noted that SiO2 layers were recessed by wet treatment prior to the bonding step, which guaranteed Cu–Cu contact and not Cu–SiO2 or SiO2–SiO2 contact [14]. TSV wafer in the bonded wafers was thinned down to around
Please cite this article in press as: S.E. Kim, S. Kim, Microelectron. Eng. (2015), http://dx.doi.org/10.1016/j.mee.2014.12.012
S.E. Kim, S. Kim / Microelectronic Engineering xxx (2015) xxx–xxx
(a)
(b)
(c)
(d)
3
Fig. 2. Optical and SEM images of (a) Cu RDL and bumps on substrate wafer (b) Cu bumps on TSV wafer (c) TSVs revealed after grinding/DRIE process and (d) schematic diagram of Kelvin structure.
30 lm using a wafer grinder (DGP8760, Disco) and DRIE (MUG21, STS) in sequence, and the Cu vias were revealed as shown in Fig. 2(c). On top of this thinned TSV wafer, Cu pads were prepared by sputtering and lift off processes for an electrical resistance measurement using Kelvin (Fig. 2(d)) and daisy chain structure. Wafer warpage was measured at each process step by multi-beam optical sensor (MOS ultra scan, kSA). Bonding interface was observed by focused ion beam (FIB) and scanning electron microscopy (SEM). 3. Results and discussion 3.1. Gap filling and CMP In the chip-to-chip stacking process, conventional underfill is usually applied to fill the gap between bumps due to mechanical and thermal reasons. However, this underfill cannot be dispensed for wafer-to-wafer stacking geometry, since capillary force is too weak to suck underfill from wafer edge to center. We prepared a bonded wafers set having an air gap between Cu bumps (Fig. 3(a)) and this air gap was observed to induce a pop-up breakage of thin TSV wafer in the vacuum process subsequent to the bonding step (see an example in Fig. 3(b)). As a gap filling material, polymers like BCB or dielectrics like SiO2 were attempted by other researches [15]. In this study, silicon oxide was selected due to its high temperature compatibility but it requires a damascene process and simultaneous SiO2–SiO2/Cu–Cu bonding which strongly depends on a chemical mechanical polishing (CMP) process.
According to our previous result [16], surface roughness should be less than 10 nm for a successful Cu–Cu bonding. A combination of Cu and SiO2 CMP followed by wet treatment turned out to be effective in controlling Cu dishing and the surface roughness [17]. 3.2. Misalignment between stacked wafers Compared with chip-to-chip stacking approach, misalignment between stacked wafers gives rise to serious yield problem in wafer-to-wafer stacking method. We speculated that misalignment during bonding process could be caused by (1) non-uniform bump height, (2) removal of spacers in a bond fixture and (3) wafer warpage. Effects of each factors were illustrated in Fig. 4 and examined by (1) preparing controlled bump height uniformity, (2) bonding without spacers, and (3) enhancing warpage by inserting additional Cu layer, respectively. In case of uniform (2–3% variation) bump height samples, only rotational misalignment was observed while non-uniform bump samples showed complex behavior of slip and rotational misalignment. Non-uniformity of bump height was generally induced by CMP and wafer thinning process. Without the spacers, misalignment was hardly observed [18]. However, misalignment by the spacers could not completely removed but be minimized, since prior to bonding step, Cu bump surface should be treated with forming gas to reduce the Cu bonding surface and this required a gap between Cu bonding surface. Warpage-enhanced wafers showed a combination of slip and expansion misalignment, but only part of expansion was explained
Please cite this article in press as: S.E. Kim, S. Kim, Microelectron. Eng. (2015), http://dx.doi.org/10.1016/j.mee.2014.12.012
4
S.E. Kim, S. Kim / Microelectronic Engineering xxx (2015) xxx–xxx
(a)
(b)
Fig. 3. (a) Schematic diagram of air gap between bonded wafers (b) optical image of pop-up breakage induced by air gap.
(a)
(b)
(c) Fig. 4. Origins of misalignment during wafer level stacking process; (a) non-uniform bump heights (b) removal of spacers in a bond fixture and (c) wafer warpage.
by warpage itself and the rest could be ascribed to thermal expansion during the bonding process [19]. The wafer warpage evolved at every process steps was measured and depicted in Fig. 5. The warpage showed maximum bow height of around 100 lm at bonding step, which was reduced by subsequent thinning process.
3.3. Bonding interface The Cu–Cu bonding interface were examined by FIB as shown in Fig. 6. Although bonding interface was partly observed, overall bonding quality seemed to be good enough to survive the following
Please cite this article in press as: S.E. Kim, S. Kim, Microelectron. Eng. (2015), http://dx.doi.org/10.1016/j.mee.2014.12.012
S.E. Kim, S. Kim / Microelectronic Engineering xxx (2015) xxx–xxx
5
Fig. 5. The wafer warpage measured at every process steps.
Fig. 6. FIB observation of Cu–Cu bonding interface (a) schematic of wafer level stacking (b) FIB image of bonding interface.
Fig. 7. (a) Electrical resistance map measured with Kelvin structure (b) FIB image showing voids at interface.
back-grinding process. Bonding interface quality was quantitatively evaluated by measuring electrical resistivity of bonding interface using daisy chain and Kelvin structures. As shown in Fig. 2(d), electrical resistance of Kelvin structure includes four contact resis-
tances, i.e., contact pad/TSV, TSV/bump, bump/bump, bump/RDL interface. It showed around 0.07 O with some deviations and this deviation could be attributed to the defects at the interface like voids (Fig. 7(b)). These voids seemed to be introduced by
Please cite this article in press as: S.E. Kim, S. Kim, Microelectron. Eng. (2015), http://dx.doi.org/10.1016/j.mee.2014.12.012
6
S.E. Kim, S. Kim / Microelectronic Engineering xxx (2015) xxx–xxx
non-uniform CMP surface and increased the electrical resistance by decreasing cross-sectional area for current flow. 4. Conclusions Wafer level bonding and stacking process for 3D stacked IC was proposed and evaluated. This process could be characterized by bonding and thinning without carrier wafer as well as Cu/recessed SiO2 hybrid bonding. Misalignment during stacking process could be ascribed to (1) non-uniform bump height, (2) removal of spacers in a bond fixture and (3) wafer warpage. The wafer warpage was observed to show maximum bow height of 100 lm at bonding step. Cu–Cu direct bonding interface showed around 0.07 O electrical resistance with some deviations caused by interface defects like voids. Acknowledgements This research was supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education (2013R1A1A2012619). References [1] Harriott, R. Lloyd, Proc. IEEE 89.3 (2001) 366–374. [2] Hongsik Park, Ali Afzali, Shu-Jen Han, George S. Tulevski, Aaron D. Franklin, Jerry Tersoff, James B. Hannon, Wilfried Haensch, Nat. Nanotechnol. 7 (12) (2012) 787–791.
[3] M. Puech, J.M. Thevenoud, J.M. Gruffat, N. Launay, N. Arnal, P. Godinat, IEEE Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (2008) 109–114. [4] M. Jürgen Wolf, et al., Electronic Components and Technology Conference, 1, 2008, pp. 1–2. [5] S.H. Hwang, B.J. Kim, H.Y. Lee, Y.C. Joo, J. Electron. Mater. 41 (2) (2012) 232– 240. [6] K. Matsumoto, S. Ibaraki, K. Sueoka, K. Sakuma, H. Kikuchi, Y. Orii, F. Yamada, 28th Annual IEEE Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM) (2012) 8–13. [7] E.J. Marinissen, Y. Zorian, IEEE International Test Conference, 2009, pp. 1–11. [8] R. Stengl, T. Tan, U. Gösele, Jpn. J. Appl. Phys. 28 (1) (1989) 1735–1741. [9] T. Suga, 3rd IEEE International Workshop on Low Temperature Bonding for 3D Integration (LTB-3D) (2012) 7–10. [10] K.N. Chen, C.S. Tan, A. Fan, R. Reif, Electrochem. Solid-State Lett. 7 (1) (2004) G14–G16. [11] B. Lee, H. Jeon, S.J. Jeon, K.W. Kwon, H.J. Lee, J. Electron. Mater. (2011) 1–6. [12] C.T. Ko, Z.C. Hsiao, H.C. Fu, K.N. Chen, W.C. Lo, Y.H. Chen, 3rd Electronic System-Integration Technology Conference (ESTC) (2010) 1–5. [13] Young Hak Cho, Sarah Eunkyung Kim, Sungdong Kim, J. Microelectron. Packag. Soc. 20 (1) (2013) 7–13. [14] Lu, Jian-Qiang, J. Jay McMahon, Ronald J. Gutmann, MRS Proc. 1112 (2009) 1112-E02. [15] A. Jourdain, S. Stoukatch, P. De Moor, W. Ruythooren, IEEE International Interconnect Technology Conference, 2007, pp. 207–209. [16] Eunsol Kim, Minjae Lee, Sungdong Kim, Sarah Eunkyung Kim, J. Microelectron. Packag. Soc. 19 (3) (2012) 37–41. [17] Minjae Lee, Sarah Eunkyung Kim, Sungdong Kim, J. Microelectron. Packag. Soc. 20 (2) (2013) 47–51. [18] Sung-Geun Kang, Jieun Lee, Eun-Sol Kim, Naeun Lim, Soohyung Kim, Sungdong Kim, Sarah Eunkyung Kim, J. Microelectron. Packag. Soc. 19 (2) (2012) 29–33. [19] Sowon Shin, Mansoek Park, Sarah Eunkyung Kim, Sungdong Kim, J. Microelectron. Packag. Soc. 20 (3) (2013).
Please cite this article in press as: S.E. Kim, S. Kim, Microelectron. Eng. (2015), http://dx.doi.org/10.1016/j.mee.2014.12.012
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Wafer level Cu–Cu direct bonding for 3D integration Sarah Eunkyung Kim a, Sungdong Kim b,⇑ a b
Graduate School of NID Fusion Technology, Seoul National University of Science and Technology, Seoul 139-743, Republic of Korea Dept. of Mechanical System Design Eng., Seoul National University of Science and Technology, Seoul 139-743, Republic of Korea
a r t i c l e
i n f o
Article history: Received 1 July 2014 Received in revised form 31 October 2014 Accepted 18 December 2014 Available online xxxx Keywords: 3D IC Wafer-to-wafer Wafer level stacking Warpage Thermo-compression bonding
a b s t r a c t Wafer level bonding and stacking process for 3D stacked IC was proposed and technical issues were discussed. Cu bumps surrounded by recessed SiO2 were thermo-compression bonded and electrically evaluated using Kelvin structures. Defects at the bonding interface such as voids were responsible for electrical resistance distribution. Wafer alignment during stacking process was found to be affected by several factors like non-uniform bump height, the spacers in a bonding fixture and wafer warpage. Step by step warpage measurement revealed that the wafer warpage was dependent on process steps and worsened at bonding step. Ó 2014 Elsevier B.V. All rights reserved.
1. Introduction Semiconductor industry has been focusing on downscaling transistors for high performance, small form factor and low production costs. Moore’s law representing these efforts, however, is facing its limit recently as transistor has been scaled down to its physical limit. A lot of efforts such as improving photolithography like EUV [1] or adopting new materials like CNT [2], are underway to keep Moore’s law continue but there are many complications that must be solved before implementing these technologies. As shrinking transistor in two dimensional area becomes difficult, building up chips into three dimension was proposed as a solution. 3D stacked IC can take advantages of small form factor and high performance by stacking chips vertically and shortening interconnection length with through silicon via (TSV), respectively. Since the idea of 3D stacked IC was first proposed, there have been many research activities on TSV fabrication technologies, for example, etching holes having high aspect ratio [3], uniform deposition of seed/barrier material, filling up the holes without defects [4]. However, recent research focus has been moved to reliability issues such as TSV stress [5] and thermal management [6] as well as design and test issues [7]. This movement implies that 3D stacked IC is ready for mass production phase. Before mass production of 3D stacked IC becomes mainstream, there are several technical and reliability concerns that must be solved, for instance, thin wafer handling and wafer bonding and stacking. Especially, ⇑ Corresponding author. E-mail address: [email protected] (S. Kim).
wafer bonding and stacking are a key technology for building up chips in three dimension. While there are many options for wafer bonding, for example, direct wafer bonding [8], surface activated bonding (SAB) [9], Cu–Cu thermo-compression bonding [10], solid liquid inter-diffusion bonding (SLID) [11] and metal/dielectric hybrid bonding [12], it becomes important to achieve low bonding temperature and to use Cu as a main bonding material. As for stacking method, there are three ways of stacking chips; chip-to-chip, chip-to-wafer, wafer-to-wafer. Due to technical accessibility and yield issue, chipto-chip stacking process is now popular in semiconductor industry, but wafer-to-wafer stacking approach is inevitable for a mass production. In this paper, we assessed various technical issues in the waferto-wafer stacking process where direct Cu–Cu thermo-compression bonding was applied. Misalignment between stacked wafers was critical for high manufacturing yield and origin of misalignment was investigated using specially designed wafer sets. Overall bonding quality was evaluated and mapped by measuring electrical resistance of bonded bumps. 2. Experimental procedure Substrate preparation and bonding process were illustrated in Fig. 1 where it should be noted that wafers were face-to-face bonded prior to thinning process. After the bonding process, TSV wafer could be thinned without temporary bonding/debonding (TBDB) since substrate wafer could play a role of carrier wafer. This approach could reduce the number of process steps by removing
http://dx.doi.org/10.1016/j.mee.2014.12.012 0167-9317/Ó 2014 Elsevier B.V. All rights reserved.
Please cite this article in press as: S.E. Kim, S. Kim, Microelectron. Eng. (2015), http://dx.doi.org/10.1016/j.mee.2014.12.012
2
S.E. Kim, S. Kim / Microelectronic Engineering xxx (2015) xxx–xxx
Fig. 1. Wafer level stacking process flow.
TBDB and increase the yield by solving thin wafer handling issues. When required, more wafers can be back-to-face stacked on top of this bonded wafer set [13]. As shown in Fig. 1, two types of 8 inch Si wafers were prepared; one is substrate wafer and the other is TSV wafer. Cu redistribution line (RDL) and bumps were fabricated on both wafers by lift off and damascene process, respectively. Fig. 2(a) and (b) shows Cu RDL and bump images, where bump diameter was 50 lm and bump pitch was 200 lm. All Cu layers have underlying Cr buffer layer for adhesion improvement. TSVs of 8 lm diameter were fabricated through conventional preparation sequences, i.e., via formation by deep reactive ion etching
(DRIE) followed by sputtering Cu seed layer and via filling by electro-deposition of Cu. After Cu bump fabrication was completed, two wafers were cleaned by immersion in diluted H2SO4 solution to remove surface Cu oxide and bonded in a wafer bonder (SB8e, SUSS Microtec) using Cu–Cu thermo-compression bonding technique. Bonding temperature was 415 °C and bonding pressure was 890 kPa. Subsequent vacuum annealing process was performed at 450 °C for 1 h. It should be noted that SiO2 layers were recessed by wet treatment prior to the bonding step, which guaranteed Cu–Cu contact and not Cu–SiO2 or SiO2–SiO2 contact [14]. TSV wafer in the bonded wafers was thinned down to around
Please cite this article in press as: S.E. Kim, S. Kim, Microelectron. Eng. (2015), http://dx.doi.org/10.1016/j.mee.2014.12.012
S.E. Kim, S. Kim / Microelectronic Engineering xxx (2015) xxx–xxx
(a)
(b)
(c)
(d)
3
Fig. 2. Optical and SEM images of (a) Cu RDL and bumps on substrate wafer (b) Cu bumps on TSV wafer (c) TSVs revealed after grinding/DRIE process and (d) schematic diagram of Kelvin structure.
30 lm using a wafer grinder (DGP8760, Disco) and DRIE (MUG21, STS) in sequence, and the Cu vias were revealed as shown in Fig. 2(c). On top of this thinned TSV wafer, Cu pads were prepared by sputtering and lift off processes for an electrical resistance measurement using Kelvin (Fig. 2(d)) and daisy chain structure. Wafer warpage was measured at each process step by multi-beam optical sensor (MOS ultra scan, kSA). Bonding interface was observed by focused ion beam (FIB) and scanning electron microscopy (SEM). 3. Results and discussion 3.1. Gap filling and CMP In the chip-to-chip stacking process, conventional underfill is usually applied to fill the gap between bumps due to mechanical and thermal reasons. However, this underfill cannot be dispensed for wafer-to-wafer stacking geometry, since capillary force is too weak to suck underfill from wafer edge to center. We prepared a bonded wafers set having an air gap between Cu bumps (Fig. 3(a)) and this air gap was observed to induce a pop-up breakage of thin TSV wafer in the vacuum process subsequent to the bonding step (see an example in Fig. 3(b)). As a gap filling material, polymers like BCB or dielectrics like SiO2 were attempted by other researches [15]. In this study, silicon oxide was selected due to its high temperature compatibility but it requires a damascene process and simultaneous SiO2–SiO2/Cu–Cu bonding which strongly depends on a chemical mechanical polishing (CMP) process.
According to our previous result [16], surface roughness should be less than 10 nm for a successful Cu–Cu bonding. A combination of Cu and SiO2 CMP followed by wet treatment turned out to be effective in controlling Cu dishing and the surface roughness [17]. 3.2. Misalignment between stacked wafers Compared with chip-to-chip stacking approach, misalignment between stacked wafers gives rise to serious yield problem in wafer-to-wafer stacking method. We speculated that misalignment during bonding process could be caused by (1) non-uniform bump height, (2) removal of spacers in a bond fixture and (3) wafer warpage. Effects of each factors were illustrated in Fig. 4 and examined by (1) preparing controlled bump height uniformity, (2) bonding without spacers, and (3) enhancing warpage by inserting additional Cu layer, respectively. In case of uniform (2–3% variation) bump height samples, only rotational misalignment was observed while non-uniform bump samples showed complex behavior of slip and rotational misalignment. Non-uniformity of bump height was generally induced by CMP and wafer thinning process. Without the spacers, misalignment was hardly observed [18]. However, misalignment by the spacers could not completely removed but be minimized, since prior to bonding step, Cu bump surface should be treated with forming gas to reduce the Cu bonding surface and this required a gap between Cu bonding surface. Warpage-enhanced wafers showed a combination of slip and expansion misalignment, but only part of expansion was explained
Please cite this article in press as: S.E. Kim, S. Kim, Microelectron. Eng. (2015), http://dx.doi.org/10.1016/j.mee.2014.12.012
4
S.E. Kim, S. Kim / Microelectronic Engineering xxx (2015) xxx–xxx
(a)
(b)
Fig. 3. (a) Schematic diagram of air gap between bonded wafers (b) optical image of pop-up breakage induced by air gap.
(a)
(b)
(c) Fig. 4. Origins of misalignment during wafer level stacking process; (a) non-uniform bump heights (b) removal of spacers in a bond fixture and (c) wafer warpage.
by warpage itself and the rest could be ascribed to thermal expansion during the bonding process [19]. The wafer warpage evolved at every process steps was measured and depicted in Fig. 5. The warpage showed maximum bow height of around 100 lm at bonding step, which was reduced by subsequent thinning process.
3.3. Bonding interface The Cu–Cu bonding interface were examined by FIB as shown in Fig. 6. Although bonding interface was partly observed, overall bonding quality seemed to be good enough to survive the following
Please cite this article in press as: S.E. Kim, S. Kim, Microelectron. Eng. (2015), http://dx.doi.org/10.1016/j.mee.2014.12.012
S.E. Kim, S. Kim / Microelectronic Engineering xxx (2015) xxx–xxx
5
Fig. 5. The wafer warpage measured at every process steps.
Fig. 6. FIB observation of Cu–Cu bonding interface (a) schematic of wafer level stacking (b) FIB image of bonding interface.
Fig. 7. (a) Electrical resistance map measured with Kelvin structure (b) FIB image showing voids at interface.
back-grinding process. Bonding interface quality was quantitatively evaluated by measuring electrical resistivity of bonding interface using daisy chain and Kelvin structures. As shown in Fig. 2(d), electrical resistance of Kelvin structure includes four contact resis-
tances, i.e., contact pad/TSV, TSV/bump, bump/bump, bump/RDL interface. It showed around 0.07 O with some deviations and this deviation could be attributed to the defects at the interface like voids (Fig. 7(b)). These voids seemed to be introduced by
Please cite this article in press as: S.E. Kim, S. Kim, Microelectron. Eng. (2015), http://dx.doi.org/10.1016/j.mee.2014.12.012
6
S.E. Kim, S. Kim / Microelectronic Engineering xxx (2015) xxx–xxx
non-uniform CMP surface and increased the electrical resistance by decreasing cross-sectional area for current flow. 4. Conclusions Wafer level bonding and stacking process for 3D stacked IC was proposed and evaluated. This process could be characterized by bonding and thinning without carrier wafer as well as Cu/recessed SiO2 hybrid bonding. Misalignment during stacking process could be ascribed to (1) non-uniform bump height, (2) removal of spacers in a bond fixture and (3) wafer warpage. The wafer warpage was observed to show maximum bow height of 100 lm at bonding step. Cu–Cu direct bonding interface showed around 0.07 O electrical resistance with some deviations caused by interface defects like voids. Acknowledgements This research was supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education (2013R1A1A2012619). References [1] Harriott, R. Lloyd, Proc. IEEE 89.3 (2001) 366–374. [2] Hongsik Park, Ali Afzali, Shu-Jen Han, George S. Tulevski, Aaron D. Franklin, Jerry Tersoff, James B. Hannon, Wilfried Haensch, Nat. Nanotechnol. 7 (12) (2012) 787–791.
[3] M. Puech, J.M. Thevenoud, J.M. Gruffat, N. Launay, N. Arnal, P. Godinat, IEEE Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (2008) 109–114. [4] M. Jürgen Wolf, et al., Electronic Components and Technology Conference, 1, 2008, pp. 1–2. [5] S.H. Hwang, B.J. Kim, H.Y. Lee, Y.C. Joo, J. Electron. Mater. 41 (2) (2012) 232– 240. [6] K. Matsumoto, S. Ibaraki, K. Sueoka, K. Sakuma, H. Kikuchi, Y. Orii, F. Yamada, 28th Annual IEEE Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM) (2012) 8–13. [7] E.J. Marinissen, Y. Zorian, IEEE International Test Conference, 2009, pp. 1–11. [8] R. Stengl, T. Tan, U. Gösele, Jpn. J. Appl. Phys. 28 (1) (1989) 1735–1741. [9] T. Suga, 3rd IEEE International Workshop on Low Temperature Bonding for 3D Integration (LTB-3D) (2012) 7–10. [10] K.N. Chen, C.S. Tan, A. Fan, R. Reif, Electrochem. Solid-State Lett. 7 (1) (2004) G14–G16. [11] B. Lee, H. Jeon, S.J. Jeon, K.W. Kwon, H.J. Lee, J. Electron. Mater. (2011) 1–6. [12] C.T. Ko, Z.C. Hsiao, H.C. Fu, K.N. Chen, W.C. Lo, Y.H. Chen, 3rd Electronic System-Integration Technology Conference (ESTC) (2010) 1–5. [13] Young Hak Cho, Sarah Eunkyung Kim, Sungdong Kim, J. Microelectron. Packag. Soc. 20 (1) (2013) 7–13. [14] Lu, Jian-Qiang, J. Jay McMahon, Ronald J. Gutmann, MRS Proc. 1112 (2009) 1112-E02. [15] A. Jourdain, S. Stoukatch, P. De Moor, W. Ruythooren, IEEE International Interconnect Technology Conference, 2007, pp. 207–209. [16] Eunsol Kim, Minjae Lee, Sungdong Kim, Sarah Eunkyung Kim, J. Microelectron. Packag. Soc. 19 (3) (2012) 37–41. [17] Minjae Lee, Sarah Eunkyung Kim, Sungdong Kim, J. Microelectron. Packag. Soc. 20 (2) (2013) 47–51. [18] Sung-Geun Kang, Jieun Lee, Eun-Sol Kim, Naeun Lim, Soohyung Kim, Sungdong Kim, Sarah Eunkyung Kim, J. Microelectron. Packag. Soc. 19 (2) (2012) 29–33. [19] Sowon Shin, Mansoek Park, Sarah Eunkyung Kim, Sungdong Kim, J. Microelectron. Packag. Soc. 20 (3) (2013).
Please cite this article in press as: S.E. Kim, S. Kim, Microelectron. Eng. (2015), http://dx.doi.org/10.1016/j.mee.2014.12.012