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α-SiC buried-gate junction field effect transistors
Materials Science and Engineering, B I I (1992) 121 - 124
121
a-SiC buried-gate junction field effect transistors G. Kelner and S. Binari Naval Research Laboratory, Washington, DC 20375-5000 (U.S.A.)
M. Shur University of Virginia, Charlottesville, VA 22903-2442 (U.S.A.)
K. Sleger Naval Research Laboratory, Washington, DC 20375-5000 (U.S.A.)
J. Paimour and H. Kong Cree Research, Inc., Durham, NC 27713 (U.S.A.)
Abstract We report the results of an experimental study on a-SiC buried-gate junction field effect transistors operating in the temperature range from 24 to 400 °C. The epitaxial structure used for fabrication of these devices employs a nitrogen-doped hexagonal a-SiC layer grown on a p-type aluminum-doped a-SiC film. Epitaxial layers were grown on the silicon face of unintentionally doped n-type a-SiC substrates. The current in the channel is modulated using the p-type layer as a gate. Fabricated devices with a 4/~m gate length have a maximum transconductance (gin) of 17 mS mm -~ and a drain saturation current (IDss) of 450 mA mm- 1 at room temperature. This value of the transconductance is the highest reported for devices of similar structure. Devices are completely pinched off at a gate voltage of - 40 V. The device transconductance drops with increasing temperature owing to the decrease in electron mobility. The values of electron mobility at elevated temperatures derived from the measured transconductances and drain conductances are in agreement with independently measured Hall data.
1. Introduction Development of SiC electronic devices is gaining in importance as the result of a growing need for electronic components to function in severe environmental conditions. Because of its wide band gap (ranging from 2.2 eV for r - s i c to 3.3 eV for 2H-a-SiC), SiC is expectd to be useful in electronic devices operating at high temperature. SiC has a high saturation electron drift velocity of 2×107 cm s -1 [1], a high breakdown field of 5 × 106 V c m -1 [2] and a high thermal conductivity of 3.5 W cm-1 °(2-1 [3], which make this material very useful for high power and high frequency devices. These properties combined with thermal stability and chemical inertness make SiC very promising for electronic device applications. Previously we reported the fabrication of one type of SiC device, a buried-gate junction field effect transister (JFET) [4]. This device was fabri0921-5107/92/$5.00
cated with r-SiC and employed an epitaxial n-type layer grown by chemical vapor deposition (CVD) on a p-type a-SiC substrate. The 6 H - a SIC(0001) substrate was grown in an Acheson furnace and had an area of approximately 0.4 cm 2. A recently developed technique for obtaining substrates of 6H-a-SiC 1-2 in diameter renewed interest in 6H-a-SiC epilayers grown on these substrates. In this paper we report on an a-SiC buried-gate JFET. Devices fabricated in this study with a 4/~m gate length have a maximum transconductance (gin) of 17 mS m m - l and a drain saturation current of 450 mA mm-~ at room temperature. Current-voltage (I- V) characteristics of fabricated devices were measured at elevated temperatures up to 400 °C.
2. Device structure and fabrication The cross-sectional drawing of an a-SiC buried-gate JFET is shown in Fig. 1. The current © Elsevier Sequoia/Printed in The Netherlands
122
n-type o~. SiC
SOURCE ~
DRAIN ~
,
GATE
'--'
t
~
p-type a- SiC
1018
g z Q t< rr
n-type a - SiC substrate (0001) uJ O z
10,7
o
Fig. 1. Cross-section of a-SiC buried-gate JFET.
O rc LIJ
E:
3 lo'~
in the channel is modulated using the p-type aSiC epitaxial layer as a gate. The SiC material consists of a nitrogen-doped n-type a-SiC layer 1 /~m thick with a carrier concentration of 5 x 10 t7 cm- 3 grown on top of an aluminum-doped p-type a-SiC layer 1.6 p m thick with a hole concentration of 1 x 1018 c m -3. The a-SiC films were grown on the silicon face of a hexagonal 6HSIC(0001 ) unintentionally doped n-type substrate with a carrier concentration of 4 x 1017 cm -a. The substrates, of 1 in diameter, and epilayers were grown by Cree Research, Inc. Devices were fabricated with gate widths of 240 and 185/~m and source-to-drain spacings in the range from 4 to 40/~m. Electrical isolation of the channel was accomplished using CF4 + 02 reactive ion etching with the wafer placed on a graphite-coated electrode. The source and drain contacts to the n-type channel were electron-beam-evaporated nickel. Contacts became ohmic after rapid thermai annealing at 1000 °C in forming gas for 20 s. The specific contact resistance was determined by the transmission line model and was found to be 1.7x 10 -4 g2 c m 2. A thermally evaporated aluminum contact annealed in forming gas for 5 rain was used to contact the p-type gate. The channel between the source and drain contacts was etched to a final thickness of approximately 0.3/~m by using CF4 + O: reactive ion etching. 3.
Device
characterization
The Hall mobility of the n-type channel at room temperature was measured to be 240 cm 2 V- 1 s- 1. The carrier concentration of the channel as a function of depth is shown in Fig. 2. This curve was obtained from the capacitance-voltage characteristics of thermally evaporated aluminum Schottky barrier contacts. As can be seen from Fig. 2, the carrier concentration in the channel is approximately 5 x 10 t7 c m -3, except near the interface with the p-type layer where it drops sharply. The channel thickness is approximately
I
I
I
0.1
0.2
0.3
DEPTH (,Ltrn)
Fig. 2. Carrier concentration channel.
vs.
depth profile of n-type
Horizontal Scale 20v/div Vertical Scale 50/LA/div Fig. 3. Gate-to-source JFET.
I-V
characteristics of buried-gate
0.3 /~m. Figure 3 shows the gate-to-source I - V characteristics of the buried-gate JFET. At a leakage current of 5 / t A the breakdown voltage is - 1 0 0 V. The current-voltage characteristics of the a-SiC buried-gate JFET with 4 /~m gate length at room temperature are shown in Fig. 4. The gate voltage varies from 0 to - 4 0 V in - 5 V steps. The device displays good saturation and is completely pinched off at a gate voltage of - 40 V. With - 40 V on the gate the device has withstood 80 V on the drain, with a drain current of 3 mA. The transconductance of this device is 17 mS mm-1, which is considerably higher than previously reported results for JFET devices of similar structure [5]. Buried-gate JFETs with different gate lengths were also fabricated. Dependences of transconductance and drain saturation
123
current at 0 V gate voltage vs. reciprocal gate length are shown in Fig. 5. Measured values of gr. and IDSS display the expected dependence on g a t e length [4]. We also performed measurements of
the device characteristics over a wide temperature range. For these measurements we chose long channel devices where transconductance is approximately proportional to electron mobility. The data in Fig. 6 were taken for a device with a 39/~m gate length at temperatures of 24, 270 and 400°C. The device transconductance drops with increasing temperature owing to the decrease in electron mobility, as we show below. The temperature dependences of the electron mobility deduced from the measured values of the device transconductance and drain conductance are shown in Fig. 7, where they are compared with the temperature-dependent Hall mobilities measured in an independent study [6, 7]. The mobility values deduced from the drain conductance go at low drain voltages were determined using the slope of the gd VS. 1/{ 1 -[( Vbi- Vg)/Vpo] 112} dependence
100 8o
=or
v
=
tr Z uJ a.-
60
- - -10V"
t.DD
401
-15V,
_
..
_
~v 0
~
0
'
10
20
-a0v
. k
30
ov
'
"
40
I "35V
50
DRAIN-TO-SOURCE VOLTAGE (V) Fig. 4, R o o m temperature drain c u r r e n t vs, d r a i n voltage
(Id-Vd) characteristics of buried-gate JFET with 4 ktm gate length. 18
I
I
I
I
1 L - - = Rs + Rd'+ gd q /uA N d W{1 - [( Vb, - V,) I Vpo]'/2}
J
~-16 -
--
600
LU 12 O lO
-
500 ~" E ,oo
~0a ca
-- 300
~
where Rs and R d are source and drain series resistances, L is the gate length, W is the gate width, Vbi ~"2.5 V is the built-in voltage, Vpo is the pinch-off voltage, q is the electronic charge, N d is the channel doping, # is the electron mobility and A is the channel thickness. The values of the mobility determined from the transconductance in the saturation region were found by using the square law device model described in ref. 4. All three mobility curves are in agreement, thus we conclude that the reduction of gm with increasing temperature is strongly related to the decrease in mobility.
14--
06
ac
-- 200 o
04 <
~ 02
z
• Transconductance
vs l/Lg • Drain saturation c u r r e n t v s l / L g
--
o 0.00
I
I
1
1
I
0.05
0.10
0.15
0.20
0.25
--
100
0.30
INVERSE GATE LENGTH 0/micron)
Fig. 5. Transconductance of buffed-gate JFET v s , reciprocal gate length, and drain saturation current dependence on reciprocal gate length.
240C
2700C
•E 16
400oc
16
16 Vg=0
L) z
-10v
Vg=Ov 8
, -- 40V
10
20
30
40
DRAIN-TO-SOURCE VOLTAGE (V)
~
h
i
10
20
, ~--
30
_l_ov
40v
-- 45v
DRAIN-TO-SOURCE VOLTAGE (V)
10
20
30 -- 45V
DRAIN-TO-SOURCE VOLTAGE (V)
Fig. 6. Current-voltage characteristics of buried-gate JFET with 39 # m gate length measured at elevated temperature.
124 1000
J
I
J
I
~
I
J
I
~
• ..... transconductance 0 . . . . . drain conductance
A 10
200
,
I
4. Conclusions
+
Our study demonstrates that a-SiC JFETs can be fabricated with characteristics which are superior to those of previously fabricated fl-SiC JFETs. These devices are operational at 400 °C. a-SiC JFET I - V characteristics display high gin, excellent saturation, complete pinch-off, high drain voltage and high p-n junction breakdown voltage.
/k
Hall I
300
,
I
,
I
J
I
400 500 600 TEMPERATURE (K)
,
I
700
J
800
Fig. 7. Temperature dependences of electron mobility deduced from measured values of device transconductance and drain conductance and from temperature-dependent Hall mobilities measured in an independent study [6, 71 for device with 39/~m gate length.
The transconductance of 17 mS m m - 1 for a 4 /am gate length in an a-SiC buried-gate JFET is comparable with the results obtained in fl-SiC JFET devices with similar gate length in spite of the smaller mobility in the channel (240 cm ~ Vs-1 for an a-SiC buried-gate JFET compared with 500 cm 2 V-~ s -1 for a fl-SiC buried-gate JFET at room temperature). This can be explained by a different device design, in particular an increased carrier concentration of the channel (5 x 1017 c m - 3 for an a-SiC device vs. 3 x 1016 c m -3 for a fl-SiC J F E T ) and a smaller channel thickness in the a-SiC JFET. These results show great potential for a-SiC material in future device applications.
Acknowledgment This work was sponsored by the Office of Naval Research.
References 1 D.K. Ferry, Phys. Rev. B, 12 (1975) 2361-2369. 2 C. van Opdorp and J. Vrakking, J. Appl. Phys., 40 (1969) 2320-2322. 3 W. von Muench and I. Pfaffender, J. AppL Phys., 48 (1977) 4831-4833. 4 G. Kelner, M. Shur, S. Binari, K. Sieger and H. Kong, IEEE Trans. Electron Devices, 36 (6) (1989) 1045-1049. 5 V. A. Dmitriev, P. A. Ivanov, N. D. llinskaya, A. L. Sirkin, B. V. Tsarenkov, A. E. Chelnokov and A. E. Cherenkov, Soy. Tech. Phys. Lett., 14 (1988) 127-128. 6 B.L. Barrett and R. B. Campbell, J. Appl. Phys., 38 (1967) 53-55. 7 T. Tachibana, H. S. Kong and R. F. Davis, J. Appl. Phys., 67 (10)(1990) 6375-6381.
121
a-SiC buried-gate junction field effect transistors G. Kelner and S. Binari Naval Research Laboratory, Washington, DC 20375-5000 (U.S.A.)
M. Shur University of Virginia, Charlottesville, VA 22903-2442 (U.S.A.)
K. Sleger Naval Research Laboratory, Washington, DC 20375-5000 (U.S.A.)
J. Paimour and H. Kong Cree Research, Inc., Durham, NC 27713 (U.S.A.)
Abstract We report the results of an experimental study on a-SiC buried-gate junction field effect transistors operating in the temperature range from 24 to 400 °C. The epitaxial structure used for fabrication of these devices employs a nitrogen-doped hexagonal a-SiC layer grown on a p-type aluminum-doped a-SiC film. Epitaxial layers were grown on the silicon face of unintentionally doped n-type a-SiC substrates. The current in the channel is modulated using the p-type layer as a gate. Fabricated devices with a 4/~m gate length have a maximum transconductance (gin) of 17 mS mm -~ and a drain saturation current (IDss) of 450 mA mm- 1 at room temperature. This value of the transconductance is the highest reported for devices of similar structure. Devices are completely pinched off at a gate voltage of - 40 V. The device transconductance drops with increasing temperature owing to the decrease in electron mobility. The values of electron mobility at elevated temperatures derived from the measured transconductances and drain conductances are in agreement with independently measured Hall data.
1. Introduction Development of SiC electronic devices is gaining in importance as the result of a growing need for electronic components to function in severe environmental conditions. Because of its wide band gap (ranging from 2.2 eV for r - s i c to 3.3 eV for 2H-a-SiC), SiC is expectd to be useful in electronic devices operating at high temperature. SiC has a high saturation electron drift velocity of 2×107 cm s -1 [1], a high breakdown field of 5 × 106 V c m -1 [2] and a high thermal conductivity of 3.5 W cm-1 °(2-1 [3], which make this material very useful for high power and high frequency devices. These properties combined with thermal stability and chemical inertness make SiC very promising for electronic device applications. Previously we reported the fabrication of one type of SiC device, a buried-gate junction field effect transister (JFET) [4]. This device was fabri0921-5107/92/$5.00
cated with r-SiC and employed an epitaxial n-type layer grown by chemical vapor deposition (CVD) on a p-type a-SiC substrate. The 6 H - a SIC(0001) substrate was grown in an Acheson furnace and had an area of approximately 0.4 cm 2. A recently developed technique for obtaining substrates of 6H-a-SiC 1-2 in diameter renewed interest in 6H-a-SiC epilayers grown on these substrates. In this paper we report on an a-SiC buried-gate JFET. Devices fabricated in this study with a 4/~m gate length have a maximum transconductance (gin) of 17 mS m m - l and a drain saturation current of 450 mA mm-~ at room temperature. Current-voltage (I- V) characteristics of fabricated devices were measured at elevated temperatures up to 400 °C.
2. Device structure and fabrication The cross-sectional drawing of an a-SiC buried-gate JFET is shown in Fig. 1. The current © Elsevier Sequoia/Printed in The Netherlands
122
n-type o~. SiC
SOURCE ~
DRAIN ~
,
GATE
'--'
t
~
p-type a- SiC
1018
g z Q t< rr
n-type a - SiC substrate (0001) uJ O z
10,7
o
Fig. 1. Cross-section of a-SiC buried-gate JFET.
O rc LIJ
E:
3 lo'~
in the channel is modulated using the p-type aSiC epitaxial layer as a gate. The SiC material consists of a nitrogen-doped n-type a-SiC layer 1 /~m thick with a carrier concentration of 5 x 10 t7 cm- 3 grown on top of an aluminum-doped p-type a-SiC layer 1.6 p m thick with a hole concentration of 1 x 1018 c m -3. The a-SiC films were grown on the silicon face of a hexagonal 6HSIC(0001 ) unintentionally doped n-type substrate with a carrier concentration of 4 x 1017 cm -a. The substrates, of 1 in diameter, and epilayers were grown by Cree Research, Inc. Devices were fabricated with gate widths of 240 and 185/~m and source-to-drain spacings in the range from 4 to 40/~m. Electrical isolation of the channel was accomplished using CF4 + 02 reactive ion etching with the wafer placed on a graphite-coated electrode. The source and drain contacts to the n-type channel were electron-beam-evaporated nickel. Contacts became ohmic after rapid thermai annealing at 1000 °C in forming gas for 20 s. The specific contact resistance was determined by the transmission line model and was found to be 1.7x 10 -4 g2 c m 2. A thermally evaporated aluminum contact annealed in forming gas for 5 rain was used to contact the p-type gate. The channel between the source and drain contacts was etched to a final thickness of approximately 0.3/~m by using CF4 + O: reactive ion etching. 3.
Device
characterization
The Hall mobility of the n-type channel at room temperature was measured to be 240 cm 2 V- 1 s- 1. The carrier concentration of the channel as a function of depth is shown in Fig. 2. This curve was obtained from the capacitance-voltage characteristics of thermally evaporated aluminum Schottky barrier contacts. As can be seen from Fig. 2, the carrier concentration in the channel is approximately 5 x 10 t7 c m -3, except near the interface with the p-type layer where it drops sharply. The channel thickness is approximately
I
I
I
0.1
0.2
0.3
DEPTH (,Ltrn)
Fig. 2. Carrier concentration channel.
vs.
depth profile of n-type
Horizontal Scale 20v/div Vertical Scale 50/LA/div Fig. 3. Gate-to-source JFET.
I-V
characteristics of buried-gate
0.3 /~m. Figure 3 shows the gate-to-source I - V characteristics of the buried-gate JFET. At a leakage current of 5 / t A the breakdown voltage is - 1 0 0 V. The current-voltage characteristics of the a-SiC buried-gate JFET with 4 /~m gate length at room temperature are shown in Fig. 4. The gate voltage varies from 0 to - 4 0 V in - 5 V steps. The device displays good saturation and is completely pinched off at a gate voltage of - 40 V. With - 40 V on the gate the device has withstood 80 V on the drain, with a drain current of 3 mA. The transconductance of this device is 17 mS mm-1, which is considerably higher than previously reported results for JFET devices of similar structure [5]. Buried-gate JFETs with different gate lengths were also fabricated. Dependences of transconductance and drain saturation
123
current at 0 V gate voltage vs. reciprocal gate length are shown in Fig. 5. Measured values of gr. and IDSS display the expected dependence on g a t e length [4]. We also performed measurements of
the device characteristics over a wide temperature range. For these measurements we chose long channel devices where transconductance is approximately proportional to electron mobility. The data in Fig. 6 were taken for a device with a 39/~m gate length at temperatures of 24, 270 and 400°C. The device transconductance drops with increasing temperature owing to the decrease in electron mobility, as we show below. The temperature dependences of the electron mobility deduced from the measured values of the device transconductance and drain conductance are shown in Fig. 7, where they are compared with the temperature-dependent Hall mobilities measured in an independent study [6, 7]. The mobility values deduced from the drain conductance go at low drain voltages were determined using the slope of the gd VS. 1/{ 1 -[( Vbi- Vg)/Vpo] 112} dependence
100 8o
=or
v
=
tr Z uJ a.-
60
- - -10V"
t.DD
401
-15V,
_
..
_
~v 0
~
0
'
10
20
-a0v
. k
30
ov
'
"
40
I "35V
50
DRAIN-TO-SOURCE VOLTAGE (V) Fig. 4, R o o m temperature drain c u r r e n t vs, d r a i n voltage
(Id-Vd) characteristics of buried-gate JFET with 4 ktm gate length. 18
I
I
I
I
1 L - - = Rs + Rd'+ gd q /uA N d W{1 - [( Vb, - V,) I Vpo]'/2}
J
~-16 -
--
600
LU 12 O lO
-
500 ~" E ,oo
~0a ca
-- 300
~
where Rs and R d are source and drain series resistances, L is the gate length, W is the gate width, Vbi ~"2.5 V is the built-in voltage, Vpo is the pinch-off voltage, q is the electronic charge, N d is the channel doping, # is the electron mobility and A is the channel thickness. The values of the mobility determined from the transconductance in the saturation region were found by using the square law device model described in ref. 4. All three mobility curves are in agreement, thus we conclude that the reduction of gm with increasing temperature is strongly related to the decrease in mobility.
14--
06
ac
-- 200 o
04 <
~ 02
z
• Transconductance
vs l/Lg • Drain saturation c u r r e n t v s l / L g
--
o 0.00
I
I
1
1
I
0.05
0.10
0.15
0.20
0.25
--
100
0.30
INVERSE GATE LENGTH 0/micron)
Fig. 5. Transconductance of buffed-gate JFET v s , reciprocal gate length, and drain saturation current dependence on reciprocal gate length.
240C
2700C
•E 16
400oc
16
16 Vg=0
L) z
-10v
Vg=Ov 8
, -- 40V
10
20
30
40
DRAIN-TO-SOURCE VOLTAGE (V)
~
h
i
10
20
, ~--
30
_l_ov
40v
-- 45v
DRAIN-TO-SOURCE VOLTAGE (V)
10
20
30 -- 45V
DRAIN-TO-SOURCE VOLTAGE (V)
Fig. 6. Current-voltage characteristics of buried-gate JFET with 39 # m gate length measured at elevated temperature.
124 1000
J
I
J
I
~
I
J
I
~
• ..... transconductance 0 . . . . . drain conductance
A 10
200
,
I
4. Conclusions
+
Our study demonstrates that a-SiC JFETs can be fabricated with characteristics which are superior to those of previously fabricated fl-SiC JFETs. These devices are operational at 400 °C. a-SiC JFET I - V characteristics display high gin, excellent saturation, complete pinch-off, high drain voltage and high p-n junction breakdown voltage.
/k
Hall I
300
,
I
,
I
J
I
400 500 600 TEMPERATURE (K)
,
I
700
J
800
Fig. 7. Temperature dependences of electron mobility deduced from measured values of device transconductance and drain conductance and from temperature-dependent Hall mobilities measured in an independent study [6, 71 for device with 39/~m gate length.
The transconductance of 17 mS m m - 1 for a 4 /am gate length in an a-SiC buried-gate JFET is comparable with the results obtained in fl-SiC JFET devices with similar gate length in spite of the smaller mobility in the channel (240 cm ~ Vs-1 for an a-SiC buried-gate JFET compared with 500 cm 2 V-~ s -1 for a fl-SiC buried-gate JFET at room temperature). This can be explained by a different device design, in particular an increased carrier concentration of the channel (5 x 1017 c m - 3 for an a-SiC device vs. 3 x 1016 c m -3 for a fl-SiC J F E T ) and a smaller channel thickness in the a-SiC JFET. These results show great potential for a-SiC material in future device applications.
Acknowledgment This work was sponsored by the Office of Naval Research.
References 1 D.K. Ferry, Phys. Rev. B, 12 (1975) 2361-2369. 2 C. van Opdorp and J. Vrakking, J. Appl. Phys., 40 (1969) 2320-2322. 3 W. von Muench and I. Pfaffender, J. AppL Phys., 48 (1977) 4831-4833. 4 G. Kelner, M. Shur, S. Binari, K. Sieger and H. Kong, IEEE Trans. Electron Devices, 36 (6) (1989) 1045-1049. 5 V. A. Dmitriev, P. A. Ivanov, N. D. llinskaya, A. L. Sirkin, B. V. Tsarenkov, A. E. Chelnokov and A. E. Cherenkov, Soy. Tech. Phys. Lett., 14 (1988) 127-128. 6 B.L. Barrett and R. B. Campbell, J. Appl. Phys., 38 (1967) 53-55. 7 T. Tachibana, H. S. Kong and R. F. Davis, J. Appl. Phys., 67 (10)(1990) 6375-6381.