0.5-V DTMOS median filter

Int. J. Electron. Commun. (AEÜ) 69 (2015) 1733–1736

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SHORT COMMUNICATION

0.5-V DTMOS median filter Fabian Khateb a,b,∗ , Tomasz Kulej c , Montree Kumngern d a

Department of Microelectronics, Brno University of Technology, Technická 10, Brno, Czech Republic Faculty of Biomedical Engineering, Czech Technical University in Prague, nám. Sítná 3105, Kladno, Czech Republic c Department of Electrical Engineering, Technical University of Cz˛estochowa, 42-201 Cz˛estochowa, Poland d Faculty of Engineering, King Mongkut’s Institute of Technology Ladkrabang, Bangkok 10520, Thailand b

a r t i c l e

i n f o

Article history: Received 3 June 2015 Accepted 25 July 2015 Keywords: Median filter DTMOS Low-voltage low-power MOS

a b s t r a c t This letter presents an analog median filter with ultra-low-voltage supply and extremely low-power consumption. The structure of the median filter is based on comparators built by current limiting transconductance amplifier (OTA). In order to achieve high transconductance and large input range the proposed CMOS structure of the OTA is based on a cascade of two differential stages where the differential pairs exploit the dynamic threshold MOSFET (DTMOS) technique. The proposed structure of OTA is capable to work with 0.5 V supply voltage and consumes 30 nW with simple CMOS circuitry. The design and simulation of the median filter have been performed in Cadence environment using the 0.18 ␮m CMOS TSMC process. The simulation results prove the functionality and the attractive features of the proposed circuit. © 2015 Elsevier GmbH. All rights reserved.

1. Introduction Median filters are non-linear circuits used for removing impulsive type noise from a signal while preserving sharp edges. They are frequently used in various signal and image processing applications, such as seismic signal processing, speech processing, computerized tomography, medical imaging, robotic vision, pattern recognition, peak detection, coding, and communication [1–10]. Various CMOS structures for the median filter were presented in the literature [6–10,20]. However, based on our survey none of these structures is capable to work under ultra-low-voltage supply and power consumption causing limitation of using these filters in portable devices where decreasing the size/weight and extending the life-time of the battery are essential. Therefore, this letter presents a new and simple CMOS structure for analog median filter with ultra-low-voltage supply and extremely low-power consumption. The proposed median filter uses the principle of balanced saturation comparator [4–8]. However, in order to improve the circuit performance under ultra low voltage supply, the dynamic threshold MOSFET (DTMOS) technique has been employed in this design. The DTMOS belongs to the non-conventional techniques

∗ Corresponding author at: Department of Microelectronics, Brno University of Technology, Technická 10, Brno, Czech Republic. Tel.: +420 54114 6128. E-mail addresses: [email protected] (F. Khateb), [email protected] (T. Kulej), [email protected] (M. Kumngern). http://dx.doi.org/10.1016/j.aeue.2015.07.015 1434-8411/© 2015 Elsevier GmbH. All rights reserved.

suitable for low voltage applications; other techniques include bulk-driven, floating-gate and quasi-floating-gate techniques or their combination [11–13]. Owing to the lower threshold voltages of DTMOS transistors, the input voltage range of the filter has been increased to 60% of VDD . Simultaneously the input referred noise and offsets are not multiplied by the gm /gmb ratio as in bulk-driven circuits, which could provide larger (rail-to-rail) input range at the cost of increased input referred noise and mismatches [14–17]. Consequently, the dynamic range has been improved. Furthermore, the relatively large transconductance of the DTMOS allows increasing the overall voltage gain and reduces the smooth corner errors of the filter, which also improves its accuracy. The rest of this letter is organized as follows. The DTMOS current limiting open-loop operational transconductance amplifier (OTA) and the median filter are described in Sections 2 and 3, respectively. Simulation results are presented in Section 4. The letter is concluded in Section 5.

2. DTMOS current limiting OTA The symbol and the CMOS structure of the current limiting OTA are shown in Fig. 1. The CMOS structure shown in Fig. 1(b) consists of a two-stage transconductor. The first stage is formed by differential pair transistors M1 , M2 with M5 , M6 operating as a current mirror and M9 as a current source. The second stage is formed by differential pair transistors M3 , M4 with M7 , M8 as a current mirror and M10 as a current source. Transistor M11 and the bias current

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mismatches of ˇ (which is much less significant in weak inversion region) one could simplify the above equation to the form:



1 1 + W1,2 L1,2 W5,6 L5,6

 2 (VOS ) ≈ A2VT



(6)

In order to determine the accuracy (resolution) of the considered OTA, the DC accuracy factor ACC can be defined as the ratio of the maximum input swing Vinm to the 3(VOS ) offset: ACC =

Vinm 3(VOS )

(7)

Substituting (6) into (7) yields:



ACC = 3AVT Fig. 1. Symbol of the current limiting OTA (a), CMOS internal structure (b).

Ibias provide the biasing current for the circuit. The compensation capacitor Cc ensures the circuit stability. Note, that the two differential pair transistors M1 , M2 and M3 , M4 are driven from the gate and the bulk terminals simultaneously in order to obtain high gain current limiting OTA under ultra-low voltage supply and extremely low power consumption. The open loop gain of the current limiting OTA is given by: A=

(gm1,2 + gmb1,2 ) (gm3,4 + gmb3,4 ) . (go2 + go6 ) (go4 + go8 )

(1)

where gm and gmb are the gate and bulk transconductances, respectively, and go is the output conductance. From Eq. (1) it is evident that high value of the open loop gain is obtained due to using the DTMOS technique. The open loop output resistance ro is given by: ro =

1 (go4 + go8 )

(2)

An important factor limiting accuracy of the considered circuit is the device mismatch. The mismatch of two closely spaced identical MOS transistors has been extensively investigated by other authors [18,19] and it is well known, that random differences of threshold voltages VT and current factors ˇ(ˇ = Cox W/L), which are dominant sources of device mismatch are described by a normal distribution with zero mean and a variance given by:  2 (VT ) =



 2 (ˇ) ˇ

A2VT

(3)

WL

2

=

where W and L are transistor channel width and length respectively and AVT and Aˇ are technology-dependent constants. Applying the above model, neglecting the second order effects and following the analysis method described in [19] the input referred offset variance  2 (VOS ) of the OTA in Fig. 1 can be calculated as:

+

(8) +

1 W5,6 L5,6

 3A A 2 CC VT

WL = 2

(9)

Vinm

According to (8) and (9) the circuit accuracy could be improved by employing larger devices. This however would lead to an increased area and lower speed of the overall structure. Thus a design tradeoff is required in the design. Assuming that the input referred noise spectral densities for thermal and flicker noise of an MOS transistor are given by Eqs. (10) and (11), respectively: Vit2 =

8kT 3gm

2 Vi,1/f =

(10)

2 Kf gm

(11)

fC OX WL

where k is the Boltzmann constant, T is the temperature, Kf is the flicker noise constant, COX is the oxide capacitance per unit area and the other factors have their usual meaning. Neglecting the second order effects and conducting a standard small-signal noise analysis, the input referred noise of a single OTA of Fig. 1, is approximately equal to the input noise of its input stage: Thermal: Vit2 = 2

8kT 3gmef1

Flicker (1/f): 2 fCOX

g m1



gmef1

+

gm5 gmef1



Kfp

 g 2 m1

W1,2 L1,2

gmef1

(12)

+

Kfn W5,6 L5,6

 g 2  m5 gmef1

(13)

(4)

WL

gm1 2  2 (VOS ) ≈ A gmef1 VT

1 W1,2 L1,2

Assuming W1,2 L1,2 = W5,6 L5,6 = WL one could calculate the required channel area (WL) for M1 (M2 ) and M5 (M6 ), providing the required accuracy:

2 Vi,1/f =

A2ˇ

Vinm



1 + W1,2 L1,2

 I 2 bias 2gmef1



A2ˇ

g

m3

gm1

2

1 W5,6 L5,6

1 1 + W1,2 L1,2 W5,6 L5,6





(5)

where gmef1 = gm1 + gmb1 is the effective transconductance of the first stage. Assuming operation in weak inversion, equality of subthreshold slope factors for n- and p-channel devices, considering further gm1 ≈ gmef1 and neglecting the term corresponding to

It is worth to note, that limitations in dynamic range introduced by both thermal and flicker noise are typically less significant than that caused by device mismatches. 3. Median filter based on current limiting OTA The median filter was built by an n-input current limiting OTA as shown in Fig. 2. The input voltages Vin1 –Vinn are applied to the non-inverting terminal of specific OTA, respectively. The output of each OTA is fed back to its inverting terminal and all these OTA outputs are tied together at the output Vout . Owing to the narrow differential range of each OTA (few milivolts) the OTAs whose input voltages are above the median saturate with maximum positive output currents whereas the OTAs whose input voltages are below the median saturate with maximum negative output currents. The maximum positive and negative output currents compensate each other and the OTA with median value

F. Khateb et al. / Int. J. Electron. Commun. (AEÜ) 69 (2015) 1733–1736

Vin1

+ -

Vin2

+ -

Vinn

+ -

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Vout

Fig. 4. DC transfer characteristic of the three input median filter. Fig. 2. Median filter based on current limiting OTAs.

on its input stay in feedback configuration hence the median value appears at the output Vout . In this work a three-input median filter is considered. The total input offset for the median filter is approximately the same as for a single OTA, since offset currents at the output, caused by other (saturated) OTAs, are divided by a large transconductance of the active OTA when referred to the input. The same applies also for the input referred noise. It worth to mention that since the inputs of the median filter are created by the DTMOS transistors, the input parasitic capacitance is higher compared to the conventional gate driven transistor. This input parasitic capacitance affects the speed of the circuit with increasing the number of the input terminals. Therefore, the proposed circuit is suitable for low frequency applications such as the biomedical one where the voltage supply and the power consumption are the main concern.

noteworthy that due to using the DTMOS transistor the current limiting OTA has high transconductance and large common-mode input range. The simulation results of the three input DTMOS median filter are shown in Figs. 4–6. The DC transfer characteristic for Vin1 swept from 0 to 500 mV, Vin2 = 100 mV and Vin3 = 400 mV is shown in Fig. 4. It is worth to point out the low corner errors apparent in this characteristic were the simulated DC error was below 1.5 mV. This DC error was still below 2 mV under different process corners and temperature variations (0–70 ◦ C). Monte Carlo mismatch

4. Simulation results The proposed CMOS structure of the current limiting OTA was designed in Cadence platform using transistor models from a 0.18 ␮m CMOS TSMC process. In Fig. 1(b) the proposed CMOS structure consume extremely low power 30 nW due to using ultra-low supply voltage of 0.5 V from one side and by setting the bias current Ibias to 20 nA from side other. The transistors aspect ratios in ␮m/␮m are: (W/L)M1–M8 = 5/1, (W/L) M9–M11 = 10/3 and the compensation capacitor Cc = 0.1 pF. It is worth to mention that due to using a low voltage supply the latch-up currents are avoided. The DC transfer characteristic of the current limiting OTA is shown in Fig. 3 were the saturation current is ±20 nA. It is

Fig. 3. DC transfer characteristic of the current limiting OTA.

Fig. 5. DC transfer characteristic of the median filter for Vin2 = Vin3 = 0.25 V (a), zoom in (b).

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a MIF value of 100% means rail-to-rail common-mode voltage range. 5. Conclusion This letter presents an analog median filter with ultra-lowvoltage supply and extremely low-power consumption with simple CMOS circuitry. Thanks to the use of DTMOS transistors the input range of the filter is as high as 60% of VDD , while the input referred noise and offsets are not multiplied by the gm /gmb ratio as in bulk-driven circuits, which could provide larger (rail-to-rail) input swing at the cost of increased input referred noise and mismatches. Consequently, in the considered application the DTMOS approach provides better performance in terms of dynamic range (accuracy), under extremely low supply voltage. The simulation results prove the functionality and the attractive features of the proposed circuit.

Fig. 6. Time response of the three input median filter. Table 1 Performance comparison of the proposed median filter with ultra low-power median filters in [10] and [20].

Technology (␮m) Number of inputs Voltage supply (V) Power consumption (nW) Input voltage range (V) NTH = (VTH /VDD )*100 (%) MIF = (Vin.pp /VDD )*100 (%) Obtained results

Acknowledgments

Proposed method

[10] 2nd and 3rd topology

[20]

Research described in this letter was financed by the National Sustainability Program under grant LO1401. For the research, infrastructure of the SIX Center was used.

0.18 3 0.5 70

0.5 3 ±1.5 270

1.5 3 ±2.5 300,000

References

0.3 80

1 31

– 14

60

33

–

Sim.

Meas.

Sim.

analysis for nominal VDD and T = 27 ◦ C (500 runs) showed input referred offset (1) of 3.1 mV. Fig. 5 shows the capability of the median filter for rejection of nonmedian input. The first input Vin1 was swept from 0 to 500 mV whereas the two other inputs were held to a common constant voltage, i.e. Vin2 = Vin3 = 250 mV. In Fig. 5(a) the curves of Vin2 , Vin3 , Vout are overlapped. However, detailed zoom in at the cross section of all curves shows the DC error which was below ±0.5 mV as shown in Fig. 5(b). The time response of the median filter excited with three triangular inputs Vin1 , Vin2 and Vin3 is shown in Fig. 6. It is again evident that the output follows the median signal of the inputs with tolerated corner error. Table 1 shows performance comparison of the proposed DTMOS median filter with the ultra-low-power analog median filters presented in [10] and [20]. Due to the fact that the corresponding structures in the comparison were realized in different technologies (i.e., different values of threshold voltage) using also different supply voltages, the following performance factors have been utilized: (a) the normalized threshold (NTH) factor, defined as the threshold-to-supply voltage ratio (VTH /VDD ) and (b) the modulation index factor (MIF), defined as the ratio between the maximum amplitude that could be successfully handled by the filter and the corresponding bias voltage (Vpp.max /VDD ). The NTH factor provides information about the capability of an active block to work in a LV environment. Obviously, as high as possible values of NTH are desired in active block in order to be efficient for LV operation. The MIF is very useful for characterizing the common-mode voltage range that could be successfully handled by the circuit;

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