1979 International conference on parallel processing

EUROMICRO Report

1979 International Conference on Parallel Processing This annually organized conference held at a Michigan resort place (August 21-24, 1979) was attended by about I00 p a r t i c i p a n t s . Although the main topics of t h i s conference are related to large computer a r c h i t e c t u r e there is recognized an increasing i n t e r e s t in microprocessing and microprogramming. From the 1979 conference four c o n t r i b u t i o n s should be mentioned which belong to the above scope: "VLSI Architecture f o r .Matrix Computations" by E. Horowitz, "A B i t - S l i c e Multi-Microprocessor System f o r Range A r i t h m e t i c " by W.H. Burkhardt, "A Parallel Microprocessing System", "LSI Implementation Options for the Shuffle-Exchange Network in a Microprogrammed SIMD-Array" by S. Ruhmann. Proceedings are available through IEEE and ACM p u b l i c a t i o n s respectively. L. Richter

ESSCIRC 79 The 5th European Solid State C i r c u i t s Conference (ESSCIRC 79), held at Southampton U n i v e r s i t y (September 18-20, 1979), attracted 225 delegates representing altogether 18 countries. The main attendance was from Europe, with s i g n i f i c a n t numbers from the United States and Japan. The general theme 'VLSI and A p p l i c a t i o n s ' was developed in a t o t a l of 60 papers, i n c l u d i n g 6 i n v i t e d addresses. The Japanese programme, which in many ways sparked o f f the current VLSI furore, was summarised by Professor T. Sugano of Tokyo Univ e r s i t y . The focus of the programme is apparently a new laboratory, to which has been seconded engineers and s c i e n t i s t s from a l l the major semiconductor manufacturers to ensure a cooperative e f f o r t . I t is intended that in due course they return to t h e i r parent firms to carry back the f r u i t s of t h i s j o i n t development- an approach to see translated to Europe. Professor H. Beneking described a German scheme f o r developing photol i t h o g r a p h i c techniques which brings together six i n d u s t r i a l and government laboratories. He also presented some s t a t i s t i c s showing Europe's dec l i n i n g r e l a t i v e share of IC production which is p a r t i c u l a r l y pronounced as c i r c u i t complexity increases, and which has been the reason for a number of government i n i t i a t i v e s . Two f u r t h e r i n v i t e d addresses, by Dr. D. Leakey and Dr. J. van Vessem, summed up positions in telecommunications and consumer e l e c t r o n i c s sectors r e s p e c t i v e l y , as being blessed with more technology than was needed i m m e d i a t e l y - w i t h a special push coming from the widespread a v a i l a b i l i t y of cheap d i g i t a l functions. Althougthese techniques were being exploited in the provision of better services from the central organiza-

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t i o n s , the customer end could only absorb much fewer functions of other than a gimmicky kind. This arose l a r g e l y from the increasing education needed before the general public could take f u l l advantage of the complex functions a v a i l a b l e . The education problem also e x i s t s in a d i f f e r e n t way for general equipment manufacturers and a very s i g n i f i c a n t trend to emerge from the Conference was the onslaught being made by IC manufacturers on shortening design time, both for t h e i r own and outside customer's use. The uncommitted l o g i c array is prominent here, backed by powerful computer systems to store c e l l - p a t t e r n s , simulate c i r c u i t behaviour, help with layout and f i n a l l y v e r i f y c i r c u i t functions. ICLandPlessey presented variants of t h i s approach, both based on fast 500 pS ECL, aimed to give design turnaround times of a few weeks with update/correction times of a few days. Racal/Mitel described a CMOS-cell system based on the same philosophy which was designed to give gate complexities of 400 to 800 on chips 150 thou square or 200 thou square, with a t y pical propagation delay around 40 ns. The aim was to carry out the f i n a l design and m e t a l l i s a tion at the equipment manufacturer's end. An equally promising and s l i g h t l y d i f f e r e n t approach suitable for n-channel MOSTwas described under the name ' M i c r o c e l l ' . Here sequent i a l c i r c u i t design is formalised by having regular horizontal bus-like structure beneath each row of f l i p - f l o p s , and gates can be d i s t r i buted i n t o t h i s bus as required. The s i m p l i c i t y of the design concept, coupled with e f f e c t i v e l y linked computer aids, again ensures a design cycle of a few weeks. Two f u r t h e r schemes aimed at smaller self-contained systems were also presented. F i r s t was a mask programmable uncommitted ROM-based sequent i a l machine with on-chip mains power supply. This included a variable state-time feature (analogue programmable) and the a b i l i t y to drive up to 12 LED or other loads. The other, a single chip special purpose computer with a 58 i n s t r u c tion set, was mounted in a 40-pin package, and was again designed to interface e a s i l y with a v a r i e t y of transducers and loads. Work on high speed systems was also presented, based on ECL processes of about 5 GHz fT- This included a range of fast A-D converters with I00 MHz conversion rates, 8 - b i t accuracy and on-chip reference voltage. The sample-and-hold c i r c u i t for t h i s range consisted of GaAs FETs, and was also described. S i m i l a r l y impressive c i r c u i t s were a 6 ns access time 64x4-bit RAM with 750 mW d i s s i p a t i o n , and a fast cascadable m u l t i p l i e r chip giving 1 6 x l 6 - b i t m u l t i p l i c a t i o n in i00 ns. The l a t t e r c i r c u i t was based on an advanced process described at ESSDERC (European Solid State Device Research Conference) which requires 23 masks. In predicting future d i r e c t i o n s for VLSI, Dr. B. Murphy of Bell Laboratories, came down in favour of CMOS ICs and looked forward to the day when