3-D numerical modeling and simulation of nanoscale FinFET for the application in ULSI circuits

Physica E 44 (2011) 80–86

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3-D numerical modeling and simulation of nanoscale FinFET for the application in ULSI circuits R. Ramesh a,n, M. Madheswaran b, K. Kannan c a

Department of Electronics and Communication Engineering, M.A.M College of Engineering, Trichy 621105, Tamilnadu, India Center for Advanced Research, Muthayammal Engineering College, Rasipuram, Tamilnadu, India c Department of Mathematics, SASTRA University, Thanjavur, Tamilnadu, India b

a r t i c l e i n f o

a b s t r a c t

Article history: Received 3 January 2011 Received in revised form 12 July 2011 Accepted 27 July 2011 Available online 4 August 2011

A complete three-dimensional numerical modeling of nanoscale FinFET including quantum-mechanical effects for the application in future ULSI circuits has been developed. The exact potential profile in the ¨ channel has been computed by obtaining a self-consistent solution of 3D Poisson–Schrodinger equation using Leibmann’s iteration method. The threshold voltage shift, drain and transfer characteristics have been estimated and the results were compared with the device simulator and experimental results. The model is purely a physics based one and overcomes the major limitations of the existing 2D/3D analytical models by providing a more accurate result and this model is validated by comparing with the existing results as well as the experimental results. & 2011 Elsevier B.V. All rights reserved.

1. Introduction A transition from bulk to multiple-gate fully depleted (FD) silicon-on-insulator (SOI) offers drive current and better shortchannel immunity [1]. CMOS designs below 0.1 mm are severely constrained by SCE and gate insulator tunneling [2–5]. One of the approaches to circumvent the gate tunneling restriction is to change the device structure so that the MOSFET gate length can be further scaled even with thicker oxide. Double-gate MOSFET (DGFET) is one of the most promising devices for channel length in the range 10–30 nm [6–9]. The alignment of the top and bottom gates to each other and to source/drain (S/D) doping are crucial to device performance, because misalignment may cause extra gate-to-S/D overlap capacitance as well as S/D series resistance [10]. In order to optimize the performance of double gate devices, self-aligned processes and structures are proposed, with FinFET being one of the most promising [11–15]. The FinFET is a symmetric three-gate structure, which means that all its three gates have the same work function and also at the same potential. This three dimensional (3-D) structure requires 3-D analysis. The potential variation in the channel used to calculate the subthreshold current and threshold voltage of FinFETs with doped and undoped channels has been reported [16]. Two dimensional (2-D) models can only be used to study the operation of the device along certain plane sections of the channel. An analytical model

n

Corresponding author. E-mail address: [email protected] (R. Ramesh).

1386-9477/$ - see front matter & 2011 Elsevier B.V. All rights reserved. doi:10.1016/j.physe.2011.07.010

based on 3-D analysis for an undoped channel has been reported [17]. El Hamid et al. [18] presented the 3-D analytical modeling including mobile charge term. Yang et al. [20] reported the scaling theory of FinFET by 3-D analytical solution of Poisson’s equation in channel region. The existing literatures reported on analytical modeling have shown the complexity in evaluating various device characteristics including QM effects. In addition, it has been found that many assumptions and approximations have to be incorporated while the device is analytically modeled. Quantum mechanical modeling is important for many reasons, e.g., the tunneling current through ultra-thin gate oxide adds to the low limit of the off-state current [20]. In FinFET devices, quantum effects and nonequilibrium, ballistic or near-ballistic transport has large impact on device performance [21]. For channel length comparable to the carrier scattering length, carriers transport ballistically. The inversion layer thickness cannot be treated same along the channel [21]. An analytical charge model based on self-consistent solution ¨ of Poisson’s and Schrodinger equation for 3-D FinFETs is carried out [22]. A ballistic quantum-mechanical simulation using CBR (Contact Block Reduction) method to investigate the behavior of 10 nm FinFET device is reported [23]. Double-gate FinFET devices with symmetric and asymmetric poly-silicon gates have been fabricated [24]. FinFET is developed with special emphasis on process simplicity and compatibility with conventional CMOS technology [25]. A simple capacitive model was proposed by Fried et al. [26] to predict the relationship between DIBL and S swing. Ben Abdallah et al. [27] proposed the modeling of ballistic quantum transport in nanostructures using the decomposition of the wave function with reduced simulation time. A numerical

R. Ramesh et al. / Physica E 44 (2011) 80–86

¨ scheme for the 1-D Schrodinger equation used to simulate a resonant tunneling diode uses the oscillating interpolating function from WKB asymptotic [28]. A 3-D quantum simulation of silicon nanowire transistors with an effective mass approximation using mode space approach producing high computational efficiency is proposed [29]. A numerical solution of coupled Poisson– ¨ Schrodinger equation for device modeling of nanoscale FinFET using Newton’s method has been reported [30]. In this paper, a 3D numerical model for n-channel nano-FinFET including QME using WKB asymptotics have been developed and presented. The prime focus is to obtain the device characteristics, considering QM ¨ effects by numerically solving the 3D Poisson–Schrodinger equations directly using Leibmann’s iteration method until self-consistency is achieved. The 3-D simulation is necessary to describe the 3-D characteristics of FinFET structure. Thus the structure symmetry should be used to reduce the mesh node count and simulation time. The WKB approximation is a more efficient method for approximation of the device parameters. When ¨ solving the Poisson–Schrodinger equations with standard finite element or finite difference methods require a large number of grid points thus increasing unnecessarily the numerical cost. In Ref. [21], the WKB approximation is used for the wave function in the x-direction and the self-consistent solution of 3-D Poisson– ¨ Schrodinger equation is obtained using Newton’s iteration method. But it does not discuss the direct 3-D modeling of ¨ nanoscale devices using Poisson–Schrodinger equations. In this ¨ paper, a direct 3-D numerical solution of the Poisson–Schrodinger equation is obtained until self-consistency is achieved. This reduces the numerical cost of the simulation and produces more accurate results with much coarser grids. This method provides a very good performance in terms of CPU time savings and fast convergence; the evaluation of grid refinement does not require computations introducing significant overhead. Though there are several methods available in the literature to solve the Poisson equation (variable separable, perturbation schemes, operator split method, etc.), they focus on several types of solutions that do not cater to the solution of a real time problem suitable for numerical modeling. Hence a numerical modeling that generates functional values at selected grid points must be developed. One such numerical model is Leibmann’s iterative scheme. The advantages of Leibmann’s iteration method are: (1) Arbitrary choice of initial values. (2) Alternative procedures like diagonal averaging and cross averaging. (3) Very low error rate (order of h4). (4) Established convergence. (5) Unconditionally stable. In our work, this Leibmann’s iteration modeling is proposed, since it has the above-mentioned merits. Detailed comparative study clearly indicates that this scheme is an apt scheme for our proposed problem as it is of lower error rate and less time consuming. The

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accuracy of our method is verified with simulator and experimental results to validate our method obtained from other references.

2. Physics based modeling The general FinFET structure is shown in Fig. 1. The following are the geometrical parameters: (1) Gate length (Lg): The physical gate length of FinFETs, defined by spacer gap. (2) Fin height (Hfin): The height of silicon fin, defined by the distance between the top gate and buried oxide layer (BOX). (3) Fin width (Tfin): The thickness of silicon fin, defined between the front and the back gates. (4) Top gate thickness (Tox1): The thickness of the top gate oxide. (5) Front or back gate thickness (Tox2): The thickness of the front or back gate oxide. (6) Channel length (Leff): The channel length is estimated by the metallurgical junction for abrupt junctions. (7) Geometrical channel width defined as W¼2  Hfin þTfin. Obviously, when Tfin is much larger than Hfin or when top gate oxide is much thinner than the front and back oxides, FinFET can be treated as single-gate fully depleted SOI MOSFET (FDFET) as long as the silicon fin remains fully depleted [17]. When Hfin is much larger than Tfin or top gate oxide (Tox1) is much thicker than the front and back oxides (Tox2), FinFET can be treated as DGFET [17]. It is difficult to assume a simple potential distribution because of its asymmetric 3-D structure. The electrostatic potential in the subthreshold region can be described by the 3-D Poisson’s equation. @2 Uðx,y,zÞ @2 Uðx,y,zÞ @2 Uðx,y,zÞ þ þ @x2 @y2 @z2 q½Na ðx,y,zÞ þ nðx,y,zÞpðx,y,zÞ ¼

es

ð1Þ

where U(x,y,z) is the surface potential at a particular point (x,y,z), Na(x,y,z) is the uniform channel doping concentration, q is the electronic charge, es is the permittivity of silicon, n(x,y,z) is the electron concentration and p(x,y,z) is the hole concentration. Poisson’s equation follows directly from Maxwell’s equations if all time derivatives are zero (i.e.) for electrostatic conditions. Maxwell’s equation describes the behavior of electric and magnetic fields and their interaction with matter. This Poisson’s equation can be used to describe the whole simulation domain of a semiconductor device. They are applied to the bulk semiconductor, the highly doped regions such as the source and drain, and to dielectric regions such as gate dielectric. nðx,y,zÞ ¼ ni e½Uðx,y,zÞmF ðxÞ=VT

ð2Þ

where ni is the intrinsic electron density in silicon, VT is the thermal voltage and mF is the non-equilibrium quasi-Fermi level referenced to the Fermi level in the source satisfying the following

Fig. 1. Schematic diagram of FinFET.

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2.1. Model for quantum mechanical ballistic transport

boundary conditions:

mF ð0Þ ¼ 0;

mF ðLÞ ¼ Vds

ð3Þ

where Vds is the drain to source voltage.The Fermi-Dirac distribution at the source end is given by [21] Fðms EÞ ¼

1 1 þ eðEms =KB TÞ

ð4Þ

At the drain end 1 1 þ eðEmds =KB TÞ

Fðmd EÞ ¼

ð5Þ

In 2-D or 1-D quantum mechanical models, the device channel is confined in one or two dimensions [20], and the energy in the third dimension is continuous. Hence the function F(m  E) needs to be integrated over the energy space to obtain the transverse mode density of states. For a 2-D model, a Fermi-Dirac integral of 1/2 is obtained. In a 3-D model, all the three dimensions are confined, so there is no need to obtain integration and the Fermi distribution is used directly. The six boundary conditions are set by the top gate, front gate, back gate, source, drain and buried oxide (Fig. 1). The buried oxide is assumed to be thick enough that any finite potential across the buried oxide leads to a negligible electric field. The boundaries between gate oxide and silicon fin are eliminated by replacing the physical dimensions with effective dimensions. The whole region is treated as homogenous silicon with effective thickness (Teff), effective channel length (Leff) and effective height (Heff) [19]. Because, in the short channel device, the lateral electric field becomes comparable to the normal electric field, the geometrical average method should be adopted [17] to reduce errors. These two effective parameters are defined by [19] sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi   4e Teff ¼ Tfin Tfin þ si Tox2 ð6Þ

eox

Heff

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi  ffi 2esi ¼ Hfin Hfin þ Tox1

eox

ð7Þ

where eox is silicon-oxide permittivity. With all the assumptions and approximations above, the boundary conditions are simplified as [19] Top gate: U9y ¼ H ¼ Vg Vfb eff

ð8Þ

eff=2

¼ Vg Vfb

ð9Þ

Back gate: U9z ¼ T

eff=2

¼ Vg Vfb :

ð10Þ

ð11Þ

Drain: U9x ¼ L ¼ Vbi þ Vds eff

ð12Þ

Bottom gate: U9y ¼ H ¼ Vg Vfb: eff

cx ¼ 0 ¼ 0, cx ¼ Leff ¼ 1; cy ¼ 0 ¼ 0, cy ¼ Heff ¼ 0; cz ¼ Teff =2 ¼ 0, cz ¼ Teff =2 ¼ 0

ð15Þ

The drain current ID considering scattering effects is given by [18,19] ID ¼

Wqni ðVgs VT Þð1expððVds =VT ÞÞ RL RH R Tfin=2 ½ð1=uT Þ þð1=Deff =‘Þ 0 ðdx= Hfin=2 Tfin=2 exp½UðxÞ=VT dy dzÞ fin=2

ð16Þ pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi n where uT ¼ 2KB T=pm is the thermal velocity and is independent of the Fermi level. Deff ¼(KBT/q)meff is the diffusion coefficient. For low Vds, the critical length ‘-L, the channel length. Assuming that only the lowest side band is occupied, the effective mass is m * ¼mt ¼0.19m0, which gives a thermal velocity 1 1 uT ¼1.2  107 cm/s. By Mathiessen’s rule where m1 eff ¼ m0 þ mB mB ¼qLm * puT is the ballistic mobility and mB ¼ qL/m * puT is the low field mobility, l is the mean free path, and W¼Tfin is the width of the device. The subthreshold swing S is a measure of the gate control on the channel. It can be expressed as S¼

S¼

@Vgs @ log IDS ln 10

1

b 12G11 ea Sinðpðxc þ a þ cÞ=aeff ÞSinðpðyc þb þ dÞÞ=beff ð17Þ

where b and a are defined as q KT a ¼ Leff =2l11 ¼ Leff =2L aeff ¼ 2ða þ cÞ; beff ¼ 2ðb þ dÞ a ¼ Tfin =2; b ¼ Hfin ; c ¼ Teff =2a;     1 mp 2 np 2 ¼ þ aeff beff l2 mn

Gmn ¼

Source: U9x ¼ 0 ¼ Vbi

where mnx , mny, mnz are effective masses in the x, y and z directions, respectively. mnx ¼ ml ¼ 0:916m0 , mny ¼ mt ¼ 0:19m0 , mnz ¼ mt ¼ 0:19m0 . E is the eigen energy, _ is the reduced Planck’s constant, q is the charge of an electron, U(x, y, z) is the surface potential, and ¨ c(x,y,z) is the eigen wave function. The 3-D Schrodinger Eq. (14) is solved using the following boundary conditions by Leibmann’s iteration method.

b¼

Front gate: U9z ¼ T

¨ The 3D effective mass Schrodinger equation along the n-channel is given by [21] " # _2 @2 _2 @2 _2 @2  þ þ þ qU cx,y,z ¼ Ecx,y,z ð14Þ ðx,y,zÞ 2mnx @x2 2mny @y2 2mnz @z2

ð13Þ

Due to the symmetrical structure in the z direction, the buried oxide boundary condition at the bottom qU/qz9y ¼ 0 ¼0 is replaced with the bottom gate boundary condition.

d ¼ Heff b

16 mnp2

xc and yc describe the position of the leakage path in the fin cross section. xc could be set to zero due to symmetry, while yc is determined by the geometrical features, doping concentration, and applied voltages. Practically, yc is treated as a fitting parameter. Substituting yc ¼Hfin in Eq. (17) becomes a lower limit of subthreshold swing. Vds is set as 0.05 V, and the lateral electric field along the channel is moderate. Hence, the drift-diffusion is accurate to describe the subthreshold conduction in FinFETs [15]. The subthreshold drain current is given by Z t0 Z h0 IDS ¼ ni eUðxÞ=VT dx dy ð18Þ t0

h0

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The threshold voltage (Vth) roll-off is given by [19]  qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi Leff Sq exp DVth ¼ a p Vbi ðVbi Vds Þ9Vbi 9 2:3KT 2Ld

Step 10. ð19Þ

1 Ld ¼ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ða=Teff Þ2 þðb=Heff Þ2 where Ld is the drain potential decay length, Vbi is the built-in potential equal to about half of the Si bandgap. Eq. (19) shows that the Vth roll-off is an exponential function of Leff/Ld. Vth roll-off caused by DIBL is estimated by the necessary gate voltage change in the most leaky path (xc,yc) [17]. If the channel furthest away from the gates, i.e., xc ¼Teff/2, yc ¼0, is chosen as the most leaky path, the sine and cosine terms will be reduced to 1.

3. Computational technique The 3D Poisson’s Eq. (1) using the boundary conditions ((8)–(13)) is solved numerically using Leibmann’s iterative method to determine the surface potential for a fixed value of gate voltage and assumed value of drain voltage. This value of ¨ surface potential is given to the 3D Schrodinger Eq. (14). The 3-D ¨ Schrodinger equation is then solved numerically using Leibmann’s iteration method and the exact value of surface potential is obtained. The potential at every point in the channel and its variation along the channel length is calculated using Leibmann’s iteration method as Uði,j,lÞ ¼ Uði1,j,lÞ þUði þ 1,j,lÞ þ Uði,j1,lÞ þ Uði,j þ 1,lÞ þ Uði,j,l1Þ þ Uði,j,l þ1Þ þ ðqNa ði,j,lÞ þ nði,j,lÞpði,j,lÞ=es Þ=6 An iterative approach has been adopted to calculate U(i,j,l) with the help of available boundary conditions. The potential at subsequent points towards drain end is calculated numerically and the device characteristics are estimated. Leibmann’s iteration method is an iterative method used to solve a linear system of equations. Unlike the Jacobi method, only one storage element is required as elements can be overwritten as they are computed, which can be advantageous for large problems with good convergence. The drain current can be estimated by numerically integrating the Eq. (16) using Simpson’s one-third rule. The subthreshold swing and threshold voltage roll-off values are estimated using Eqs. ((17) and (19)).The results obtained are validated with commercial device simulator results and experimental values. Algorithm Step 1. Step 2. Step 3. Step 4.

Step 5. Step 6. Step 7.

Step 8. Step 9.

Assign gate length, channel length, device width, height and thickness of silicon fin. Apply bias voltages. Start with a trial potential U(x,y,z). Obtain the electron concentration n(x,y,z). Determine numerically the surface potential by solving the 3D Poisson’s equation using Leibmann’s iteration method by 20  20  20 iterations. Substitute this surface potential value in the 3D ¨ Schrodinger’s equation. ¨ Solve the 3-D Schrodinger’s equation using Leibmann’s iteration method. Calculate new n(x, y, z) value from the obtained wavefunctions and their corresponding eigenenergies. A new surface potential value U(x, y, z) is obtained. Calculate the relative error of the surface potential between the exact and simulated values.

Step 11. Step 12.

83

Repeat step 4 to step 9 until it converges (erroro0.0001) by increasing the number of iterations. Estimate the exact value of surface potential at every point along the channel length. Obtain subthreshold swing, threshold voltage rolloff and drain characteristics of the device.

4. Results and discussion Numerical computation has been carried out for the nanoscale FinFET. The parameters used for the calculation are given in Table 1. Fig. 2 shows the potential profile of the FinFET including QM effects obtained using Leibmann’s iteration method on a grid of 20  13  10 points is compared with the reference solution obtained from DAVINCI simulator [18] (broken line). The surface potential U(x) is calculated for different values of x. Leibmann’s iteration method shows a good agreement with the reference values and gives more accurate values due to quantum mechanical effects. Fig. 3 shows the three dimensional view of surface potential of nanoscale FinFET including quantum mechanical effects for Vds ¼0.8 V. The S-factor, which is a measure of the subthreshold behavior of the device, is extracted from the Ids–Vgs characteristics of the FinFET device. Fig. 4 shows the comparison of surface potential values obtained using Leibmann’s iteration method with the WKB values including quantum mechanical effects for Vds ¼1.5 V. It is found that Leibmann’s iteration method provides more accurate results than the WKB approximation because the WKB approximation underestimates the density of electrons penetrating into the channel under the potential barrier U(x,y,z). The S-factor for various channel lengths and fin thickness for a constant fin height are obtained from the device simulation and Table 1 Parameters and constants. Parameter

Value

Gate length (Lg) Top gate oxide thickness (Tox1) Front (or) back gate thickness (Tox2) Channel length (Leff) Thermal voltage (VT) Intrinsic carrier concentration (ni) Acceptor concentration (Na) Flatband voltage (Vfb) Built-in potential (Vbi) Gate voltage (Vg)

60 nm 5 nm 1 nm 60 nm 0.025852 V 9.65  109/cm3 1  1016/cm3  0.48 V 0.6 V 0.2 V

Fig. 2. Three dimensional potential variation along the channel length for various Vds values. Vg ¼ 0.2 V, Hfin ¼ 60 nm, Tfin ¼ 20 nm and Leff ¼ 60 nm. The dotted lines show DAVINCI simulated values at Vds ¼ 0.8 V [18].

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Fig. 5. Subthreshold swing along channel length for various Tfin values at Hfin ¼60 nm and Vds ¼ 1.5 V. Fig. 3. Three dimensional view of surface potential for Vds ¼0.8 V.

Fig. 4. Comparison of surface potential for various methods for Vds ¼ 1.5 V, Vgs ¼ 0.2 V, Hfin ¼ 50 nm, and Tfin ¼20 nm.

shown in Fig. 5. The calculated subthreshold swing (S) is 71.56 mV/ dec at Vds ¼1.5 V. This is due to the fact that the punch-through is successfully interrupted by the thin body of FinFET. The comparison of S-factor values with Taurus simulator values for various channel lengths and fin thickness for Hfin ¼60 nm and Vds ¼1 V is shown in Fig. 6. It is found that the S-factor increases exponentially with decreasing channel length. From Fig. 7 it is observed that as the Hfin is increased from 20 to 100 nm, the saturation of S is observed [17]. The critical Hfin needed for saturation is different for devices with different Tfin [17]. The simulated results are compared with experimental results [17] to validate our method. It is found that the simulated results are in good agreement with experimental results. Fig. 8 shows that S changes more rapidly as Tfin changes from 10 to 60 nm, the rate of change increases initially and then slow down. At high Vds values (Vds ¼1.5 V), the electric field will increase at the back surface compared to the top surface and compared with experimental results for Hfin ¼ 65 nm [17]. A good agreement has been obtained with experimental values in Fig. 9 [18], for xc at approximately 77% of Tfin and yc at 99% of Hfin for Vds ¼1 V. The position of the most leaky path is highly dependent on the channel doping, gate bias and device geometry. For the case of undoped channel and deep subthreshold operation, the device geometry is the dominant variable. The closer the channel path to the gate, the more source barrier is reduced by the gate, while for the channel away from the gate, the more source barrier is reduced by the source/ drain potential [17]. If the source/drain potential penetration is the dominant factor in determining the source barrier, the most leaky path will be the channel path away from the gate. The source/drain potential includes the built-in potential, Vbi and applied drain bias, Vds [18]. Fig. 10 shows the comparison of subthreshold swing for various Hfin values at low Vds value (Vds ¼20 mV) and compared with

Fig. 6. Comparison of subthreshold swing along channel length with Taurus simulator values for different Tfin values and Vds ¼ 1 V [18].

Fig. 7. Subthreshold Swing for different Tfin values for Leff ¼ 60 nm, Vds ¼ 1.5 V and compared with experimental values [17].

Fig. 8. Subthreshold swing for various Hfin values, Leff ¼60 nm, and Vds ¼ 1.5 V.

R. Ramesh et al. / Physica E 44 (2011) 80–86

Fig. 9. Comparison of subthreshold swing for various fin thickness with experimental values at Hfin ¼ 60 nm, Leff ¼ 60 nm, and Vds ¼1 V.

Fig. 10. Comparison of Subthreshold swing for various Hfin values with experimental values at Hfin ¼ 60 nm, Leff ¼60 nm, and Vds ¼ 20 mV.

experimental results [18]. It shows that the simulated subthreshold swing values are in good agreement with experimental results. The simulated Id  Vgs characteristics are shown in Figs. 11 and 12. The drain current normalized by the channel width W at the same Vgs is almost independent of Hfin while fixing Tfin. Excellent match with results obtained from experimental work is observed. The small differences in the normalized drain current with same Hfin and different Tfin come from the threshold voltage roll-off due to increase in Tfin [17]. The normalized drain current of FinFET with 10 nm Hfin is almost twice that of FinFET with 30 nm Hfin [17]. Depending on the relative ratio of Tfin to Hfin, either one of these two parameters can be the dominant parameter controlling the short channel effects (SCE) of FinFET. For a given Leff, changing the dominant parameter will lead to big changes in Vth roll-off and subthreshold swing (S) values, while changing the nondominant parameter will result in small changes or almost no changes .This is because the channel is controlled by two gates on the sides while only one gate on the top and no gate at the bottom. The subthreshold current versus gate bias Vgs obtained using Leibmann’s iteration method for different values of Vds are shown in Fig. 13. The subthreshold current is supposed to be accurate to study the subthreshold behavior of nanoscale FinFET. The result is compared with DAVINCI simulated result for Vds ¼0.5 V for validation of the method. It can be seen that the subthreshold current increases with increase in Vds values. The ID–VD characteristics of nanoscale FinFET are shown in Fig. 14. It shows that the subthreshold leakage current is well suppressed even at low doping concentration (1  1016 cm  3). It is also found that there is no kink effect, which is produced due to floating body. DVth obtained from Leibmann’s iteration method at

85

Fig. 11. Id–Vgs characteristics of FinFET for various Tfin values at Hfin ¼ 60 nm, Leff ¼ 60 nm, and Vds ¼1.5 V.

Fig. 12. Id–Vgs characteristics of FinFET for various Hfin values at Tfin 40 nm, Leff ¼ 60 nm, and Vds ¼1.5 V.

Fig. 13. Subthreshold drain current as a function of gate voltage for various drain voltages and comparison with DAVINCI simulator results for Vds ¼0.5 V.

different Vds is compared with the Taurus simulated results and experimental results [17] in Fig. 15. In a FinFET, the minimum potential in the semiconductor volume rather than minimum surface potential determines the threshold voltage. The good match between these results validates our method. The FinFET structure and the parameters used in our work and Refs. [17,18] are the same. 4.1. Numerical efficiency Tables 2 and 3 show the comparison of Leibmann’s iteration method with DAVINCI and Taurus simulator results. The simulation

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5. Conclusion

Drain Current (µA)

10 8 6 4 2 0 0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

Vds (V) Fig. 14. Drain current characteristics of FinFET for various Vgs values.

The 3-D numerical model presented here can be used for the practical characterization of three dimensional nanoscale FinFET. The device can be very well considered to be a nanodevice as all the dimensions are in nanometer range. The quantum transport modeling of this device based on the self-consistent solution ¨ of 3-D Poisson–Schrodinger equation has shown numerically the efficiency of Leibmann’s iteration method as compared to device simulator results. The subthreshold swing, threshold voltage roll-off, drain characteristics enhance the study of various other parameters of the device. Accurate results have been obtained with significantly reduced computational time. These device characteristics can also be extended to illuminated condition to prove the suitability of this device as a high speed photodetector.

References

Fig. 15. Comparison of threshold voltage roll-off with Taurus simulator solutions at different Vds values. Table 2 Comparisons of the simulation times & mean relative errors of Taurus simulator & Leibmann’s iteration method for different meshes. No. of grid points in x,y,z

Simulation time Leibmann’s iteration method (s)

20  13  10 102 45  32  23 642 60  49  34 1568

Mean rel. error Leibmann’s iteration method

Simulation time Taurus (s)

Mean relativeerror Taurus

0.0523 0.0265 0.0183

108s 687 1655

0.1135 0.0948 0.0336

Table 3 Comparisons of the simulation times and mean relative errors of DAVINCI and Leibmann’s iteration method for different meshes. No. of grid points in x,y,z

Simulation time Leibmann’s iteration method (s)

20  13  10 102 45  32  23 642 60  49  34 1568

Mean rel. error Leibmann’s iteration method

Simulation time DAVINCI (s)

Mean relative error DAVINCI

0.0523 0.0265 0.0183

110 703 1710

0.2158 0.1054 0.0564

is done using Matlab version 7.0.1 with a personal computer using Intel Dual Core Processor. It is found that the simulation time and the relative error reduces considerably with Leibmann’s iteration method.

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