- Email: [email protected]
4548451 Pinless connector interposer and method for making the same
600
New Patents
4548451 PINLESS CONNECTOR INTERPOSER AND METHOD FOR MAKING THE SAME Garry M Benarr, Terry A Burns, William Walker assigned to International Business Machines Corporation
~,,~
~ ~
A circuit for generating an equalization pulse for test purposes uses an equalization pulse generator which generates an equalization pulse in response to receiving one or more address transition signals generated from an address transition. The address transition signals are received by a multi-input logic circuit which causes the equalization pulse to be present at least as long as a signal is present at one of the inputs. A test pad on the integrated circuit receives an cxternally generated test signal of variable duration. The test signal is coupled to an input of the logic circuit to generate the equalization pulse for the duration of the test signal.
4549200
A pinless connector interposer for making densely populated, inexpensive, simple, reliable, self-wiping connections between components used in semiconductor packaging such as semiconductor carrying substrates, flexible and rigid printed circuit boards and cards. The connector interposer comprises an elastomeric base member in which deformable protrusions are formed on both the top and bottom surface of the base member, wherein the protrusions correspond to contact pads of semiconductor packaging components. An electrically conductive metal coated flexible overlay is bonded to the base member, forming electrically conductive tab elements, enabling a multitude of connections to be made to a semiconductor package. The connections can be accommodated on centers as low as 0.025 inches, despite the non-planarity that may exist between the packaging components of a system.
4549101 CIRCUIT FOR GENERATING TEST EQUALIZATION PULSE Lal C Sood assigned to Motorola Inc
REPAIRABLE MULTI-LEVEL OVERLAY SYSTEM FOR SEMICONDUCTOR DEVICE Mario E Ecker, Leonard T Olson assigned to International Business Machines Corporation
A multi-level integrated circuit packaging system having a primary support frame, an array of secondary support frames mounted in said primary support frame and an array of single chip carriers associated with each secondary support frame. An integrated circuit is encapsulated in each single chip carrier, which may be a variety of carrier types which has an insulated wiring pattern with EC wells and delete lands. The secondary and primary support frames also have EC pads so that a change capability exists to any electrical signal path terminating on the chip.
34
%0
vvo K 3 TM
~
Arx°
4549249 OVERHEAD LIGHTING SYSTEM FOR ONE OR MORE VISUAL DISPLAY TERMINALS Sylvan R Shemitz assigned to Sylvan R Shemitz and Associates Inc
New Patents
4548451 PINLESS CONNECTOR INTERPOSER AND METHOD FOR MAKING THE SAME Garry M Benarr, Terry A Burns, William Walker assigned to International Business Machines Corporation
~,,~
~ ~
A circuit for generating an equalization pulse for test purposes uses an equalization pulse generator which generates an equalization pulse in response to receiving one or more address transition signals generated from an address transition. The address transition signals are received by a multi-input logic circuit which causes the equalization pulse to be present at least as long as a signal is present at one of the inputs. A test pad on the integrated circuit receives an cxternally generated test signal of variable duration. The test signal is coupled to an input of the logic circuit to generate the equalization pulse for the duration of the test signal.
4549200
A pinless connector interposer for making densely populated, inexpensive, simple, reliable, self-wiping connections between components used in semiconductor packaging such as semiconductor carrying substrates, flexible and rigid printed circuit boards and cards. The connector interposer comprises an elastomeric base member in which deformable protrusions are formed on both the top and bottom surface of the base member, wherein the protrusions correspond to contact pads of semiconductor packaging components. An electrically conductive metal coated flexible overlay is bonded to the base member, forming electrically conductive tab elements, enabling a multitude of connections to be made to a semiconductor package. The connections can be accommodated on centers as low as 0.025 inches, despite the non-planarity that may exist between the packaging components of a system.
4549101 CIRCUIT FOR GENERATING TEST EQUALIZATION PULSE Lal C Sood assigned to Motorola Inc
REPAIRABLE MULTI-LEVEL OVERLAY SYSTEM FOR SEMICONDUCTOR DEVICE Mario E Ecker, Leonard T Olson assigned to International Business Machines Corporation
A multi-level integrated circuit packaging system having a primary support frame, an array of secondary support frames mounted in said primary support frame and an array of single chip carriers associated with each secondary support frame. An integrated circuit is encapsulated in each single chip carrier, which may be a variety of carrier types which has an insulated wiring pattern with EC wells and delete lands. The secondary and primary support frames also have EC pads so that a change capability exists to any electrical signal path terminating on the chip.
34
%0
vvo K 3 TM
~
Arx°
4549249 OVERHEAD LIGHTING SYSTEM FOR ONE OR MORE VISUAL DISPLAY TERMINALS Sylvan R Shemitz assigned to Sylvan R Shemitz and Associates Inc