4891782 PARALLEL NEURAL NETWORK FOR A FULL BINARY ADDER John L America as Army
assigned
United States the Secretary of
for addition of Nnumbers using parallel netThe of a register is and into second in mathematical fashion so as add the of first register into second When the register contains zeros then desired sum is in the register.
o translate, according to (1) the timing of the keypresses, (2) the presence or absence of a delimiter character at the beginning or end of a group of keypresses, (3) the presence or absence of the group of keypresses in a dictionary of stored groups of keypresses, and/or (4) the sequence of keypresses that preceded or followed the group.
A bit
4891787 PARALLEL PROCESSING SYSTEM WITH PROCESSOR ARRAY HAVING SIMD/MIMD INSTRUCTION PROCESSING David K Gifford assigned to Massachusetts Institute of Technology
4891786 STROKE TYPING SYSTEM Eric Goldwasser
A storage method and control system for creating linguistic expressions such as natural language text by both sequential and simultaneous keypresses. The system controls a programmable digital processor to receive keypresses from the operator and to translate groups of keypresses to linguistic expressions or
A highly-parallel processing system in which a number of processing elements are interconnected by a network, and are also connected to a system bus and are controlled by a central processing unit. Each processing element includes a memory, and all of the memories in the processing elements form at least part of the memory available to the CPU. The processing elements normally execute programs in MIMD mode, and the CPU or another unit can interrupt them to execute a SIMD instruciton. The network allows for transmission of variable length messages and also for combining messages when received at a common processing element.
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