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4906921 Structure and process for testing integrated circuits permitting determination of the properties of layers
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New Patents
4906921 STRUCTURE AND PROCESS FOR TESTING INTEGRATED CIRCUITS PERMITTING DETERMINATION OF THE PROPERTIES OF LAYERS Andre Juge, Saint Egreve, France assigned to SGS-Thompson Microelectronics S A The instant invention relates to a test structure for an integrated circuit for determining the incidence of various conduction effects on given layers and separating the surface effects from the wedge effects and the periphery effects into two perpendicular directions, wherein test patterns of determined shapes are incorporated into elementary components comprising the given layers transversely polarized, further comprising at least four test patterns (1 I, 13, 15, 17) in which the given layers are delimited according to four rectangles, each of which has a common dimension with another one, that is, those four rectangles have only two length values (YD) and two width values (XD).
4907065 INTEGRATED CIRCUIT CHIP SEALING ASSEMBLY Vahak K Sahakian assigned to LSI Logic Corporation An integrated circuit (IC) chip package is formed by extending the overall dimensions of a standard IC on a semiconductor substrate, typically a first silicon wafer, to provide an integral band of semiconductor material therearound on which are formed a series of spaced IC chip input/output pad areas extending along the band. A bottom peripheral edge of a discrete cap of the same semiconductor material, e.g. silicon, is sealingly affixed around an inner periphery of the band inboard of the series of pad areas and outboard of the IC active circuit areas, so that the cap interior spacedly covers the active circuit
area and the input/output pad areas are exposed. The caps may be made by photolithography and microetching techniques from a second semiconductor wafer of the same type as the IC wafer. Metallization extends on the first wafer from connect pads on the active circuit area to the extended and exposed input/output pad areas exterior of the cap. The IC may be probed for test purposes prior to capping. Use of lead frames, plastic encapsulation processes and a ceramic housing are avoided, while maximizing the use of compatible materials having the same coefficient of thermal expansion. In one embodiment, essentially an all silicon package is provided.
4907230 APPARATUS AND METHOD FOR TESTING PRINTED CIRCUIT BOARDS AND THEIR COMPONENTS Rik Heller, Henrick Krigel Apparatus and method for testing electrical circuits, especially printed circuit boards containing a number of integrated circuit components. Access to the component to be tested is by means of a clip with driver/sensor pins having field effect transistor circuitry. Each pin corresponds to an access point on the device under test, and each pin includes its own circuitry for driving the inputs and sensing the outputs of both analog and digital components. The test instrumentation is integrated with a host microcomputer, eliminating the need for memory behind the pins . Test programming directs the test instrumentation to perform functional testing while the components are in circuit and to test for in-circuit component parameters. The invention provides automatic test generation, including means for learning the characteristics of known good components and boards. The invention also provides expert system programming for recording and analyzing test results data and for using this data to generate faster tests.
For information about PATSEARCH ~
Pergamon Orbit InfoLine Inc. 8000 Westpark Drive McLean, VA 22102 USA
Telephone (703) 442-0900 Telex: 90-1811
Pergamon Orbit InfoLine Ltd 12 Vandy Street London EC2A 2DE UK Telephone (01) 377-4650 Telex: 8814614
New Patents
4906921 STRUCTURE AND PROCESS FOR TESTING INTEGRATED CIRCUITS PERMITTING DETERMINATION OF THE PROPERTIES OF LAYERS Andre Juge, Saint Egreve, France assigned to SGS-Thompson Microelectronics S A The instant invention relates to a test structure for an integrated circuit for determining the incidence of various conduction effects on given layers and separating the surface effects from the wedge effects and the periphery effects into two perpendicular directions, wherein test patterns of determined shapes are incorporated into elementary components comprising the given layers transversely polarized, further comprising at least four test patterns (1 I, 13, 15, 17) in which the given layers are delimited according to four rectangles, each of which has a common dimension with another one, that is, those four rectangles have only two length values (YD) and two width values (XD).
4907065 INTEGRATED CIRCUIT CHIP SEALING ASSEMBLY Vahak K Sahakian assigned to LSI Logic Corporation An integrated circuit (IC) chip package is formed by extending the overall dimensions of a standard IC on a semiconductor substrate, typically a first silicon wafer, to provide an integral band of semiconductor material therearound on which are formed a series of spaced IC chip input/output pad areas extending along the band. A bottom peripheral edge of a discrete cap of the same semiconductor material, e.g. silicon, is sealingly affixed around an inner periphery of the band inboard of the series of pad areas and outboard of the IC active circuit areas, so that the cap interior spacedly covers the active circuit
area and the input/output pad areas are exposed. The caps may be made by photolithography and microetching techniques from a second semiconductor wafer of the same type as the IC wafer. Metallization extends on the first wafer from connect pads on the active circuit area to the extended and exposed input/output pad areas exterior of the cap. The IC may be probed for test purposes prior to capping. Use of lead frames, plastic encapsulation processes and a ceramic housing are avoided, while maximizing the use of compatible materials having the same coefficient of thermal expansion. In one embodiment, essentially an all silicon package is provided.
4907230 APPARATUS AND METHOD FOR TESTING PRINTED CIRCUIT BOARDS AND THEIR COMPONENTS Rik Heller, Henrick Krigel Apparatus and method for testing electrical circuits, especially printed circuit boards containing a number of integrated circuit components. Access to the component to be tested is by means of a clip with driver/sensor pins having field effect transistor circuitry. Each pin corresponds to an access point on the device under test, and each pin includes its own circuitry for driving the inputs and sensing the outputs of both analog and digital components. The test instrumentation is integrated with a host microcomputer, eliminating the need for memory behind the pins . Test programming directs the test instrumentation to perform functional testing while the components are in circuit and to test for in-circuit component parameters. The invention provides automatic test generation, including means for learning the characteristics of known good components and boards. The invention also provides expert system programming for recording and analyzing test results data and for using this data to generate faster tests.
For information about PATSEARCH ~
Pergamon Orbit InfoLine Inc. 8000 Westpark Drive McLean, VA 22102 USA
Telephone (703) 442-0900 Telex: 90-1811
Pergamon Orbit InfoLine Ltd 12 Vandy Street London EC2A 2DE UK Telephone (01) 377-4650 Telex: 8814614