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4933042 Method for packaging integrated circuit chips employing a polymer film overlay layer
viii
New Patents
4932028
4933860
E R R O R L O G S Y S T E M FOR SELF-TESTING IN VERY LARGE SCALE INTEGRATED CIRCUIT (VLSI) UNITS
METHOD FOR FABRICATING A RADIO FREQUENCY INTEGRATED CIRCUIT AND PRODUCT FORMED THEREBY
Haluk Katircioglu, John A De Beule, Debaditya Mukherjee, Gary C Whitlock assigned to Unisys Corporation A VSLI chip is implemented with registers which log permanent and intermittent errors occurring within the chip as sensed by concurrent error detection circuitry (CED). If a fatal error is detected (one which would destroy the reliability of chip operations), then the chip is immobilized into a hold mode (freeze). Interrupts are signalled to a cooperating maintenance controller which can pass the error information to an external computer for display and for locating a faulty area.
Louis C Liu assigned to TRW Inc A method of designing and fabricating a semiconductor integrated circuit for operation at radio frequencies. The method includes fabricating an integrated circuit having circuit components, at least one of which is an active device, testing the electrical performance of at least one of the active devices and then forming an electrical conductor to the integrated circuit to interconnect selected ones of the circuit components to form a radio frequency circuit, wherein the selection is based on the outcome of the electrical performance test.
4935378 M E T H O D FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING MORE THAN TWO CONDUCTIVE LAYERS
4933042 METHOD FOR PACKAGING INTEGRATED CIRCUIT CHIPS EMPLOYING A POLYMER FILM OVERLAY LAYER Charles W Eichelberger, Robert Wojnarowski, Kenneth Welles assigned to General Electric Company A method and apparatus are provided for disposing a polymer film on an irregularly-shaped substrate at relatively high temperatures. In particular, the method and apparatus of the present invention provide a system for the packaging of very large scale intergrated circuit chips. The system of the present invention particularly solves problems associated with high temperature processing and problems associated with the highly irregular surfaces that result. Nonetheless, the resultant product is capable of being fashioned into circuit chip systems which are independently testable and which may be reconfigured after testing by removal of the polymer film itself.
Seiichi Mori, Tokyo, Japan Kabushiki Kaisha Toshiba
assigned
to
According to a semiconductor device manufacturing method of the invention, a first polycrystalline silicon layer doped with an impurity, a thin oxide film, a second polycrystalline silicon layer, and a silicon nitride film are sequentially formed, one upon the other. The silicon nitride film, the second polycrystalline silicon layer, the thin oxide film, and the first polycrystalline silicon layer are then etched, in a self-aligned manner, by means of a photolithography process. A thick oxide film is formed on a side wall portion of the first polycrystalline silicon layer, using the silicon nitride film as a mask, and after the silicon nitride film is removed, a conductive film is formed on the entire surface. Since a film formation process advances without patterning the first polycrystalline silicon layer, the first polycrystalline silicon layer is not damaged by an RIE process and the like. A defect density of the oxide film formed on the first polycrystalline silicon layer can be reduced. Since the thick oxide film is formed on the side wall portion of the first polycrystalline silicon layer, a withstand voltage and reliability of this portion are largely improved.
New Patents
4932028
4933860
E R R O R L O G S Y S T E M FOR SELF-TESTING IN VERY LARGE SCALE INTEGRATED CIRCUIT (VLSI) UNITS
METHOD FOR FABRICATING A RADIO FREQUENCY INTEGRATED CIRCUIT AND PRODUCT FORMED THEREBY
Haluk Katircioglu, John A De Beule, Debaditya Mukherjee, Gary C Whitlock assigned to Unisys Corporation A VSLI chip is implemented with registers which log permanent and intermittent errors occurring within the chip as sensed by concurrent error detection circuitry (CED). If a fatal error is detected (one which would destroy the reliability of chip operations), then the chip is immobilized into a hold mode (freeze). Interrupts are signalled to a cooperating maintenance controller which can pass the error information to an external computer for display and for locating a faulty area.
Louis C Liu assigned to TRW Inc A method of designing and fabricating a semiconductor integrated circuit for operation at radio frequencies. The method includes fabricating an integrated circuit having circuit components, at least one of which is an active device, testing the electrical performance of at least one of the active devices and then forming an electrical conductor to the integrated circuit to interconnect selected ones of the circuit components to form a radio frequency circuit, wherein the selection is based on the outcome of the electrical performance test.
4935378 M E T H O D FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING MORE THAN TWO CONDUCTIVE LAYERS
4933042 METHOD FOR PACKAGING INTEGRATED CIRCUIT CHIPS EMPLOYING A POLYMER FILM OVERLAY LAYER Charles W Eichelberger, Robert Wojnarowski, Kenneth Welles assigned to General Electric Company A method and apparatus are provided for disposing a polymer film on an irregularly-shaped substrate at relatively high temperatures. In particular, the method and apparatus of the present invention provide a system for the packaging of very large scale intergrated circuit chips. The system of the present invention particularly solves problems associated with high temperature processing and problems associated with the highly irregular surfaces that result. Nonetheless, the resultant product is capable of being fashioned into circuit chip systems which are independently testable and which may be reconfigured after testing by removal of the polymer film itself.
Seiichi Mori, Tokyo, Japan Kabushiki Kaisha Toshiba
assigned
to
According to a semiconductor device manufacturing method of the invention, a first polycrystalline silicon layer doped with an impurity, a thin oxide film, a second polycrystalline silicon layer, and a silicon nitride film are sequentially formed, one upon the other. The silicon nitride film, the second polycrystalline silicon layer, the thin oxide film, and the first polycrystalline silicon layer are then etched, in a self-aligned manner, by means of a photolithography process. A thick oxide film is formed on a side wall portion of the first polycrystalline silicon layer, using the silicon nitride film as a mask, and after the silicon nitride film is removed, a conductive film is formed on the entire surface. Since a film formation process advances without patterning the first polycrystalline silicon layer, the first polycrystalline silicon layer is not damaged by an RIE process and the like. A defect density of the oxide film formed on the first polycrystalline silicon layer can be reduced. Since the thick oxide film is formed on the side wall portion of the first polycrystalline silicon layer, a withstand voltage and reliability of this portion are largely improved.