A 130K-gate CMOS mainframe chip set

Microprocessors A 130K-gate CMOS mainframe chip set K IKEDA, A Y A M A G I W A , K IKUZAKI, M FUJITA, A MASAKI, M ASANO (Hitachi Kanagawa Works, Japan) 1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition, New York, USA, 25-27 Feb. 1987 (Coral Gables, FL, USA: Lewis Winner Feb. 1987), pp. 86-87,350 A mainframe chip set with 130K gates on 3 chips was fabricated using a 1.3 pm double-Al-layer CMOS process. The chip set was designed as a mainframe processor. While most of the standard cell-type chips are composed mainly of static-logic poly-cell blocks, a few macrocell blocks have been used as arithmetic logic unit (ALU) and RAMs. The ALU is a dynamic logic block, as its speed is a determining factor in processor performance. The chips have a WSi2/poly-Si-layer and double-Allayers. Their die sizes are 12.9 m m 2, and they are packaged on a 240-pin (192 signal pin) pin grid array. A processor chip set on a 60K master image chip H SCHETTLER, G KOETZLE (IBM Labs., Boeblingen, Germany) 1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition, New York, USA, 25-27 Feb. 1987 (Coral Gables, FL, USA: Lewis Winner Feb. 1987), pp. 88-89, 351-352 A master image is an array of cell locations without gates or transistors. It offers some of the advantages of semicustom gate arrays and custom macro design. However, production time is longer than that of gate arrays. A flexible master image with respect to logic, RAM, ROM, and other macros is discussed. Macros of any size can be placed at any location on the chip. During the personalisation, the logic elements and the larger macros are placed by an automatic design system. A single logic element may take the area of one or more cells. Only array macros, like RANIs, are custom-designed for optimisation. The technology used for the master image is a 1.0 lum CMOS N-well structure with three layers of metal. Two layers are used for wiring and the third layer contains the power distribution and the I/O redistribution for the central area pad arrangement. The master image itself consists of a virtual grid for circuit placement, the power distribution through all three layers of metal, and the driver/receiver area at the chip perimeter. The placement strategy on the virtual grid allows circuit depopulation of certain areas in order to gain routing channels for global wiring. (3 refs.) The super Z80 microprocessor- the tlitachi liD 64180

C BITARD

Micro. Syst. (France) no. 75, pp. 125-126 (May 1987). In French This 8 bit microprocessor in its 64 pin DIP looks like a ZS0 to which have been added such facilities as MMU, DMA and UART, together with supplementary instructions. A clock generator and a dynamic memory refresh circuit are also integrated into the package. Various other features are discussed. G.P.

A modular design and test approach for a family of VLSI MPUs D BRAUNE, A GUER1N, J LABROUSSE (Int. Microelectron. Support Center, Fontcnay Aux Roses, France) 1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition, New York, USA, 25-27 Feb. 1987 (Coral Gables, FL, USA: Lewis Winner Feb. 1987), pp. 90-91,353 A modular design approach was applied, and different design tools merged into a controllable design system, to create and test a complex but flexible VLSI IC. It is the first dement of a highly integrated MPU family combining traditional design methods for reusable core functions, independent test program generation, automated design methods and a flexible on-chip bus protocol for easy peripheral function replacement. The complete circuit contains a CPU whose instruction set is fully compatible with available microprocessors, a memory management unit a two-channel IDNIA controller, a bus interface and three timer functions. llarvard architecture pushes microcontroller IC into high-speed realm G G O O D t t U E , J JENKINS, A KHAN Electron. Components & Appl. (Netherlands) vol. 8, no. 1, pp. 32-38 With its three parallel buses, ECL-based circuitry and 100 ns instruction cycle, the new 8X401A microcontrollet has no trouble filling the most demanding roles in, for example, signal processing and communication, and peripheral control. Besides the 8X401's high speed, other advantages over its predecessors are its ability to handle both interrupts and subroutines in their entirety, its four new instructions for jumps and returns and its extra arithmetic and logic operations. The architecture of a capability-based microprocessor

system P CORSINI (Pisa Univ., Italy), L LOPRIORE 1EEEAficro. (USA) vol. 7, no. 3, pp. 35-51 (June 1987) The results of research aimed at the definition and implementation of a microprocessor-based advanced architecture whose main goal is the reduction of the semantic gap are presented. Tiffs architecture is oriented towards high-level languages supporting modular decomposition of programs, user-defined data abstraction, and concurrency. Its salient features are a capabilityoriented addressing scheme, an approach to memory management based on the concept of a single-level store, implementation of tagged storage by the tagging of memory segments, and significant hardware support for multi-tasking. Particular attention is paid to object types and memory management, and the architecture is evaluated according to how well it reduces the semantic gap. It is also shown how it has been implemented as a research prototype in which the central processing units has been built around an off-the-shelf microprocessor and in which an intelligent memory device autonomously supports the memory management functions. (15 refs.)

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