- Email: [email protected]
A 1 V, 69–73 GHz CMOS power amplifier based on improved Wilkinson power combiner
Microelectronics Journal 43 (2012) 370–376
Contents lists available at SciVerse ScienceDirect
Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
A 1 V, 69–73 GHz CMOS power amplifier based on improved Wilkinson power combiner Haikun Jia n, Baoyong Chi, Lixue Kuang, Zhihua Wang Institute of Microelectronics, Tsinghua University, Beijing 100084, China
a r t i c l e i n f o
a b s t r a c t
Article history: Received 9 August 2011 Received in revised form 17 February 2012 Accepted 27 February 2012 Available online 20 March 2012
A 1 V, 69–73 GHz CMOS power amplifier based on improved Wilkinson power combiner is presented. Compared with the traditional one, the proposed Wilkinson power combiner could lower down the insertion loss and reduce the die area by eliminating the quarter-wavelength transmission lines while preserving the characteristics of Wilkinson power combining and good port isolation. The presented power amplifier has been implemented in 65 nm CMOS process and achieves a measured saturated output power of 10.61 dBm and a peak power added efficiency of 8.13% at 73 GHz with only 1 V power supply. The die area including pads is 1.23 0.45 mm2, while the power combiner only occupies 200 80 mm2. & 2012 Elsevier Ltd. All rights reserved.
Keywords: Millimeter wave Power amplifier Power combining CMOS
1. Introduction Along with the rapid development of the CMOS process, CMOS millimeter-wave circuits have received a lot of attentions for potential applications in communication, radar and image systems. Although many improved mm-wave front-ends and transceivers have been developed [1–3,7], the power amplifier in CMOS still remains a bottleneck for the millimeter-wave systems. Since the output voltage swing is limited by a low breakdown voltage of scaled MOS transistors and the high loss silicon substrate worsens the quality of on-chip passive components, it is difficult for the mm-wave power amplifier (PA) to achieve high output power. The power combining technique is widely used to improve the output power of the PA. PAs with power combining techniques, based on the transformer or the Wilkinson power combiner, have been reported [4–8]. The Wilkinson power combiner could theoretically achieve lossless power combining when working with a matched load. The input and output ports of the Wilkinson combiner are well isolated, which could reduce the interference between two sub-amplifier paths when there exists some mismatching. The Wilkinson combiner is mainly formed by the transmission lines in which the electromagnetic field is well confined compared to the transformer. It can simplify the layout design since the coupling between passive components can be well controlled.
n
Corresponding author. Tel.: þ86 10 6279 4545. E-mail address: [email protected] (H. Jia).
0026-2692/$ - see front matter & 2012 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2012.02.003
The main disadvantage of the Wilkinson combiner is the large area as the segments of the transmission lines are quarterwavelength long. As a result, the die area consumed by the Wilkinson combiner would be large even if it operates in millimeter-wave frequency bands. The quarter-wavelength transmission line would also decrease the power combining efficiency noticeably, due to the loss of long on-chip transmission lines. Many efforts have been made to reduce the size of the Wilkinson combiner (divider) using lumped elements. The Wilkinson divider reported in [9] consists of a parallel LC-ladder and a series RL circuit. There are still two inductors and two capacitors required in this divider. In [10] active inductors are employed to further reduce the size. The bandwidth of this divider is relatively narrow. In this paper, an improved Wilkinson power combiner is proposed. The quarter-wavelength transmission lines are eliminated while the characteristics of the theoretical lossless power combining and good port isolation are preserved. Thus, the die area consumed by the power combiner can be further reduced and the loss due to transmission lines is lowered down. A 69–73 GHz PA based on the proposed Wilkinson power combiner has been implemented in 65 nm CMOS process and the measured results verify the feasibility of the proposed Wilkinson power combiner.
2. Proposed Wilkinson power combiner Figs. 1 and 2 show the structures of a traditional Wilkinson power combiner and the proposed Wilkinson power combiner.
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Fig. 1. Structure of the traditional Wilkinson power combiner.
Fig. 3. Proposed Wilkinson power combiner in symmetrical form.
Fig. 2. Structure of the proposed Wilkinson power combiner.
It canpbe ffiffiffiffiffiffiffiffiseen that the quarter-wavelength transmission lines with 2Z 0 characteristic impedance are replaced by transmission lines with Z0 characteristic impedance. An extra capacitor C is added between two input ports to assure the good port isolation. The impedance seen from the left of the dashed line in Fig. 2 is matched to Z0/2. A resistor of 2Z0 is placed between the two input ports in both traditional and proposed Wilkinson power combiners. The proposed Wilkinson power combiner can be analyzed in odd and even modes. It can be redrawn in a symmetrical form as shown in Fig. 3. The matched Z0/2 load impedance seen in Fig. 2 is split into two resistors of Z0 in parallel. In the even mode, no current flows through the resistor and the capacitor between the two input ports, so they can be shorted virtually. The half circuit in the even mode is shown in Fig. 4(a). It is obvious that the input and output ports in the even mode are matched. In the odd mode, the voltage on the symmetry axis is always a zero. So it can be connected to the ground virtually. The half circuit in the odd mode is shown in Fig. 4(b), which consists of a capacitor of 2C, a resistor of Z0 and a transmission line. The input impedance of the odd mode half circuit seen from port is expressed as follows: Z in ¼ Z 0 ==
1 2jo0 C
==ðjZ 0 tan b‘Þ
ð1Þ
in which o0 is the operation frequency, and l is the length of the transmission line. When the capacitor resonates with the transmission line, or 1 ¼ Z 0 tan b‘, 2o0 C
ð2Þ
the input impedance is equal to the port impedance Z0. In this design the capacitance is chosen to be 140 fF and the transmission line is chosen to be 49 mm for layout design consideration. The S-parameter matrix of the proposed Wilkinson power combiner can be expressed as follows according to the above analysis. 2 3 jb‘ jb‘ ep ep ffiffi ffiffi 0 2 2 6 jb‘ 7 6 epffiffi 7 2Z 0 o0 C tan b‘1 2Z 0 o0 C tan b‘1 1 1 7 S¼6 ð3Þ 2 2 o C tan b ‘ þ 2j tan b ‘ o C tan b ‘ þ 2j tan b ‘ 12Z 12Z 0 0 0 0 6 2 7 4 ejb‘ 5 2Z 0 o0 C tan b‘1 2Z 0 o0 C tan b‘1 1 1 pffiffi 2 12Z o0 C tan b‘ þ 2j tan b‘ 2 12Z o0 C tan b‘ þ 2j tan b‘ 2 0
0
Fig. 4. Half-circuit of the proposed Wilkinson power combiner in (a) even mode and (b) odd mode.
When the relationship based on the Eq. (2) is held, the S-parameter matrix can be simplified as follows: 2
0
6 jb‘ 6e S ¼ 6 pffiffi2 4 jb‘ epffiffi 2
jb‘ ep ffiffi 2
0 0
jb‘ ep ffiffi 2
3
7 0 7 7 5 0
ð4Þ
An extra matching network is needed to transform 50 O load impedance into 25 O. Taking the pad parasitic capacitance into account, only a 180 mm transmission line in series is needed to complete the impedance transformation. Even taking the extra matching network into account, the total area consumed is much less than the traditional Wilkinson combiner. The total length of the transmission line needed in the proposed combiner is about 280 mm while it should be about 954 mm (half of the on-chip wavelength at 73 GHz) in the traditional Wilkinson combiner. Fig. 5 shows the simulation results of the proposed Wilkinson power combiner. The return loss of each port is below 18 dB in the operation frequency band. The isolation between the two input ports is better than 30 dB. Fig. 6 shows the simulated combining loss of the traditional Wilkinson power combiner with ideal and practical transmission lines (TLs) and the proposed Wilkinson power combiner including a matching network with practical transmission lines. It can be seen that the combining loss of the proposed Wilkinson power combiner is lower than that of the traditional Wilkinson power combiner by 0.2 dB.
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Fig. 5. Simulated return loss and port isolation of the proposed Wilkinson power combiner.
Fig. 6. Simulated combining loss of the traditional and the proposed Wilkinson power combiner.
3. Power amplifier design
Fig. 7. Block diagram of the proposed PA.
The proposed PA consists of a pre-drive stage, two 2-stage cascade sub-PAs and the proposed Wilkinson PA. Fig. 7 shows the block diagram of the proposed PA. The pre-drive stage is used to deliver the power to two 2-stage cascade sub-amplifiers. The input impedance of the pre-drive stage is matched to 50 O. On-chip microstrip lines are employed in the matching network.
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Fig. 8. Schematic of the first pre-drive stage.
Fig. 9. Schematic of 2-stage cascade sub-PA.
The parasitic capacitance of the input G–S–G pad is taken into account when designing the matching network, which is about 38 fF by EM simulation. As shown in Fig. 8, top metal with 3.4 mm thickness is used as the signal trace of the microstrip. Since the thickness of M1 in 65 nm CMOS is 0.18 mm while copper’s skin depth is about 0.25 mm at 77 GHz, M1 and M2 are shunted together to form the ground plane [11]. It can reduce the penetration of the electromagnetic field into the substrate. The simulated insertion loss of the microstrip lines is 0.76 dB/mm. Custom modeled MOM capacitors are used as AC coupling and DC decoupling capacitors. All the passive components are designed and verified using a commercial full wave electromagnetic simulation tool HFSS. The schematic of the 2-stage cascade sub-amplifier is shown in Fig. 9. A common-source single transistor topology is chosen rather than the cascode topology. The cascode topology improves the device’s stability but reduces the voltage headroom, thus limiting the output voltage swing. Since the supply voltage is 1.0 V in our design, the cascode topology would reduce the output
Fig. 10. Simulated contours of constant 1 dB compressed output power for 24 2 mm2 NMOS transistor. The NMOS is biased at around 0.3 mA/mm for optimal fT.
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power of the amplifier significantly. The last stage of the amplifier is optimized for the highest output power. A load-pull simulation is performed to obtain the optimized load impedance seen from the drain of output transistors. Fig. 10 shows the contours of constant power delivered to the output load regarding to the load impedance. As demonstrated in Fig. 10, the optimal load impedance should be 25.5þj22.6 O (point A in Fig. 10). Matching network formed by the microstrip lines is used to transform 50 O load impedance to the optimized impedance needed at the drain of the output transistors. The parasitic capacitance due to the output G–S–G pad of 38 fF is included in the output matching network. The sizes of the output transistors in the sub-amplifier are chosen to be 24 2 mm2 60 nm. The figure width of the transistors is chosen to be 2 mm for maximum stable gain (MSG), and the transistors are biased at around 0.3 mA/mm for optimal fT [12]. A transistor of 32 2 mm2 60 nm is used to drive the output transistors. It is over-sized to guarantee that the saturated output power of the PA would not be affected by this transistor. This would adversely affect the power added efficiency of the PA. To further enhance the output power of the power amplifier, the matching network between the first and the last stages of the
sub-amplifier is simplified. As shown in Fig. 9, the input impedance of the last stage transistor and the output impedance of the first stage transistor are conjugate-matched directly using three segment microstrip lines, rather than matching to 50 O [13]. Thus the number of the required microstrip lines is reduced.
4. Measurement results The PA based on the proposed Wilkinson power combiner has been implemented in 65 nm CMOS. Fig. 11 shows the microphotograph of the chip. The die area is 1.23 0.45 mm2, including the pads. The proposed combiner only occupies the area of 200 80 mm2. The measurements were performed at up to 75 GHz using a G–S–G probe station, a millimeter-wave power meter and a network analyzer. The equipment is calibrated by Impedance Standard Substrate (ISS) using a short-open-load-through (SOLT) method. The simulated and measured S-parameters of the presented PA are shown in Fig. 12. The simulated results are calibrated using the measured results of the on-chip passive components. The measured small signal gain (S21) is 19.7 dB at 73 GHz with a peak of 24.0 dB at 70.5 GHz. The measured 3 dB bandwidth is 4.2 GHz from 68.1 GHz
Fig. 11. Microphotograph of the presented PA.
Fig. 12. Simulated and measured S-parameter of the presented PA.
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Fig. 13. Measured large-signal performance of the PA at 73 GHz.
Table 1 Performance summary and comparisons. Technology
65 nm CMOS (this work)
90 nm CMOS [13]
65 nm CMOS [7]
65 nm CMOS [14]
65 nm CMOS [15]
Working frequency (GHz) Voltage supply (V)
69–73 1.0
65.7–83.2 1.2
53–68 1.2
57–65 1.0
Gain (dB) Psat (dBm) Peak PAE (%) Output referred P1 dB (dBm)
24.0 10.6 8.13 6.79
8.5 6.3 N/A 4.7
14.3 16.6 4.9 11
15.8 11.5 11 2.5
101–117 VDD1 ¼1.4 VDD2 ¼1 12.2 12.9 8.2 9.6
to 72.3 GHz, which is enough for typical applications such as automotive radar. Since the purpose of this work is to verify the feasibility of the proposed combiner, precise working frequency is not a critical issue. The frequency is simply determined according to the electromagnetic simulation results. The input return loss (S11) is less than 10 dB from 69.9 GHz to 71.1 GHz. It can be seen that obvious jitter exists in the measured S11 from 65 GHz to 68 GHz from the measured result. One possible reason may be that the connection between probe and PAD on chip is not stable. The measured output return loss (S22) is 11.3 dB at 73 GHz and less than 5 dB from 69 to 73 GHz. The measured large signal performance can be seen from Fig. 13. The connection loss between the chip and the equipment has been calibrated to obtain the intrinsic performance. The whole chip draws DC current of 110 mA at the supply voltage of 1 V. The saturated output power of the PA is 10.61 dBm at 73 GHz. The peak power added efficiency (PAE) is 8.13%. It is relatively low partly due to the over-sized transistors. The output referred 1 dB compression point (P1 dB) is 6.79 dBm. Table 1 summarizes the performance of the presented PA. 5. Conclusion In this paper, an improved Wilkinson power combiner is proposed. The quarter-wavelength transmission lines are eliminated
while the characteristics of the theoretical lossless power combining and good port isolation are preserved. Thus, the die area consumed by the power combiner is reduced and the loss due to the transmission lines is lowered down. A 69–73 GHz PA based on the proposed Wilkinson power combiner has been implemented in 65 nm CMOS process. The total chip size is 1.23 0.45 mm2 while the combiner occupies 200 80 mm2.The measured power gain, output P1 dB, Psat and peak PAE at 73 GHz are 19.7 dB, 6.79 dBm, 10.61 dBm and 8.13%, respectively while the power supply is only 1.0 V.
Acknowledgments This work was supported by the National Natural Science Foundation of China under Grant no. 61076029, and the authors acknowledge chip fabrication donation by TSMC. References [1] C. Marcu, D. Chowdhury, C. Thakkar, J.D. Park, L.K. Kong, M. Tabesh, Y.J. Wang, B. Afshar, A. Gupta, A. Arbabian, S. Gambini, R. Zamani, E. Alon, A.M. Niknejad, 90 nm CMOS low power 60 GHz transceiver with integrated baseband circuitry, IEEE J. Solid-State Circuits 44 (12) (2009) 3434–3447. [2] T. Mitomo, N. Ono, H. Hoshino, Y. Yoshihara, O. Watanabe, I. Seto, 77 GHz 90 nm CMOS transceiver for FMCW radar applications, VLSI Dig. Tech. Pap. (2009) 246–247.
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[3] Yikun Yu, Peter G.M. Baltus, Anton de Graauw, Edwin van der Heijden, Cicero S. Vaucher, Arhur H.M. van Roermund, 60 GHz phase shifter integrated with LNA and PA in 65 nm CMOS for phased array systems, IEEE J. Solid-State Circuits 45 (9) (2010). [4] U.R. Pfeiffer, D. Gordon, A 23 dBm 60 GHz distributed active transformer in a silicon process technology, IEEE Trans. Microwave Theory Techn. 55 (2007) 857–865. [5] J.-W. Lai, Alberto Valdes-Garcia, A 1 V 17.9 dBm 60 GHz power amplifier in standard 65 nm CMOS, ISSCC Dig. Tech. Pap. (2010) 424–426. [6] Chi Y Law, Anh-Vu Pham, A high-gain 60 GHz power amplifier with 20 dBm output power in 90 nm CMOS, ISSCC Dig. Tech. Pap. (2010) 427–429. [7] B. Martineau, V. Knopik, A. Siligaris, A 53–68 GHz 18 dBm power amplifier with an 8-way combiner in standard 65 nm CMOS, ISSCC Dig. Tech. Pap. (2010) 430–432. [8] Y. Yoshihar, R. Fujimoto, N. Ono, T. Mitomo, H. Hoshino, M. Hamada, A 60 GHz CMOS power amplifier with Marchand Balun-based parallel power combiner, ASSCC Dig. Tech. Pap. (2008) 121–124. [9] Tadashi Kawai, Hiroyuki Mizuno, Isao Ohta, Akira Enokihara, Lumpedelement quadrature Wilkinson power divider, in: Proceedings of the Microwave Conference (APMC), Asia-Pacific, 2009.
[10] Liang-Hung Lu, Yu-Te Liao, Chung-Ru Wu, A miniaturized Wilkinson power divider with CMOS active inductors, IEEE Microwave Wireless Components Lett. 15 (11) (2005) 775–777. [11] L. Lee, Y.A. Li, M.H. Hung, S.J. Huang, A fully-integrated 77 GHz FMCW radar transceiver in 65 nm CMOS technology, IEEE J. Solid-State Circuits 45 (12) (2010) 2746–2756. [12] Debopriyo Chowdhury, Patrick Reynaert, Ali M. Niknejad, Design considerations for 60 GHz transformer-coupled CMOS power amplifiers, IEEE J. SolidState Circuits 44 (10) (2009) 2733–2744. [13] Toshihide Suzuki, Yoichi Kawano, Masaru Sato, Tatsuya Hirose, Kazukiyo Joshin, 60 and 77 GHz power amplifiers in standard 90 nm CMOS, ISSCC Dig. Tech. Pap. (2008) 561–563. [14] Wei L. Chan, John R. Long, Marco Spirito, John J. Pekarik, A 60 GHz-band 1 V 11.5 dBm power amplifier with 11% PAE in 65 nm CMOS, ISSCC Dig. Tech. Pap. (2009) 380–381. [15] Zhiwei Xu, Qun Jane Gu, Mau-Chung Frank Chang, A W-band current combined power amplifier with 14.8 dBm Psat and 9.4% maximum PAE in 65 nm CMOS, in: Proceedings of the IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2011.
Contents lists available at SciVerse ScienceDirect
Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
A 1 V, 69–73 GHz CMOS power amplifier based on improved Wilkinson power combiner Haikun Jia n, Baoyong Chi, Lixue Kuang, Zhihua Wang Institute of Microelectronics, Tsinghua University, Beijing 100084, China
a r t i c l e i n f o
a b s t r a c t
Article history: Received 9 August 2011 Received in revised form 17 February 2012 Accepted 27 February 2012 Available online 20 March 2012
A 1 V, 69–73 GHz CMOS power amplifier based on improved Wilkinson power combiner is presented. Compared with the traditional one, the proposed Wilkinson power combiner could lower down the insertion loss and reduce the die area by eliminating the quarter-wavelength transmission lines while preserving the characteristics of Wilkinson power combining and good port isolation. The presented power amplifier has been implemented in 65 nm CMOS process and achieves a measured saturated output power of 10.61 dBm and a peak power added efficiency of 8.13% at 73 GHz with only 1 V power supply. The die area including pads is 1.23 0.45 mm2, while the power combiner only occupies 200 80 mm2. & 2012 Elsevier Ltd. All rights reserved.
Keywords: Millimeter wave Power amplifier Power combining CMOS
1. Introduction Along with the rapid development of the CMOS process, CMOS millimeter-wave circuits have received a lot of attentions for potential applications in communication, radar and image systems. Although many improved mm-wave front-ends and transceivers have been developed [1–3,7], the power amplifier in CMOS still remains a bottleneck for the millimeter-wave systems. Since the output voltage swing is limited by a low breakdown voltage of scaled MOS transistors and the high loss silicon substrate worsens the quality of on-chip passive components, it is difficult for the mm-wave power amplifier (PA) to achieve high output power. The power combining technique is widely used to improve the output power of the PA. PAs with power combining techniques, based on the transformer or the Wilkinson power combiner, have been reported [4–8]. The Wilkinson power combiner could theoretically achieve lossless power combining when working with a matched load. The input and output ports of the Wilkinson combiner are well isolated, which could reduce the interference between two sub-amplifier paths when there exists some mismatching. The Wilkinson combiner is mainly formed by the transmission lines in which the electromagnetic field is well confined compared to the transformer. It can simplify the layout design since the coupling between passive components can be well controlled.
n
Corresponding author. Tel.: þ86 10 6279 4545. E-mail address: [email protected] (H. Jia).
0026-2692/$ - see front matter & 2012 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2012.02.003
The main disadvantage of the Wilkinson combiner is the large area as the segments of the transmission lines are quarterwavelength long. As a result, the die area consumed by the Wilkinson combiner would be large even if it operates in millimeter-wave frequency bands. The quarter-wavelength transmission line would also decrease the power combining efficiency noticeably, due to the loss of long on-chip transmission lines. Many efforts have been made to reduce the size of the Wilkinson combiner (divider) using lumped elements. The Wilkinson divider reported in [9] consists of a parallel LC-ladder and a series RL circuit. There are still two inductors and two capacitors required in this divider. In [10] active inductors are employed to further reduce the size. The bandwidth of this divider is relatively narrow. In this paper, an improved Wilkinson power combiner is proposed. The quarter-wavelength transmission lines are eliminated while the characteristics of the theoretical lossless power combining and good port isolation are preserved. Thus, the die area consumed by the power combiner can be further reduced and the loss due to transmission lines is lowered down. A 69–73 GHz PA based on the proposed Wilkinson power combiner has been implemented in 65 nm CMOS process and the measured results verify the feasibility of the proposed Wilkinson power combiner.
2. Proposed Wilkinson power combiner Figs. 1 and 2 show the structures of a traditional Wilkinson power combiner and the proposed Wilkinson power combiner.
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Fig. 1. Structure of the traditional Wilkinson power combiner.
Fig. 3. Proposed Wilkinson power combiner in symmetrical form.
Fig. 2. Structure of the proposed Wilkinson power combiner.
It canpbe ffiffiffiffiffiffiffiffiseen that the quarter-wavelength transmission lines with 2Z 0 characteristic impedance are replaced by transmission lines with Z0 characteristic impedance. An extra capacitor C is added between two input ports to assure the good port isolation. The impedance seen from the left of the dashed line in Fig. 2 is matched to Z0/2. A resistor of 2Z0 is placed between the two input ports in both traditional and proposed Wilkinson power combiners. The proposed Wilkinson power combiner can be analyzed in odd and even modes. It can be redrawn in a symmetrical form as shown in Fig. 3. The matched Z0/2 load impedance seen in Fig. 2 is split into two resistors of Z0 in parallel. In the even mode, no current flows through the resistor and the capacitor between the two input ports, so they can be shorted virtually. The half circuit in the even mode is shown in Fig. 4(a). It is obvious that the input and output ports in the even mode are matched. In the odd mode, the voltage on the symmetry axis is always a zero. So it can be connected to the ground virtually. The half circuit in the odd mode is shown in Fig. 4(b), which consists of a capacitor of 2C, a resistor of Z0 and a transmission line. The input impedance of the odd mode half circuit seen from port is expressed as follows: Z in ¼ Z 0 ==
1 2jo0 C
==ðjZ 0 tan b‘Þ
ð1Þ
in which o0 is the operation frequency, and l is the length of the transmission line. When the capacitor resonates with the transmission line, or 1 ¼ Z 0 tan b‘, 2o0 C
ð2Þ
the input impedance is equal to the port impedance Z0. In this design the capacitance is chosen to be 140 fF and the transmission line is chosen to be 49 mm for layout design consideration. The S-parameter matrix of the proposed Wilkinson power combiner can be expressed as follows according to the above analysis. 2 3 jb‘ jb‘ ep ep ffiffi ffiffi 0 2 2 6 jb‘ 7 6 epffiffi 7 2Z 0 o0 C tan b‘1 2Z 0 o0 C tan b‘1 1 1 7 S¼6 ð3Þ 2 2 o C tan b ‘ þ 2j tan b ‘ o C tan b ‘ þ 2j tan b ‘ 12Z 12Z 0 0 0 0 6 2 7 4 ejb‘ 5 2Z 0 o0 C tan b‘1 2Z 0 o0 C tan b‘1 1 1 pffiffi 2 12Z o0 C tan b‘ þ 2j tan b‘ 2 12Z o0 C tan b‘ þ 2j tan b‘ 2 0
0
Fig. 4. Half-circuit of the proposed Wilkinson power combiner in (a) even mode and (b) odd mode.
When the relationship based on the Eq. (2) is held, the S-parameter matrix can be simplified as follows: 2
0
6 jb‘ 6e S ¼ 6 pffiffi2 4 jb‘ epffiffi 2
jb‘ ep ffiffi 2
0 0
jb‘ ep ffiffi 2
3
7 0 7 7 5 0
ð4Þ
An extra matching network is needed to transform 50 O load impedance into 25 O. Taking the pad parasitic capacitance into account, only a 180 mm transmission line in series is needed to complete the impedance transformation. Even taking the extra matching network into account, the total area consumed is much less than the traditional Wilkinson combiner. The total length of the transmission line needed in the proposed combiner is about 280 mm while it should be about 954 mm (half of the on-chip wavelength at 73 GHz) in the traditional Wilkinson combiner. Fig. 5 shows the simulation results of the proposed Wilkinson power combiner. The return loss of each port is below 18 dB in the operation frequency band. The isolation between the two input ports is better than 30 dB. Fig. 6 shows the simulated combining loss of the traditional Wilkinson power combiner with ideal and practical transmission lines (TLs) and the proposed Wilkinson power combiner including a matching network with practical transmission lines. It can be seen that the combining loss of the proposed Wilkinson power combiner is lower than that of the traditional Wilkinson power combiner by 0.2 dB.
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Fig. 5. Simulated return loss and port isolation of the proposed Wilkinson power combiner.
Fig. 6. Simulated combining loss of the traditional and the proposed Wilkinson power combiner.
3. Power amplifier design
Fig. 7. Block diagram of the proposed PA.
The proposed PA consists of a pre-drive stage, two 2-stage cascade sub-PAs and the proposed Wilkinson PA. Fig. 7 shows the block diagram of the proposed PA. The pre-drive stage is used to deliver the power to two 2-stage cascade sub-amplifiers. The input impedance of the pre-drive stage is matched to 50 O. On-chip microstrip lines are employed in the matching network.
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Fig. 8. Schematic of the first pre-drive stage.
Fig. 9. Schematic of 2-stage cascade sub-PA.
The parasitic capacitance of the input G–S–G pad is taken into account when designing the matching network, which is about 38 fF by EM simulation. As shown in Fig. 8, top metal with 3.4 mm thickness is used as the signal trace of the microstrip. Since the thickness of M1 in 65 nm CMOS is 0.18 mm while copper’s skin depth is about 0.25 mm at 77 GHz, M1 and M2 are shunted together to form the ground plane [11]. It can reduce the penetration of the electromagnetic field into the substrate. The simulated insertion loss of the microstrip lines is 0.76 dB/mm. Custom modeled MOM capacitors are used as AC coupling and DC decoupling capacitors. All the passive components are designed and verified using a commercial full wave electromagnetic simulation tool HFSS. The schematic of the 2-stage cascade sub-amplifier is shown in Fig. 9. A common-source single transistor topology is chosen rather than the cascode topology. The cascode topology improves the device’s stability but reduces the voltage headroom, thus limiting the output voltage swing. Since the supply voltage is 1.0 V in our design, the cascode topology would reduce the output
Fig. 10. Simulated contours of constant 1 dB compressed output power for 24 2 mm2 NMOS transistor. The NMOS is biased at around 0.3 mA/mm for optimal fT.
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power of the amplifier significantly. The last stage of the amplifier is optimized for the highest output power. A load-pull simulation is performed to obtain the optimized load impedance seen from the drain of output transistors. Fig. 10 shows the contours of constant power delivered to the output load regarding to the load impedance. As demonstrated in Fig. 10, the optimal load impedance should be 25.5þj22.6 O (point A in Fig. 10). Matching network formed by the microstrip lines is used to transform 50 O load impedance to the optimized impedance needed at the drain of the output transistors. The parasitic capacitance due to the output G–S–G pad of 38 fF is included in the output matching network. The sizes of the output transistors in the sub-amplifier are chosen to be 24 2 mm2 60 nm. The figure width of the transistors is chosen to be 2 mm for maximum stable gain (MSG), and the transistors are biased at around 0.3 mA/mm for optimal fT [12]. A transistor of 32 2 mm2 60 nm is used to drive the output transistors. It is over-sized to guarantee that the saturated output power of the PA would not be affected by this transistor. This would adversely affect the power added efficiency of the PA. To further enhance the output power of the power amplifier, the matching network between the first and the last stages of the
sub-amplifier is simplified. As shown in Fig. 9, the input impedance of the last stage transistor and the output impedance of the first stage transistor are conjugate-matched directly using three segment microstrip lines, rather than matching to 50 O [13]. Thus the number of the required microstrip lines is reduced.
4. Measurement results The PA based on the proposed Wilkinson power combiner has been implemented in 65 nm CMOS. Fig. 11 shows the microphotograph of the chip. The die area is 1.23 0.45 mm2, including the pads. The proposed combiner only occupies the area of 200 80 mm2. The measurements were performed at up to 75 GHz using a G–S–G probe station, a millimeter-wave power meter and a network analyzer. The equipment is calibrated by Impedance Standard Substrate (ISS) using a short-open-load-through (SOLT) method. The simulated and measured S-parameters of the presented PA are shown in Fig. 12. The simulated results are calibrated using the measured results of the on-chip passive components. The measured small signal gain (S21) is 19.7 dB at 73 GHz with a peak of 24.0 dB at 70.5 GHz. The measured 3 dB bandwidth is 4.2 GHz from 68.1 GHz
Fig. 11. Microphotograph of the presented PA.
Fig. 12. Simulated and measured S-parameter of the presented PA.
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Fig. 13. Measured large-signal performance of the PA at 73 GHz.
Table 1 Performance summary and comparisons. Technology
65 nm CMOS (this work)
90 nm CMOS [13]
65 nm CMOS [7]
65 nm CMOS [14]
65 nm CMOS [15]
Working frequency (GHz) Voltage supply (V)
69–73 1.0
65.7–83.2 1.2
53–68 1.2
57–65 1.0
Gain (dB) Psat (dBm) Peak PAE (%) Output referred P1 dB (dBm)
24.0 10.6 8.13 6.79
8.5 6.3 N/A 4.7
14.3 16.6 4.9 11
15.8 11.5 11 2.5
101–117 VDD1 ¼1.4 VDD2 ¼1 12.2 12.9 8.2 9.6
to 72.3 GHz, which is enough for typical applications such as automotive radar. Since the purpose of this work is to verify the feasibility of the proposed combiner, precise working frequency is not a critical issue. The frequency is simply determined according to the electromagnetic simulation results. The input return loss (S11) is less than 10 dB from 69.9 GHz to 71.1 GHz. It can be seen that obvious jitter exists in the measured S11 from 65 GHz to 68 GHz from the measured result. One possible reason may be that the connection between probe and PAD on chip is not stable. The measured output return loss (S22) is 11.3 dB at 73 GHz and less than 5 dB from 69 to 73 GHz. The measured large signal performance can be seen from Fig. 13. The connection loss between the chip and the equipment has been calibrated to obtain the intrinsic performance. The whole chip draws DC current of 110 mA at the supply voltage of 1 V. The saturated output power of the PA is 10.61 dBm at 73 GHz. The peak power added efficiency (PAE) is 8.13%. It is relatively low partly due to the over-sized transistors. The output referred 1 dB compression point (P1 dB) is 6.79 dBm. Table 1 summarizes the performance of the presented PA. 5. Conclusion In this paper, an improved Wilkinson power combiner is proposed. The quarter-wavelength transmission lines are eliminated
while the characteristics of the theoretical lossless power combining and good port isolation are preserved. Thus, the die area consumed by the power combiner is reduced and the loss due to the transmission lines is lowered down. A 69–73 GHz PA based on the proposed Wilkinson power combiner has been implemented in 65 nm CMOS process. The total chip size is 1.23 0.45 mm2 while the combiner occupies 200 80 mm2.The measured power gain, output P1 dB, Psat and peak PAE at 73 GHz are 19.7 dB, 6.79 dBm, 10.61 dBm and 8.13%, respectively while the power supply is only 1.0 V.
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