- Email: [email protected]
A 256 × 256 SRAM-XOR pixel ferroelectric liquid crystal over silicon spatial light modulator
I995
I5 September
OPTICS COMMUNICATIONS Optics
Communications
I 19 ( 1995)
623-632
Full length article
A 256 x 256 SRAM-XOR pixel ferroelectric liquid crystal over silicon spatial light modulator D.C. Burns a, I. Underwood” ’
Depurrment
of Electrical
h Deparrment
of Physics
Engineering,
The University
& Astronomy,
The University
J. Gourlay b, A. O’Hara b, D.G. Vass b ofEdinburgh, ofEdinburgh,
Kings Buildings,
Mayfield
Road, Edinburgh,
UK
Kings Buildings,
Mayfield
Road, Edinburgh,
UK
Received 17 July I995
Abstract An electronically addressed spatial light modulator is introduced. It is based on the hybrid technology of ferroelectric liquid crystal over silicon, and comprises an array of 256 x 256 pixels operating at a charge balanced frame rate of up to 2.1 kHz. The pixel circuit, incorporating a static random access memory latch and an exclusive-OR gate, has significant performance advantages over the single transistor design used elsewhere. The silicon backplane has also been used to help develop post-processing planarisation techniques for high fill-factor (84%)) optically flat electrode mirrors.
1. Introduction Many optical processing systems rely critically on the availability of high performance, electronicallyaddressed spatial light modulators (SLMs) . In recent years there has been active interest in developing the hybrid SLM technology of ferroelectric liquid crystal over silicon (FLCOS). FLCOS SLMs combine the fast switching times and low switching energies of FLCs, with the high frequency operation and versatile functionality available from large scale integrated circuit technology. These electronically-addressed SLMs function as electronically-written, opticallyread memory devices and are suitable for use in display applications and as input or filter planes in optical systems. FLCOS SLMs are produced by sandwiching a thin layer (l-2 ,um) of FLC between a custom silicon backplane and a cover glass coated on the inside with a transparent conductive electrode (see Fig. I ). Most backplane designs are based on the single-transistor 0030-4018/95/$09.50
@
1995
SSDf 0030.4018(95)00414-9
dynamic random access (DRAM) circuit [ l-41. The transistor acts as a switch to control the amount of charge stored on a capacitive storage element - usually a small metal pad that doubles as a mirror (referred to here as an electrode mirror) on the surface of the silicon. The resulting voltage on the electrode mirror generates an electric field across the FLC layer to produce binary phase or amplitude modulation in an incident wavefront. The DRAM-type circuit offers high pixel density but has several performance limitations, including photo-induced charge leakage and limited FLC drive capability. As a development of previous prototype devices [ 5,6] that were designed to modulate nematic liquid crystal, we present the SBS256, a 256 x 256 pixel FLCOS SLM that incorporates a static random access memory (SRAM) latch and an exclusive-OR (XOR) gate in each pixel. The pixel circuit overcomes the performance limitations of the DRAM-type pixel at the expense of circuit area. We also present preliminary results from our post-processing planarisation technique which
Elsevier Science B.V. All rights reserved
D. C. Burns et al. /Optics Communications I1 9 (I 995) 623-632
623
CHIP CARRIER Fig. 1. Cross-section
of a FLCOS SLM.
(4 DATA IDATA
SRAM
b
LATCH
/ENABLE
CK
(b)
DATA
, ELECTRODE
,-
MIRROR
/DATA
/LATCH
*---SRAM
Fig. 2. (a) Schematic
LATCH
diagram and (b) transistor-level
XOR
diagram of the SRAM-XOR
pixel. The slash (I) refers to the complement
of a signai
D.C. Bums et al. /Optics Communicafions 119 (I 995) 623-632
provides high quality, high fill factor electrode mirrors over the SRAM-XOR pixels.
2. Pixel design issues Fig. 2 shows both a schematic and transistor level diagram of the SRAM-XOR pixel. The data value stored in the SRAM latch and a global clock signal, CK, are the inputs to the XOR gate, whose output is connected to the second-level metal electrode mirror. The CK signal is also applied to the transparent front electrode. In this arrangement, the voltage signal on the electrode mirror is in phase or in anti-phase with the front electrode depending on whether a logic zero or logic one is stored in the latch (see Table 1). In order to prevent chemical degradation of the FLC layer, it must be charge balanced i.e. if a positive voltage pulse is applied across the FLC, it should be followed by a negative voltage pulse of equal magnitude and duration. The XOR gate permits the FLC layer to be charge balanced simply by toggling CK on a 50% duty cycle. Fig. 3 shows the signals present on a pixel during two consecutive frames. During the first frame, a logic one is stored in the pixel memory, indicating that the pixel should be ON. The overlying FLC is switched to the optical state corresponding to the ON state, by the +VDD voltage pulse, and then OFF by the -Vnn pulse; the FLC is charge balanced. During the second frame, a logic zero is stored in the latch indicating an OFF pixel; no voltage is applied across the FLC. When the FLC exhibits bistability, and with no electric field across the FLC layer, the FLC remains in the state it was last switched to - in this drive scheme it would be OFF because of the charge balancing -VDD pulse in the previous frame. In practice we have found that, due to the single-sided alignment treatment of our cell assembly techniques, one of the FLC states is favoured over the other. (The polarisation components in the viewing system can easily be adjusted to ensure that the favoured state corresponds to the OFF state.) Therefore when +bn is applied across the FLC, it flips to its ON state, but when 0 V is applied, the FLC relaxes to (or stays in) the more favoured OFF state. The SRAM-XOR pixel has significant performance advantages over the DRAM-type. For example, as data
1
LATCH
625 Fth
, ,
(F+l)
FRAME
:
FRAME
th
: :
0 .A
Fig. 3. Pixel drive scheme.
in an SRAM latch is continually reinforced by internal positive feedback, its storage capabilities are, unlike those of the DRAM-type, robust under high readbeam intensities. As a consequence, the SRAM-XOR pixel only needs to be accessed when its state is to be altered, whereas the DRAM-type must be continually refreshed from an external framestore, even when it is not being altered. DRAM-type devices are often charge balanced using a pattern/inverse pattern drive scheme [ 11. A synchronised, pulsed light source is then used to interrogate the device. The 64 x 64 SRAM-inverter pixel device by Cotter et al. [ 71 uses the inverter to drive the electrode mirror so the pattern/inverse pattern drive scheme must be used for charge-balancing. The extra degree of freedom provided by having an XOR-gate in each pixel permits the device to be charge balanced without an inverse pattern appearing, so a continuous rather than pulsed light source can be used to interrogate it. On silicon backplanes, active elements are included in the pixels to permit the array to be addressed very rapidly, ideally within one FLC switching time. In a DRAM-type device, sufficient charge must be dumped onto the pixel data storage capacitor to switch the overlying FLC. The FLC switching time is inversely proportional the FLC’s spontaneous polarisation Ps (in nC/cm*), so faster FLC materials generally have
61-h
D.C. Burns et al. /Optics
Communications
119 (1995) 623-632
Tahlc I Truth table and optical response of the FLC layer for the SRAM-XOR Inputs to XOR gate
pixel.
ELECTRODE
FRONT
LATCH
CK
MIRROR
ELECTRODE
0
0
0
0
I
I
I
0
I
0
-vDD
OFF
1
I
0
I
+VDD
ON
higher values, and thus higher effective capacitance. For FLC mixtures with PS greater than 40 nC/cm2, the charge dumped onto the capacitor with a small addressing pulse may not be enough to switch the FLC therefore the access transistor must remain on to supply charge until the FLC switches. If this is necessary, the array takes N FLC switching times to address, where N is the number of columns, so the potential frame rate is severely affected. In the SRAM-XOR pixel, the electrode mirror is always actively driven via circuit transistors by the power rails (see Fig. 2)) so there is an effectively unlimited amount of charge available to switch the FLC even when other columns of the pixel array are being addressed. The pixel design is therefore more suitable than the DRAM-type for driving faster FLC mixtures.
3. Device architecture The 256 x 256 pixel array is addressed using a column-at-a-time addressing scheme. Data enters the backplane via a 32-bit bus. The data bits are loaded into thirty-two parallel 8bit shift registers; eight clock cycles are required to assemble the 256-bit data word for a column. The data word is then latched to an auxiliary 256-bit register-buffer which drives the DATA and /DATA buslines. The register-buffer circuit helps optimise the addressing scheme as it permits the (n + 1) th data word to be assembled in the shift registers while the nth word is written to its appropriate column. As both operations are performed simultaneously, the frame scan time can be kept to a minimum. The appropriate column /ENABLE signal is selected using an 8-to-256 line column decoder.
Optical response VFLC
of FLC
0
0
OFF
1
0
OFF
4. Backplane drive scheme For medium resolution arrays such as the SBS256, the bit-plane scan time Taps, can take up a significant proportion of the frame time when the device is operating at high frame rates. For example, if the data shift register of the SBS256 is clocked at 24 MHz, Taps = 85 ps as it takes 2048 clock cycles to scan in a bit-plane. For a 2 kHz frame rate, this corresponds to about 17% of the frame time. The time elapsed between addressing the first and last columns can cause problems with charge balancing and defining when the image is valid. However, with an XOR-gate at each pixel, a drive scheme that can fully charge balance and synchronously switch the FLC layer across the whole array can be implemented. Fig. 4 shows a frame in which two pixels are switched ON, preceeded and succeeded by frames in which they are switched OFF. Although there is a delay in addressing pixel A which is in the first column, and pixel Z in the last column, CK can be switched to logic one at the end of the bitplane scanning sequence so that the optical state of all both pixels switch simultaneously. Similarly, when CK is switched to logic zero, they switch to their non reflecting state simultaneously. Note however, that receive their charge balancing pulses for different portions of the frame, with pixels in columns other than the last one scanned actually receiving part of theirs during the bit-plane scan of the next frame. The pattern on delay, Tpo, is given by, TPO
=
TBPS
+
TFLC
+
TEX
(1)
and the balance delay, TB, by, TB
=&Lc+TEx,
(2)
where, Tops is the bit-plane scan time; Tnc is the liquid crystal settling time (assuming symmetrical switch-
D.C. Burns et al. /Optics Communications 119 (1995) 623-632
I I
Nth
PATTERN ON DELAY
1 SCAN i I I "00
CK
f(
;
II
I:I II
0
If
II
"00
LATCH A
0
iBALANCE; (N+l)th I ; DELAY I SCAN I I
1
I/ /I
II
I
I I
I
II >t / II I I I
I
A VFLC FOR
621
+"DDo-
‘t
I ;
I
PIXEL Z
-"DD
v ;
Fig. 4. Charge balanced SLM drive scheme. Pixel A is in the left-most column of the pixel array and pixel Z is in the right-most column. Assume that both their latches are set to logic one in the Fth frame and logic zero in the preceding and succeeding frames. By toggling the global clock signal, CK, at appropriate times within the frame, the FLC above the pixels switch on and off simultaneously - there is no skew across the array.
ing) ; and TEX is extra time inserted to give the appropriate frame rate. Notice that a Topsterm must be included in Tpoto ensure proper charge balancing. Therefore, from Eqs. ( 1), (2), and adding TBPSfor the bit-plane scan, the frame rate fcx is given by 1 .fCK =
~(TBPS + TFLC + TEX) ’
From this, the maximum
frame rate, fcK_
(3) is given
by, 1 fCKw
=
~(TBPS + Tnc)
that is, when
’
(4)
TEX= 0.
5. Post-processing
and device assembly
The silicon backplanes are fabricated by the Austria Mikro Systeme [ 81 foundry using a 1.2 ,zrn nwell double-metal, 5.5 V, CMOS process. We have
used several of the SBS256 silicon wafers to help develop our in-house post-processing planarisation technique to significantly improve the fill factor and optical quality of the electrode mirrors. The planarisation technique is described in detail elsewhere [ 91. Briefly, planarisation involves the deposition of a thick dielectric layer (3-4 pm) over the foundry wafer which is polished flat using chemical-mechanical polishing. A further metal layer is then patterned to form opticallyflat electrode mirrors that almost completely cover the underlying pixel circuits and buslines (see Fig. 5). Our present set of photolithographic masks generate 37 x 37 pm2 mirrors over the 40 x 40 pm* pixels, thus giving us an 84% flat fill factor when the area of the via hole is taken into account. We expect to improve this figure as we refine the technique. After a wafer of silicon backplanes has been postprocessed and probe tested to identify candidate die, it is diced up, and the candidates are glued into pin grid array packages and gold bonding wires are attached. The SLM assembly procedure is performed in a clean
D. C. Bwns et al. /Optics
Cotutnunicurions
I19 (1995) 623432
Fig. 5. Photomicrographs of a group of six pixels (a) without, and (b) with post-processing flat fill factor is 7-T%, while for the planarised devices it is 84%.
planarisation.
For unplantised
devices the
D.C. Burns et al/Optics
Communications 119 (1995) 623-632
room environment. All equipment and substrates are meticulously cleaned to minimise contamination. A 12 mm x 12 mm x 1.l mm block of optically-flat, Indium Tin Oxide (ITO) coated glass is used as the cover glass with the IT0 coating providing the front electrode signal to the pixel array. A thin aluminium film is deposited onto one of the thin faces and onto the edge of the ITO-coated face. The film serves as a connection between the conducting IT0 film and front electrode bonding wire (see Fig. 1) . Asymmetric medium angle deposition SO, alignment layers are evaporated onto the cover glass. This structure gives relatively strong surface anchoring of the ELC molecules. Four spots of UV curing glue, impregnated with 2 pm spacer balls, are placed at the corners of the cover glass. The cover glass is then placed carefully atop the active area of the backplane chip, and the glue is cured with an ultra-violet lamp. The front electrode bonding wire is then glued to the aluminium film on the edge of the cover glass. The device is tilled with Merck-BDH SCE13 FLC material [lo] elevated temperature (> lO@‘C), and at low pressure ( < 10P5 TOIT). Finally, the device is slowly cooled back down to room temperature. It can be optically assessed under a polarising microscope while patterns are scanned into it from a computer controlled interface.
6. Electrical functionality
tests
Numerous testpoints and structures are included on the backplane to verify circuit functionality and also to help determine yield during probe testing. With the testpoints, we have verified that the data shift registers and enable decoder can operate at up to 24 MHz, resulting in a potential frame scan time of 85 ,ZS. Note that all of the circuits on the backplane are based on static logic designs and can therefore also be clocked arbitrarily slowly. This permits the device to be driven by very simple interface logic and controlled by a relatively low performance personal computer. The yield of the backplane is affected by defectinduced shorts and open circuits in the densely packed metal interconnect layers within the pixel array. Some of the interconnect signals, such as power rails and the global pixel clock signal, are connected directly to external circuitry and pads, and can therefore be probed
629
with a volt meter or oscilloscope to check their integrity. However, other signals such as the DATAs and /ENABLES are generated and distributed entirely onchip and so are not as readily accessible. To help test the integrity of these lines, some simple test structures are included along the edges of the pixel array. From the six wafers we have tested, each with 21 candidate die, the yield test structures have shown us that we can expect about 50% of the backplanes to have no dysfunctional DATA, /ENABLE or CK lines within the pixel array. Another 32% can be expected to function with one or more ‘dead’ lines or blocks caused by defect shorts or open-circuits. These partially functioning backplanes can be made into devices and used in applications where a full 256 x 256 pixel array is not required. The remaining 18% of backplanes have fatal shorts that draw large currents from the power supply and therefore should not be used because of the risk of damaging the driver interface circuits. The yield figures are very encouraging considering the high circuit and interconnect density within the pixel array.
7. Optical characterisation Both unplanarised and planarised backplanes have been made into SLM devices. Fig. 6 shows a test pattern on a 128 x 128 section of an unplanarised device operating in amplitude modulation mode and viewed under a polarising microscope. A close-up section of a planarised device is shown in Fig. 7: note the high flat fill factor (84%) of the pixels. The pixel contrast ratio is approximately 8:l - a typical value for SLM backplanes. To measure the FLC response times, a device is placed in a simple optical system where the output pattern is focused onto a photodiode detector. An ‘all ON’ pattern is scanned onto the SLM, and CK toggled at 1 kHz. The rise time TicRlsE = 150f5 ps, while the fall time 7-m~~~~ = 55f5 pus (see Fig. 8). Mao and Johnson [ 111 have also reported asymmetrical switching times for their neural-backplane FLCOS SLM. The asymmetry may be due to the single-sided FLC alignment layer. For our present devices, the potential frame rate of the device is limited by TmcRIsE. Assuming data is loaded onto the backplane at 24 MHz (Tars = 85 ps), and using Eq. (4). the maximum
630
D. C. Burns el al. /Optics
Communications
I1 9 (1995) 623432
Fig. 6. A test pattern on a 128 x 128 section of an unplanarised device.
frame rate is 2.1 kHz which has been verified.
8. Discussion and conclusions We have presented the SBS256, a general purpose 256 x 256 SRAM-XOR pixel FLCOS SLM, that incorporates an SRAM latch and XOR-gate in each pixel. The pixel circuit overcomes many of the performance limitations of the DRAM-type circuit used elsewhere, to provide robust data storage, and the ability to drive high spontaneous polarisation FLC mixtures. The XOR gate in each pixel permits the FLC layer to be charge balanced without the use of a pattern/inverse pattern drive scheme, so the device can be used with a continuous illumination. Also, by tog-
gling the global pixel clock signal at the appropriate times within the frame period, all the programmed ON pixels can be switched on and off simultaneously there is no addressing skew associated with the viewed image. With our present assembly techniques, the SBS256 can operate at a fully charged balanced frame rate of 2.1 kHz. With better cell assembly techniques, for example by using a thinner FLC layer, a 4 kHz frame rate should be possible. We have also demonstrated that post-processingplanarisation techniques can be used to increase the pixel fill factor from 23% to 84%. Further improvements can be expected with developments in the technique. Future SRAM-XOR backplane designs could dispense with the low fill factor mirror altogether (a min-
D. C. Burns et al. /Optics
Communications I I9 (1995) 623-632
Fig. 7. A test pattern on close-up section of a planarised
I -
ai’
I ,
o
___,_ 0
0.2
0-l
/ 0.6
i s-.-, 0.8
631
device
- 0.2
I
.I “”
I
I.?
,
I
I
I.4
1.6
18
......
7
TIME lmsl
Fig. 8. Optical response
of the WC.
Here the global FE (= CK) signal are toggled at 1 kHz.
The rise time TmRlsE = 1502~5ps, while
the fat) time &cFALL= 55f5 ps. imum size via node would still be necessary to connect the third-level metal mirror to the underlying circuitry ), thus making the SRAM-XOR type pixel more competitive in terms of area, with the DRAM-type pixel.
Acknowledgements The device fabrication was funded by the Engineering and Physical Sciences Research Council as part of the Scottish Collaborative Initiative in Optoelec-
h?Z
D.C. Burns et al. /Optics
Communications
tronic Sciences. D.C. Burns acknowledges the financial support of the Department of Education Northern Ireland. The authors gratefully thank T. Stevenson and A.D. Ruthven for their assistance in this work.
References ] I ] 1. Underwood, D.G. Vass, R.M. Sillitto, G. Bradford, N.E. Fancey, A.O. Al-Chalabi, M.J. Birch, W.A. Crossland, AI? Sparks and S.G. Lantham, in: Proc. SPIE, Vol. 1562, ed. D.M. Gookin (1991) p. 107. [ 21 M.A. Handschy, L.K. Cotter. J.D. Cunningham, T.J. Drabik and SD. Gaalema, in: Spatial Light Modulators and Applications Technical Digest, Vol. 6 (Optical Society of America, Washington, DC, 1993) p. 14. [ 31 D.J. McKnight, K.M. Johnson and R.A. Serati, Optics Lett. 18 (1993) 2159.
I I9 (199.5) 623432
[4] K.M. Johnson, D.J. McKnight and I. Underwood, J. Quantum Electron. 29 (1993) 699. [ 5 1 1.Underwood, D.G. Vass and R.M. Sill&to, IEE Proceedings, Vol. 133 (1986) p. 77. [6] D.J. M&night, D.G. Vass and R.M. Sillitto, Appl. Optics 28 (1989) 4757. [7] L.K. Cotter, T.J. Drabik, R.J. Dillon and M.A. Handschy, Optics Lett. 15 (1990) 291. [ 81 Austria Mikro Systeme International GmbH, SchoS PremsRhten, 8141 Unterpremsb%ten, Austria. [9] A. O’Hara, 1. Underwood and D.G. Vass, in: Technical Digest of the Optical Fabrication and Testing Workshop, Vol. 13 (Optical Society of America, Washington, DC, 1994) p. 86. [lo] Merck Ltd. Merck House, Poole, Dorset, England. [ 111 C.C. Mao and K.M. Johnson, Appl. Optics 32 ( 1993) 1290.
I5 September
OPTICS COMMUNICATIONS Optics
Communications
I 19 ( 1995)
623-632
Full length article
A 256 x 256 SRAM-XOR pixel ferroelectric liquid crystal over silicon spatial light modulator D.C. Burns a, I. Underwood” ’
Depurrment
of Electrical
h Deparrment
of Physics
Engineering,
The University
& Astronomy,
The University
J. Gourlay b, A. O’Hara b, D.G. Vass b ofEdinburgh, ofEdinburgh,
Kings Buildings,
Mayfield
Road, Edinburgh,
UK
Kings Buildings,
Mayfield
Road, Edinburgh,
UK
Received 17 July I995
Abstract An electronically addressed spatial light modulator is introduced. It is based on the hybrid technology of ferroelectric liquid crystal over silicon, and comprises an array of 256 x 256 pixels operating at a charge balanced frame rate of up to 2.1 kHz. The pixel circuit, incorporating a static random access memory latch and an exclusive-OR gate, has significant performance advantages over the single transistor design used elsewhere. The silicon backplane has also been used to help develop post-processing planarisation techniques for high fill-factor (84%)) optically flat electrode mirrors.
1. Introduction Many optical processing systems rely critically on the availability of high performance, electronicallyaddressed spatial light modulators (SLMs) . In recent years there has been active interest in developing the hybrid SLM technology of ferroelectric liquid crystal over silicon (FLCOS). FLCOS SLMs combine the fast switching times and low switching energies of FLCs, with the high frequency operation and versatile functionality available from large scale integrated circuit technology. These electronically-addressed SLMs function as electronically-written, opticallyread memory devices and are suitable for use in display applications and as input or filter planes in optical systems. FLCOS SLMs are produced by sandwiching a thin layer (l-2 ,um) of FLC between a custom silicon backplane and a cover glass coated on the inside with a transparent conductive electrode (see Fig. I ). Most backplane designs are based on the single-transistor 0030-4018/95/$09.50
@
1995
SSDf 0030.4018(95)00414-9
dynamic random access (DRAM) circuit [ l-41. The transistor acts as a switch to control the amount of charge stored on a capacitive storage element - usually a small metal pad that doubles as a mirror (referred to here as an electrode mirror) on the surface of the silicon. The resulting voltage on the electrode mirror generates an electric field across the FLC layer to produce binary phase or amplitude modulation in an incident wavefront. The DRAM-type circuit offers high pixel density but has several performance limitations, including photo-induced charge leakage and limited FLC drive capability. As a development of previous prototype devices [ 5,6] that were designed to modulate nematic liquid crystal, we present the SBS256, a 256 x 256 pixel FLCOS SLM that incorporates a static random access memory (SRAM) latch and an exclusive-OR (XOR) gate in each pixel. The pixel circuit overcomes the performance limitations of the DRAM-type pixel at the expense of circuit area. We also present preliminary results from our post-processing planarisation technique which
Elsevier Science B.V. All rights reserved
D. C. Burns et al. /Optics Communications I1 9 (I 995) 623-632
623
CHIP CARRIER Fig. 1. Cross-section
of a FLCOS SLM.
(4 DATA IDATA
SRAM
b
LATCH
/ENABLE
CK
(b)
DATA
, ELECTRODE
,-
MIRROR
/DATA
/LATCH
*---SRAM
Fig. 2. (a) Schematic
LATCH
diagram and (b) transistor-level
XOR
diagram of the SRAM-XOR
pixel. The slash (I) refers to the complement
of a signai
D.C. Bums et al. /Optics Communicafions 119 (I 995) 623-632
provides high quality, high fill factor electrode mirrors over the SRAM-XOR pixels.
2. Pixel design issues Fig. 2 shows both a schematic and transistor level diagram of the SRAM-XOR pixel. The data value stored in the SRAM latch and a global clock signal, CK, are the inputs to the XOR gate, whose output is connected to the second-level metal electrode mirror. The CK signal is also applied to the transparent front electrode. In this arrangement, the voltage signal on the electrode mirror is in phase or in anti-phase with the front electrode depending on whether a logic zero or logic one is stored in the latch (see Table 1). In order to prevent chemical degradation of the FLC layer, it must be charge balanced i.e. if a positive voltage pulse is applied across the FLC, it should be followed by a negative voltage pulse of equal magnitude and duration. The XOR gate permits the FLC layer to be charge balanced simply by toggling CK on a 50% duty cycle. Fig. 3 shows the signals present on a pixel during two consecutive frames. During the first frame, a logic one is stored in the pixel memory, indicating that the pixel should be ON. The overlying FLC is switched to the optical state corresponding to the ON state, by the +VDD voltage pulse, and then OFF by the -Vnn pulse; the FLC is charge balanced. During the second frame, a logic zero is stored in the latch indicating an OFF pixel; no voltage is applied across the FLC. When the FLC exhibits bistability, and with no electric field across the FLC layer, the FLC remains in the state it was last switched to - in this drive scheme it would be OFF because of the charge balancing -VDD pulse in the previous frame. In practice we have found that, due to the single-sided alignment treatment of our cell assembly techniques, one of the FLC states is favoured over the other. (The polarisation components in the viewing system can easily be adjusted to ensure that the favoured state corresponds to the OFF state.) Therefore when +bn is applied across the FLC, it flips to its ON state, but when 0 V is applied, the FLC relaxes to (or stays in) the more favoured OFF state. The SRAM-XOR pixel has significant performance advantages over the DRAM-type. For example, as data
1
LATCH
625 Fth
, ,
(F+l)
FRAME
:
FRAME
th
: :
0 .A
Fig. 3. Pixel drive scheme.
in an SRAM latch is continually reinforced by internal positive feedback, its storage capabilities are, unlike those of the DRAM-type, robust under high readbeam intensities. As a consequence, the SRAM-XOR pixel only needs to be accessed when its state is to be altered, whereas the DRAM-type must be continually refreshed from an external framestore, even when it is not being altered. DRAM-type devices are often charge balanced using a pattern/inverse pattern drive scheme [ 11. A synchronised, pulsed light source is then used to interrogate the device. The 64 x 64 SRAM-inverter pixel device by Cotter et al. [ 71 uses the inverter to drive the electrode mirror so the pattern/inverse pattern drive scheme must be used for charge-balancing. The extra degree of freedom provided by having an XOR-gate in each pixel permits the device to be charge balanced without an inverse pattern appearing, so a continuous rather than pulsed light source can be used to interrogate it. On silicon backplanes, active elements are included in the pixels to permit the array to be addressed very rapidly, ideally within one FLC switching time. In a DRAM-type device, sufficient charge must be dumped onto the pixel data storage capacitor to switch the overlying FLC. The FLC switching time is inversely proportional the FLC’s spontaneous polarisation Ps (in nC/cm*), so faster FLC materials generally have
61-h
D.C. Burns et al. /Optics
Communications
119 (1995) 623-632
Tahlc I Truth table and optical response of the FLC layer for the SRAM-XOR Inputs to XOR gate
pixel.
ELECTRODE
FRONT
LATCH
CK
MIRROR
ELECTRODE
0
0
0
0
I
I
I
0
I
0
-vDD
OFF
1
I
0
I
+VDD
ON
higher values, and thus higher effective capacitance. For FLC mixtures with PS greater than 40 nC/cm2, the charge dumped onto the capacitor with a small addressing pulse may not be enough to switch the FLC therefore the access transistor must remain on to supply charge until the FLC switches. If this is necessary, the array takes N FLC switching times to address, where N is the number of columns, so the potential frame rate is severely affected. In the SRAM-XOR pixel, the electrode mirror is always actively driven via circuit transistors by the power rails (see Fig. 2)) so there is an effectively unlimited amount of charge available to switch the FLC even when other columns of the pixel array are being addressed. The pixel design is therefore more suitable than the DRAM-type for driving faster FLC mixtures.
3. Device architecture The 256 x 256 pixel array is addressed using a column-at-a-time addressing scheme. Data enters the backplane via a 32-bit bus. The data bits are loaded into thirty-two parallel 8bit shift registers; eight clock cycles are required to assemble the 256-bit data word for a column. The data word is then latched to an auxiliary 256-bit register-buffer which drives the DATA and /DATA buslines. The register-buffer circuit helps optimise the addressing scheme as it permits the (n + 1) th data word to be assembled in the shift registers while the nth word is written to its appropriate column. As both operations are performed simultaneously, the frame scan time can be kept to a minimum. The appropriate column /ENABLE signal is selected using an 8-to-256 line column decoder.
Optical response VFLC
of FLC
0
0
OFF
1
0
OFF
4. Backplane drive scheme For medium resolution arrays such as the SBS256, the bit-plane scan time Taps, can take up a significant proportion of the frame time when the device is operating at high frame rates. For example, if the data shift register of the SBS256 is clocked at 24 MHz, Taps = 85 ps as it takes 2048 clock cycles to scan in a bit-plane. For a 2 kHz frame rate, this corresponds to about 17% of the frame time. The time elapsed between addressing the first and last columns can cause problems with charge balancing and defining when the image is valid. However, with an XOR-gate at each pixel, a drive scheme that can fully charge balance and synchronously switch the FLC layer across the whole array can be implemented. Fig. 4 shows a frame in which two pixels are switched ON, preceeded and succeeded by frames in which they are switched OFF. Although there is a delay in addressing pixel A which is in the first column, and pixel Z in the last column, CK can be switched to logic one at the end of the bitplane scanning sequence so that the optical state of all both pixels switch simultaneously. Similarly, when CK is switched to logic zero, they switch to their non reflecting state simultaneously. Note however, that receive their charge balancing pulses for different portions of the frame, with pixels in columns other than the last one scanned actually receiving part of theirs during the bit-plane scan of the next frame. The pattern on delay, Tpo, is given by, TPO
=
TBPS
+
TFLC
+
TEX
(1)
and the balance delay, TB, by, TB
=&Lc+TEx,
(2)
where, Tops is the bit-plane scan time; Tnc is the liquid crystal settling time (assuming symmetrical switch-
D.C. Burns et al. /Optics Communications 119 (1995) 623-632
I I
Nth
PATTERN ON DELAY
1 SCAN i I I "00
CK
f(
;
II
I:I II
0
If
II
"00
LATCH A
0
iBALANCE; (N+l)th I ; DELAY I SCAN I I
1
I/ /I
II
I
I I
I
II >t / II I I I
I
A VFLC FOR
621
+"DDo-
‘t
I ;
I
PIXEL Z
-"DD
v ;
Fig. 4. Charge balanced SLM drive scheme. Pixel A is in the left-most column of the pixel array and pixel Z is in the right-most column. Assume that both their latches are set to logic one in the Fth frame and logic zero in the preceding and succeeding frames. By toggling the global clock signal, CK, at appropriate times within the frame, the FLC above the pixels switch on and off simultaneously - there is no skew across the array.
ing) ; and TEX is extra time inserted to give the appropriate frame rate. Notice that a Topsterm must be included in Tpoto ensure proper charge balancing. Therefore, from Eqs. ( 1), (2), and adding TBPSfor the bit-plane scan, the frame rate fcx is given by 1 .fCK =
~(TBPS + TFLC + TEX) ’
From this, the maximum
frame rate, fcK_
(3) is given
by, 1 fCKw
=
~(TBPS + Tnc)
that is, when
’
(4)
TEX= 0.
5. Post-processing
and device assembly
The silicon backplanes are fabricated by the Austria Mikro Systeme [ 81 foundry using a 1.2 ,zrn nwell double-metal, 5.5 V, CMOS process. We have
used several of the SBS256 silicon wafers to help develop our in-house post-processing planarisation technique to significantly improve the fill factor and optical quality of the electrode mirrors. The planarisation technique is described in detail elsewhere [ 91. Briefly, planarisation involves the deposition of a thick dielectric layer (3-4 pm) over the foundry wafer which is polished flat using chemical-mechanical polishing. A further metal layer is then patterned to form opticallyflat electrode mirrors that almost completely cover the underlying pixel circuits and buslines (see Fig. 5). Our present set of photolithographic masks generate 37 x 37 pm2 mirrors over the 40 x 40 pm* pixels, thus giving us an 84% flat fill factor when the area of the via hole is taken into account. We expect to improve this figure as we refine the technique. After a wafer of silicon backplanes has been postprocessed and probe tested to identify candidate die, it is diced up, and the candidates are glued into pin grid array packages and gold bonding wires are attached. The SLM assembly procedure is performed in a clean
D. C. Bwns et al. /Optics
Cotutnunicurions
I19 (1995) 623432
Fig. 5. Photomicrographs of a group of six pixels (a) without, and (b) with post-processing flat fill factor is 7-T%, while for the planarised devices it is 84%.
planarisation.
For unplantised
devices the
D.C. Burns et al/Optics
Communications 119 (1995) 623-632
room environment. All equipment and substrates are meticulously cleaned to minimise contamination. A 12 mm x 12 mm x 1.l mm block of optically-flat, Indium Tin Oxide (ITO) coated glass is used as the cover glass with the IT0 coating providing the front electrode signal to the pixel array. A thin aluminium film is deposited onto one of the thin faces and onto the edge of the ITO-coated face. The film serves as a connection between the conducting IT0 film and front electrode bonding wire (see Fig. 1) . Asymmetric medium angle deposition SO, alignment layers are evaporated onto the cover glass. This structure gives relatively strong surface anchoring of the ELC molecules. Four spots of UV curing glue, impregnated with 2 pm spacer balls, are placed at the corners of the cover glass. The cover glass is then placed carefully atop the active area of the backplane chip, and the glue is cured with an ultra-violet lamp. The front electrode bonding wire is then glued to the aluminium film on the edge of the cover glass. The device is tilled with Merck-BDH SCE13 FLC material [lo] elevated temperature (> lO@‘C), and at low pressure ( < 10P5 TOIT). Finally, the device is slowly cooled back down to room temperature. It can be optically assessed under a polarising microscope while patterns are scanned into it from a computer controlled interface.
6. Electrical functionality
tests
Numerous testpoints and structures are included on the backplane to verify circuit functionality and also to help determine yield during probe testing. With the testpoints, we have verified that the data shift registers and enable decoder can operate at up to 24 MHz, resulting in a potential frame scan time of 85 ,ZS. Note that all of the circuits on the backplane are based on static logic designs and can therefore also be clocked arbitrarily slowly. This permits the device to be driven by very simple interface logic and controlled by a relatively low performance personal computer. The yield of the backplane is affected by defectinduced shorts and open circuits in the densely packed metal interconnect layers within the pixel array. Some of the interconnect signals, such as power rails and the global pixel clock signal, are connected directly to external circuitry and pads, and can therefore be probed
629
with a volt meter or oscilloscope to check their integrity. However, other signals such as the DATAs and /ENABLES are generated and distributed entirely onchip and so are not as readily accessible. To help test the integrity of these lines, some simple test structures are included along the edges of the pixel array. From the six wafers we have tested, each with 21 candidate die, the yield test structures have shown us that we can expect about 50% of the backplanes to have no dysfunctional DATA, /ENABLE or CK lines within the pixel array. Another 32% can be expected to function with one or more ‘dead’ lines or blocks caused by defect shorts or open-circuits. These partially functioning backplanes can be made into devices and used in applications where a full 256 x 256 pixel array is not required. The remaining 18% of backplanes have fatal shorts that draw large currents from the power supply and therefore should not be used because of the risk of damaging the driver interface circuits. The yield figures are very encouraging considering the high circuit and interconnect density within the pixel array.
7. Optical characterisation Both unplanarised and planarised backplanes have been made into SLM devices. Fig. 6 shows a test pattern on a 128 x 128 section of an unplanarised device operating in amplitude modulation mode and viewed under a polarising microscope. A close-up section of a planarised device is shown in Fig. 7: note the high flat fill factor (84%) of the pixels. The pixel contrast ratio is approximately 8:l - a typical value for SLM backplanes. To measure the FLC response times, a device is placed in a simple optical system where the output pattern is focused onto a photodiode detector. An ‘all ON’ pattern is scanned onto the SLM, and CK toggled at 1 kHz. The rise time TicRlsE = 150f5 ps, while the fall time 7-m~~~~ = 55f5 pus (see Fig. 8). Mao and Johnson [ 111 have also reported asymmetrical switching times for their neural-backplane FLCOS SLM. The asymmetry may be due to the single-sided FLC alignment layer. For our present devices, the potential frame rate of the device is limited by TmcRIsE. Assuming data is loaded onto the backplane at 24 MHz (Tars = 85 ps), and using Eq. (4). the maximum
630
D. C. Burns el al. /Optics
Communications
I1 9 (1995) 623432
Fig. 6. A test pattern on a 128 x 128 section of an unplanarised device.
frame rate is 2.1 kHz which has been verified.
8. Discussion and conclusions We have presented the SBS256, a general purpose 256 x 256 SRAM-XOR pixel FLCOS SLM, that incorporates an SRAM latch and XOR-gate in each pixel. The pixel circuit overcomes many of the performance limitations of the DRAM-type circuit used elsewhere, to provide robust data storage, and the ability to drive high spontaneous polarisation FLC mixtures. The XOR gate in each pixel permits the FLC layer to be charge balanced without the use of a pattern/inverse pattern drive scheme, so the device can be used with a continuous illumination. Also, by tog-
gling the global pixel clock signal at the appropriate times within the frame period, all the programmed ON pixels can be switched on and off simultaneously there is no addressing skew associated with the viewed image. With our present assembly techniques, the SBS256 can operate at a fully charged balanced frame rate of 2.1 kHz. With better cell assembly techniques, for example by using a thinner FLC layer, a 4 kHz frame rate should be possible. We have also demonstrated that post-processingplanarisation techniques can be used to increase the pixel fill factor from 23% to 84%. Further improvements can be expected with developments in the technique. Future SRAM-XOR backplane designs could dispense with the low fill factor mirror altogether (a min-
D. C. Burns et al. /Optics
Communications I I9 (1995) 623-632
Fig. 7. A test pattern on close-up section of a planarised
I -
ai’
I ,
o
___,_ 0
0.2
0-l
/ 0.6
i s-.-, 0.8
631
device
- 0.2
I
.I “”
I
I.?
,
I
I
I.4
1.6
18
......
7
TIME lmsl
Fig. 8. Optical response
of the WC.
Here the global FE (= CK) signal are toggled at 1 kHz.
The rise time TmRlsE = 1502~5ps, while
the fat) time &cFALL= 55f5 ps. imum size via node would still be necessary to connect the third-level metal mirror to the underlying circuitry ), thus making the SRAM-XOR type pixel more competitive in terms of area, with the DRAM-type pixel.
Acknowledgements The device fabrication was funded by the Engineering and Physical Sciences Research Council as part of the Scottish Collaborative Initiative in Optoelec-
h?Z
D.C. Burns et al. /Optics
Communications
tronic Sciences. D.C. Burns acknowledges the financial support of the Department of Education Northern Ireland. The authors gratefully thank T. Stevenson and A.D. Ruthven for their assistance in this work.
References ] I ] 1. Underwood, D.G. Vass, R.M. Sillitto, G. Bradford, N.E. Fancey, A.O. Al-Chalabi, M.J. Birch, W.A. Crossland, AI? Sparks and S.G. Lantham, in: Proc. SPIE, Vol. 1562, ed. D.M. Gookin (1991) p. 107. [ 21 M.A. Handschy, L.K. Cotter. J.D. Cunningham, T.J. Drabik and SD. Gaalema, in: Spatial Light Modulators and Applications Technical Digest, Vol. 6 (Optical Society of America, Washington, DC, 1993) p. 14. [ 31 D.J. McKnight, K.M. Johnson and R.A. Serati, Optics Lett. 18 (1993) 2159.
I I9 (199.5) 623432
[4] K.M. Johnson, D.J. McKnight and I. Underwood, J. Quantum Electron. 29 (1993) 699. [ 5 1 1.Underwood, D.G. Vass and R.M. Sill&to, IEE Proceedings, Vol. 133 (1986) p. 77. [6] D.J. M&night, D.G. Vass and R.M. Sillitto, Appl. Optics 28 (1989) 4757. [7] L.K. Cotter, T.J. Drabik, R.J. Dillon and M.A. Handschy, Optics Lett. 15 (1990) 291. [ 81 Austria Mikro Systeme International GmbH, SchoS PremsRhten, 8141 Unterpremsb%ten, Austria. [9] A. O’Hara, 1. Underwood and D.G. Vass, in: Technical Digest of the Optical Fabrication and Testing Workshop, Vol. 13 (Optical Society of America, Washington, DC, 1994) p. 86. [lo] Merck Ltd. Merck House, Poole, Dorset, England. [ 111 C.C. Mao and K.M. Johnson, Appl. Optics 32 ( 1993) 1290.