A 860 kHz grounded memristor emulator circuit

Accepted Manuscript Regular paper A 860 kHz Grounded Memristor Emulator Circuit C. Sánchez-López, L.E. Aguila-Cuapio PII: DOI: Reference:

S1434-8411(16)31542-4 http://dx.doi.org/10.1016/j.aeue.2016.12.015 AEUE 51755

To appear in:

International Journal of Electronics and Communications

Received Date: Accepted Date:

26 May 2016 20 December 2016

Please cite this article as: C. Sánchez-López, L.E. Aguila-Cuapio, A 860 kHz Grounded Memristor Emulator Circuit, International Journal of Electronics and Communications (2016), doi: http://dx.doi.org/10.1016/j.aeue.2016.12.015

This is a PDF file of an unedited manuscript that has been accepted for publication. As a service to our customers we are providing this early version of the manuscript. The manuscript will undergo copyediting, typesetting, and review of the resulting proof before it is published in its final form. Please note that during the production process errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.

A 860 kHz Grounded Memristor Emulator Circuit C. S´anchez-L´opeza,∗, L.E. Aguila-Cuapioa Department of Electronics, Autonomous University of Tlaxcala Clzda. Apizaquito S/N, km. 1.5, Apizaco, Tlaxcala, 90300, Mexico a

Abstract A grounded memristor emulator circuit operating from 16 Hz to 860 kHz is proposed. The emulator circuit is built around a plus-type second generation current conveyor, a four quadrant analog multiplier, a capacitor and a resistor. Two DC voltage sources are used for controlling the zero crossing of the frequency-dependent pinched hysteresis loop over a broad range of amplitude Am of the input signal, and principally when the memristor emulator circuit is operating at high-frequency. It describes in detail the derivation of the behavioral model of the proposed emulator circuit, including parasitic elements and showing that the charge-controlled memductance is a first-order function. Furthermore, a design guide to choose the numerical value of each discrete element in function of the operating frequency and Am is also given. The emulator circuit is built with off-the-shelf devices, and numerical results obtained by means of the behavioral model are compared with HSPICE simulations and experimental tests, showing good agreement among all them in a wide range of frequencies. This is against with some memristor emulator circuit available in the literature which present a good behavior at low-frequency and however, the zero crossing of the pinched hysteresis loop is deviated when the operating frequency increases. It is worth to stress that for the best knowledge of the authors, this is the first memristor emulator circuit that is operating to high-frequency. Moreover, the proposed emulator circuit can be configured as decremental or incremental memristor in order to be used in future applications such as cellular neural networks, modulators, sensors, chaotic systems, relaxation oscillators, nonvolatile memory devices and programmable analog circuits. Keywords: Memristor emulator, pinched hysteresis loop, nonlinear resistor. ∗

[email protected]

¨) Preprint submitted to Int. J. Electron. Commun. (AEU

December 29, 2016

1. Introduction Memristor is a two terminal element that can be controlled by flux or charge [1]-[3]. There are, basically, four possible configurations: charge- or flux-controlled memristance or memductance, where the former is the inverted version of the latter. In any case, the memristor can be configured to operate at incremental or decremental mode. Moreover, to study and research several real applications based on memristors, not only a lot of computer models have been proposed to be used in numerical simulations [4]-[12], but emulator circuits have also been reported in the literature [13]-[24]. In fact, different memristor emulator circuits using different active devices were developed due to that a solid-state memristor was not commercially available [25]-[27]. In this context, the integrated circuit called Neuro-Bit, has been released for sale by Bio Inspired Technologies [28], which offers chips with 8 or 20 functional chalcogenide-based ion-conducting memristor devices. However, these chips are still expensive and are limited to operate at incremental mode. This a serious drawback since some applications need both kind of memristors. For instance, one pair of incremental and decremental memristors are used to mimic the synapsis of a neuron by using a bridge circuit [29]. Furthermore, an environment highly controlled must be used during tests in order to avoid irreparable damage to the device. All in all, memristor emulator circuits are still important to study and research real applications as those mentioned above. As a consequence, a lot of emulator circuits using off-the-shelf components have been developed to imitate not only the real behavior of a non-inverted and inverted memristor [30], but also the real behavior of meminductors and memcapacitors [31]. In the context of memristor emulator circuits, these can be designed using different techniques, such as: analog, digital, hybrid or mutators. Depending of the application, any emulator circuit must accomplish some properties, some of them are: the frequency-dependent pinched hysteresis loop for any kind of flux- or chargecontrolled incremental or decremental memristor/memductor, in its version grounded or floating, must pass through the origin for any periodic signal with any amplitude, operating frequency and initial conditions; the possibility for controlling the initial state of the emulator circuit, i.e., adjust of the initial conditions; non-volatility; memristive/memductive behavior at highfrequency and without offset, etc. A survey on the basic concepts on the 2

design of memristor emulator circuits is given in [32], Chapter 22. Most emulator circuits have been built using a large number of active and passive components such as op amps, current feedback operational amplifiers, positive second generation current conveyors (CCII+), differential difference current conveyor, analog multipliers, micro-controller unit, analog to digital converters and viceversa, see [25]-[27] and the references cited therein. As a consequence, emulator circuits not only become complex and bulky, requiring rigid conditions to operate, but also some emulators do not exhibit those fingerprints that are useful to affirm that the emulator circuit is a memristor or memristive device [33]-[39]. From all them, the frequency-dependent pinched hysteresis loop must pass through the origin for any periodic signal with any amplitude, operating frequency and initial conditions. In each topology, however, the pinched hysteresis loop is deviated of the origin, which is more evident when the operating frequency of the input signal increases. Therefore, all memristor emulator circuits reported until today in the literature can model the behavior of a memristor only at very low-frequency, reducing their application range. Furthermore, below a certain critical frequency, the emulator circuit mimics the behavior of a memristor and beyond of that critical frequency, the emulator becomes a memristive device with an additional battery in series [40]. A technique for achieving that the frequency-dependent pinched hysteresis loop associated to a memristor emulator circuit is operating at highfrequency and without be deviated of the origin, was recently introduced in [41]. The technique involves in add two DC voltage sources in the analog multiplier in order to vertically and horizontally control the offset on the hysteresis loop. However, as described in [41], this offset reduction technique is only applicable to floating and grounded memristor emulator circuits whose design is based on analog multipliers. Because a memristor emulator circuit can be used in the high speed signal processing, the development of simple emulators operating at high-frequency is widely demanded. This paper concentrates on deriving a simple grounded memristor emulator circuit compensated in offset, operating at high-frequency and whose design is based on CCII+, a four quadrant analog multiplier, a capacitor, a resistor and two DC voltage sources. It is important mention that the derived memductance of the proposed memristor emulator circuit is linearly dependent on the charge. Therefore, memristor emulator circuits with general memductance vs. state characteristics are not considered. In Section II, the memristor emulator circuit is introduced and its behavioral model is also deduced. In this point, 3

  < 

     




  





; 





   

= 

< 

6



< 

 : 










: 

; 

 




 =

 ;










 99 9+




 

Figure 1: Memristor emulator circuit compensated in offset.

we show that the memristor emulator circuit compensated in offset can be configured as incremental or decremental memristor by using a single switch. In Section III, we analyze the frequency performance of the behavioral model and numerical simulations as well as HSPICE results are presented. A design guide is explained in order to select the numerical value of the time-constant of the emulator circuit in function of the operating frequency and Am . In Section IV, theoretical derivations are validated through lab tests by using off-the-shelf devices and showing that the frequency-dependent pinched hysteresis loop is holding up to 860 kHz. Comparisons among the proposed memristor emulator circuit and those reported in the literature are also described. Finally, in Section V, conclusions are summarized. 2. Proposed Emulator Circuit The grounded memristor emulator circuit compensated in offset is shown in Fig. 1. Here, Rx and Rz are parasitic resistances at the x - and z -terminal, respectively; Ca is the parasitic capacitance at node 1 and Rb is a resistor that will be used to adjust the behavior of the integrator circuit at high-frequency; RaH and RbH are the upper and lower resistances of a 20kΩ precision potentiometer with ±1% of tolerance, which are varied to obtain the VH voltage source; whereas RaV and RbV are also the upper and lower resistances of other 20kΩ precision potentiometer with ±1% of tolerance, which are varied to obtain the VV voltage source. ±Vdd is the supply voltage. According to CCII+ properties on the linear region [42], it is characterized by vx (t) = Av vy (t),

iy (t) = 0,

iz (t) = Ai ix (t)

(1)

where Av and Ai are the voltage and current gains of the voltage and current followers, respectively. It is important to mention that Av and Ai are finites 4

and of limited bandwidth, however, according to [42], the corner frequency for both followers occurs at MHz range. Because the maximum operating frequency of the proposed memristor emulator circuit is less than the corner frequency of both followers, Av and Ai are considered as frequency independent. Analyzing Fig. 1 one gets the following relations (R1 + Rx )im (t) = vm (t) − Av v2 (t)

(2)

v1 dv1 (t) − (3) dt Rz ||Rb Combining (3) and the third relation of (1), one obtains Z t Ai 1 qm (t) − v1 (τ )dτ (4) v1 (t) = − C1 + Ca (Rz ||Rb )(C1 + Ca ) 0 Rt where qm (t)= 0 im (τ )dτ . Here, we consider that the initial condition of the integrator is zero. Moreover, the memristance into a decremental memristor decreases proportionally with the voltage drop across the terminals of the memristor, whereas for an incremental memristor the memristance increases. In order to achieve these effects, a four-quadrant analog multiplier is used. According the AD633JN data sheet [43] and Fig. 1, we have two cases a) Incremental mode iz (t) = −(C1 + Ca )

v2 (t) =

(X1 − X2 )(Y3 − Y4 ) vm (t) − VH +Z = v1 (t) + VV 10 10

(5)

b) Decremental mode v2 (t) =

VH − vm (t) (X1 − X2 )(Y3 − Y4 ) +Z = v1 (t) + VV 10 10

Combining (5) and (6) and substituting in (2), one gets   Av Av VH v1 (t) ± v1 (t) − Av VV (R1 + Rx )im (t) = vm (t) 1 ∓ 10 10

(6)

(7)

Finally, considering that the charge-controlled memductance is defined as im (t) =W (qm (t), VV , VH ) and including (4) in (7), one obtains vm (t)   Av VV 1 1 − W (qm (t), VV , VH ) = R1 +R vm (t) x V   (8) Rt 1− v H(t) ± 10(R1 +Rxm)(C1 +Ca ) Av Ai qm (t) + Rz 1||Rb 0 v1 (τ )dτ 5

In practice, Rz ≈3 MΩ [42] and due to the nonlinearities of the integrator, Rb will be used with a high-value in order to prevent charge to Cz by the offset currents and voltages at the frequency of interest. Therefore, (8) can be approximate as     Av Ai qm (t) Av VV VH 1 (9) W (qm (t), VV , VH ) ≈ R1 +Rx 1 − vm (t) ± 10(R1 +Rx )(C1 +Ca ) 1 − vm (t) From (9), one can see that both memductances are not only function of the charge and of the DC voltage sources, but the derived behavioral model is also a first order function. Here, VV and VH will be used to vertically and horizontally control the offset of the frequency-dependent pinched hysteresis loop on the voltage-current plane. Note that when VV =VH =0, the ideal behavior and without offset of the pinched hysteresis loop is obtained. Moreover, when VV 6= VH 6=0, the frequency-dependent pinched hysteresis loop is pushed or pulled from origin, according the numeric value of the DC voltage sources, as will be demonstrated in Section 3. In particular, one can observe in Fig. 1 that four DC supply voltages are required to bias the emulator circuit: ±Vdd , VH and VV , but in general, the two last voltage sources can be designed by using precision potentiometers, connecting their extremes to +Vdd and −Vdd and the middle terminal is VH or VV , as shown in Fig. 1. Regarding again to Fig. 1, the switch S is used to interchange the kind of memristor, where I denotes the incremental topology whereas D denotes the decremental topology. 3. Frequency Performance Having derived the behavioral model of the memristor emulator circuit shown in Fig. 1, now we are able to do a frequency analysis. Following the idea given in [19, 24], we assume that vm (t)=Am sin(ωt), where ω=2πf and Am is the amplitude of the voltage signal source in Fig. 1. According the behavior of the frequency-dependent pinched hysteresis loop, this is composed by two lobes with symmetric areas. Since the hysteresis loop is represented on the v-i plane, the average current occurs when the area of both lobes is zero and therefore, the hysteresis loop tends to a straight line as f → ∞. This last effect is achieved when the linear time-varying part of the memristor is zero and hence, from (9), we get im (t) =

vm (t) − Av VV Am sin(ωt) − Av VV = R1 + R x R 1 + Rx 6

(10)

Rt By definition, qm (t)= 0 im (τ )dτ and as consequence qm (t) = −

Am Av VV t cos(ωt) − ω(R1 + Rx ) R1 + R x

(11)

Substituting (11) in (9), the memductance is rewritten as 1 v Ai Am W (qm (t), VV , VH ) = R1 +R ± 10ω(R1A+R x  x )2 (C1 +Ca )  VH × cos(ωt) + AvAVmV ω t vm −1 − (t)

Av VV (R1 +Rx )vm (t)

(12)

One can observe that the memductance is composed of a linear time-invariant admittance, a linear time-varying admittance and an additional battery in series. Similarly as [19, 24], the relationship between the first two parts can be described by the ratio of their amplitudes, given as k=

1 T Av Ai Am = = 10ω(R1 + Rx )(C1 + Ca ) τf τ

(13)

where

20π(R1 + Rx )(C1 + Ca ) (14) Av Ai Am is the time constant of the emulator circuit and T=1/f is the period of vm (t). A similar procedure can be studied between the amplitudes of first and third part of (12), given as (15) ka = Av τ=

and the relation between the amplitudes of the second and third part of (12) is given as Ai Am (16) kb = 10ω(R1 + Rx )(C1 + Ca ) Comparing (13), (15) and (16), one can observe that (13) gives more information on the frequency performance of the emulator circuit. Furthermore, when the frequency-dependent pinched hysteresis loop does not present, in the best case, an offset in the zero crossing, then VV =VH =0 and (12) is reduced to 1 Av Ai Am cos(ωt − π) W (qm (t)) ≈ ± (17) R1 + Rx 10ω(R1 + Rx )2 (C1 + Ca ) and hence, (13) is still holding, whereas (15) and (16) disappear. Besides, from (12) and (13) and assuming that Am , VV and VH are constant and nonzero, one can intuit that k will decrease as the frequency increases, but (12) also reveals that 7

1. k →0 when f → ∞. The memductive behavior becomes dominated by its linear time-invariant admittance and presents an offset on the vertical-axis which depends of VV . 2. k →1 when f → τ1 . The maximum pinched hysteresis loop is achieved and the crossing-point exhibits an offset on the horizontal and vertical axes, which depends of VH and VV . 3. k ≥1 when f ≤ τ1 . The hysteresis loop is lost, regardless of VH and VV . This means that T is larger than τ . Moreover, if VV and VH are constant and nonzero, f is fixed and Am is varied, (12) and (13) reveal another interesting behavior 4. k →0 when Am decreases. The memductive behavior becomes also dominated by its linear time-invariant admittance and exhibits an offset on the vertical-axis which depends of VV . 5. k →1 when Am is monotonically increased. As a consequence, the maximum pinched hysteresis loop not only is achieved, but the crossingpoint also exhibits an offset on the horizontal and vertical axes, which depends of VH and VV . 6. k ≥1 when Am increases too much. In this case, the hysteresis loop is also lost, regardless of VH and VV . This means that T is constant whereas τ is modified. Additionally, when f and Am are fixed, and VV along with VH take positive or negative values, the crossing-point of the hysteresis loop can be moved on the voltage-current plane. It is worth noting that (12) is not modeling the offset of the emulator circuit, which is due, principally, to the parasitic elements associated to each input-output terminal of the active devices, the offset of the same active devices and by the integrator circuit nonidealities. The latter is because the integrator circuit will have a low-pass filtering effect and when an offset voltage is present in the input signal, it will accumulate until a certain limit or overflow is reached. Due to this feature, not only the hysteresis loop becomes deformed, resulting an asymmetrical behavior, but also the areas enclosed in the first and third quadrant are not equals. Nonetheless, (12) is including a mechanism to pull or push the crossing-point of the hysteresis loop towards the origin and hence, the upper and lower lobe area of the hysteresis loop will be relatively equal [34]. On the other hand, the behavior of the frequency-dependent pinched hysteresis loop can be kept over a broad range of frequencies and amplitude Am , 8

!

Figure 2: Variation of (18) in function of f and Am .

whether the numerical value of k is on the interval (0,1) [19, 24]. This means that (14) must be updated according to f and Am , respectively. Therefore, from (13) we get Av Ai Am (R1 + Rx )(C1 + Ca ) = (18) 20πkf Figure 2 shows the approximated numerical value that must be selected for (R1 + Rx )(C1 + Ca ) in function of the frequency and Am , which has been obtained from (18) and assuming that Av =Ai =0.98 and k =0.5. Referring again to Fig. 2, one must be careful on how to select the numerical value of R1 and C1 , since they can be smaller than parasitic elements on the x - and z -terminal of the AD844AN given as Rx ≈75Ω and Cz ≈5.5pF, and on the Y -terminal of the AD633JN shown in Fig. 1, given by CY 3 ≈CY 4 ≈2pF. Note that the parasitic capacitance among the horizontal connection lines of the breadboard (Cbb ) or printed circuit board should be also taken into account during experimental tests. According to [44], the approximated parasitic capacitance between two adjacent lines into a breadboard is 2.7pF and this decreases when the distance between lines increases. In order to minimize the effect of the parasitic capacitances of the breadboard during experimental tests of Fig. 1, C1 was connected at least 5 lines of separation, which gives a parasitic capacitance Cbb =1pF. Therefore, the total parasitic capacitance at node 1 of Fig. 1 is Ca =Cz +Cbb +CY 3,Y 4 , respectively. Besides the described above, although the considered range for Am in Fig. 2 is [0,10], the permitted maximum value will depend on the bias voltages. Once the behavioral model 9

Table 1: Component list of Fig. 1.

Element R1 Rb C1 VH VV R1 Rb C1 VH VV R1 Rb C1 VH VV ♣

Macromodel HSPICE Experimental Inc. Dec. Inc. Dec. Inc. Dec. For f =16 Hz and 500 Hz 38.2 kΩ (Precision potentiometer) open circuit 0.1µF (±20%) 30mV 30mV 0 0 0 0 -50mV -53mV 70mV For f =860 kHz uncompensated 30kΩ (±5%)♣ 8.3 kΩ (Precision potentiometer) open circuit 10kΩ (±5%) 0 ♣ 0.24V 0 -0.24V♣ 0.32V♣ 0 For f =860 kHz compensated 30kΩ (±5%)♣ 8.3 kΩ (Precision potentiometer) open circuit 10kΩ (±5%) 0 10µV 50mV 22mV -87mV 0 0 214mV -290mV -7.2V 7.25V

Values used to fit numerical results to HSPICE and experimental results.

for each incremental and decremental memristor has been deduced, numerical simulations can be realized. Table 1 gives the numerical values of the elements of Fig. 1 associated to the minimum and maximum operating frequency. However, one can do a similar analysis for other operating frequencies as already shown in [24]. Here, Am =2V along with a bias voltage of ±Vdd =±10V were used. Henceforth, numerical results of the incremental topology will be shown below in the left-side whereas for the decremental topology will be shown in the right-side. In a first step, we consider VH =VV =0, f =16 Hz and according to Fig. 2, (18) and Table 1, we obtain (R1 + 75)(C1 + 8.5p) = 3.8213e−3

(19)

It is evident from (19) that at low-frequency, the parasitic capacitance is negligible. From (12), numerical results for each topology are depicted in Fig. 3(a) (solid line) and Fig. 3(b) (solid line), where vR1 (t)=vm (t)-v3 (t)=im (t)R1 10

,

!"#

! -./012'03)45,10675),(89%"#:,o9%"$!#* ;<=>?-,62'754)2@3,(89%"#:,o9%"$!#* A4B1@'@C05,(89%"#:,o9%"$!#*

$"#

-./012'03)45,10675),(89%"#:,o9%"$!#* ;<=>?-,62'754)2@3,(89%"#:,o9%"$!#* A4B1@'@C05,(89%"#:,o9%"$!#*

$"#

$

$

%"#

%"# &+$()*(&*

&+$()*(&*

,

!"#

!

% ï%"#

%

ï%"#

ï$

ï$

ï$"#

ï$"#

ï!

ï!

ï!"# , ï!"#

!"#

ï!"# , ï!"#

,

!"#

ï!

ï$"#

ï$

ï%"#

% &'()*(&*

%"#

$

$"#

!

ï!

ï$"#

ï$

(a)

% &'()*(&*

%"#

$

$"#

!

!"#

(b)

!"#

,

!

! -./012'03)45,10675),(89%"%$:;,o9%"$!#* <=>?@-,62'754)2A3(89%"%$:;,o9%"$!#* B4C1A'AD05,(89%"%$:;,o9%"$!#*

$"#

-./012'03)45,10675),(89%"%$:;,o9%"$!#* <=>?@-,62'754)2A3(89%"%$:;,o9%"$!#* B4C1A'AD05,(89%"%$:;,o9%"$!#*

$"#

$

$

%"#

%"# &+$()*(&*

&+$()*(&*

ï%"#

%

% ï%"#

ï%"# ï$

ï$

ï$"#

ï$"#

ï!

ï!

ï!"# , ï!"#

ï!"# , ï!"#

ï!

ï$"#

ï$

ï%"#

% &'()*(&*

%"#

$

$"#

!

!"#

(c)

ï!

ï$"#

ï$

ï%"#

% &'()*(&*

%"#

$

$"#

!

!"#

(d)

Figure 3: Comparing experimental, numerical and HSPICE results of the pinched hysteresis loop operating at: (a) 16 Hz and (c) 500 Hz, for incremental topology; (b) 16 Hz and (d) 500 Hz, for decremental topology.

has been used to indirectly plot im (t). Let us now to increase monotonically the operating frequency of vm (t) until f =500 Hz. As depicted in Fig. 3(c) (solid line) and Fig. 3(d) (solid line), the frequency-dependent pinched hysteresis loop for both topologies becomes dominated by the linear timeinvariant admittance. In this stage, for widening the hysteresis loop of each topology and keeping f =500 Hz, C1 must be adjusted to 3.2nF or R1 =1.147 kΩ. In both cases, the contribution of the parasitic elements is negligible. The topology shown in Fig. 1 was also simulated in HSPICE by using the same numerical values of the passive elements given in Table 1 and on the 11

-./012'03)45,10675),(89%"#:,o9!";!#?@A-,62'754)2B3(89%"#:,o9!";!#
!

! -./012'03)45,10675),(89%"#:,o9!";!#?@A-,62'754)2B3(89%"#:,o9!";!#
$"#

$"#

$

$

%"#

%"# &+$()*(&*

&+$()*(&*

,

!"#

,

!"#

%

% ï%"#

ï%"# ï$

ï$

ï$"#

ï$"#

ï!

ï!

ï!"# , ï!"#

ï!"# , ï!"#

ï!

ï$"#

ï$

ï%"#

% &'()*(&*

%"#

$

$"#

!

!"#

ï!

ï$"#

ï$

(a)

%"#

$

$"#

!

!"#

,

!"# !

! -./012'03)45,10675),(89%"$:;$<,o9=":>!!!* ?@ABC-,62'754)2D3(89%"$:;$<,o9=":>!!!* E4F1D'DG05,(89%"$:;$<,o9=":>!!!*

$"#

-./012'03)45,10675),(89%"$:;$<,o9=":>!!!* ?@ABC-,62'754)2D3(89%"$:;$<,o9=":>!!!* E4F1D'DG05,(89%"$:;$<,o9=":>!!!*

$"#

$

$

%"#

%"# &+$()*(&*

&+$()*(&*

% &'()*(&*

(b) ,

!"#

%

% ï%"#

ï%"# ï$

ï$

ï$"#

ï$"#

ï!

ï!

ï!"# , ï!"#

ï%"#

ï!

ï$"#

ï$

ï%"#

% &'()*(&*

%"#

$

$"#

!

!"#

(c)

ï!"# , ï!"#

ï!

ï$"#

ï$

ï%"#

% &'()*(&*

%"#

$

$"#

!

!"#

(d)

Figure 4: Comparing experimental, numerical and HSPICE results of the pinched hysteresis loop operating at 860kHz: (a) uncompensated and (c) compensated, for incremental topology; (b) uncompensated and (d) compensated, for decremental topology.

same operating frequencies mentioned above. Figure 3(a) (dash-dot line) and Fig. 3(b) (dash-dot line) show the pinched hysteresis loops operating at 16 Hz, whereas Fig. 3(c) (dash-dot line) and Fig. 3(d) (dash-dot line) depict the hysteresis loop operating to 500 Hz. On these simulations, we note that the crossing-point of the pinched hysteresis loops was slightly deviated of the origin and hence, was necessary to update the DC voltage sources, as given in Table 1. As first conjecture, our results indicate that the derived memristor behavior models introduce a relatively low level of inaccuracy compared with HSPICE results. According to Fig. 3, one can observe that at low-frequency, 12

not only the parasitic capacitances are negligibles, but also the crossing-point of the hysteresis loop for both topologies does not deviate drastically of the origin, confirming the mentioned above issues. In a second step, we increase the operating frequency of vm (t) until f =860 kHz, keeping VH =VV =0 and by considering the numerical value of Rb and C1 given in Table 1 (i.e., for macromodel case), we have (R1 + 75)Ca = 7.109e−8

(20)

and hence R1 =8.289 kΩ. Numerical results of the pinched hysteresis loop for each operation mode of Fig. 1 are ilustrated in Fig. 4(a) (solid line) and Fig. 4(b) (solid line). It is clear that (17) can model the pinched hysteresis loop for any operating frequency and amplitude, keeping the crossing-point in the origin. This ideal behavior, however, is lost when the emulator circuit was simulated on HSPICE. Simulation results are depicted in Fig. 4(a) (dash-dot line) and Fig. 4(b) (dash-dot line), where Rb =10 kΩ was used to improve the phase behavior of the integrator circuit. Note that a level of offset is glimpsed on the v -i plane, getting a memductive behavior with an additional battery. It is worth to stress that this shortcoming does not happen in the behavior models since no information about of the offset is included on them. However, whether (12) is used at incremental mode, with VH =VV =240 mV and R1 =30 kΩ, the pinched hysteresis loop depicted in Fig. 4(a) (solid line) fits to Fig. 4(a) (dash-dot line). A similar behavior also occurs when (12) is configured at decremental mode, with VH =240 mV, VV =320 mV and R1 =30 kΩ. Consequently, the pinched hysteresis loop depicted in Fig. 4(b) (solid line) can be adjusted to Fig. 4(b) (dash-dot line). The latter gives us a starting point to select the numerical value of VH and VV in HSPICE simulations. On the other hand, to push the crossing-point of the hysteresis loop towards the origin during HSPICE simulations, the DC voltage sources shown in Fig. 1 were again updated. For the incremental case, VH =10 µV and VV =214 mV were used, whereas for the decremental mode VH =50 mV and VV =-290 mV were adjusted. As a consequence, the offset was minimized as shown in Fig. 4(c) (dash-dot line) and Fig. 4(d) (dash-dot line), respectively. In order to obtain a behavior similar among numerical results and HSPICE simulations, the numerical value for each element given in Table 1 (i.e., for f =860 kHz compensated) was used. Besides of the frequency-dependent pinched hysteresis loop, other important fingerprint of the emulator circuit is the nonvolatily of its memductance. 13

!5

4.2

x 10

3.9

Memductance (S)

3.5 3.1 2.7 2.3 1.9 1.5 1.1 0.7 0

0.1

0.2

0.3

0.4

0.5 Time (s)

0.6

0.7

0.8

0.9

1

0.6

0.7

0.8

0.9

1

(a) 1.1 1 0.9 0.8 Vin (V)

0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0

0.1

0.2

0.3

0.4

0.5 Time (s)

(b) Figure 5: Simulation results of the memductance change when a pulse train is applied across the memristor emulator circuit: (a) Incremental (blue line) and Decremental (black line) behavior; (b) Pulse train.

This means that once programmed the memductance, its last value must be keeping during a long time and when the input signal is not applied. By using the numerical values given in Table 1 for f =16 Hz and applying a pulse train at input terminal of the memristor emulator circuit with 1V of amplitude, 6.35 ms pulse width and 20.8 ms of period, one obtains the memductance change. Figure 5 shows the memductance change for both configurations and the pulse train. Note that during non-pulse period, the memductance is nonvolatile and its variation is negligible. For incremental topology, the memductance increases according the amplitude and pulse width, as depicted in Fig. 5(a) (blue line), whereas for the decremental topology, the memductance decreases (black line). On these figures, one can also obtain the memductance variation, which is given as: ∆Winc =15.5 µS for ∆t=356 ms, and ∆Wdec = 15.52 µS for ∆t=996.87 ms (or in terms of memristance ∆Minc = 15.41 kΩ and ∆Mdec =65.43 kΩ). It is worth to mention that the memduc-

14

Table 2: DC sensitivity analysis of Fig. 1.

Element Nominal Value Name Inc. Dec. R1 8.3kΩ Rb 10kΩ RaH 10kΩ 9.9kΩ RbH 10kΩ RaV 9.58kΩ 10kΩ RbV 10kΩ 9.43kΩ Rx 75Ω +Vdd +10V −Vdd -10V

Element sensitivity (volts/unit) Inc. Dec. -3.860e-08 3.740e-08 -1.152e-07 1.301e-07 -1.598e-05 -1.809e-05 1.595e-05 1.777e-05 5.210e-04 4.990e-04 -4.988e-04 -5.294e-4 -3.860e-08 3.740e-08 -4.941e-01 -4.665e-01 -4.727e-01 -4.967e-01

Normalized sensitivity (volts/percent) Inc. Dec. -3.171e-06 3.072e-06 -1.152e-05 1.301e-05 -1.598e-03 -1780e-03 1.595e-03 1.777e-03 4.992e-02 4.990e-2 -4.988e-02 -4.986e-2 -2.895e-08 2.805e-08 -4.941e-02 -4.665e-02 4.727e-02 4.967e-02

tance variation for both topologies not only can be achieved in the same time interval by modifying the pulse width and amplitude of the pulse train shown in Fig. 5(b), but the behavior for each memductance can also be reverted to its last value whether a negative pulse of the same size is applied. A similar analysis can be done for the rest of frequencies given in Table 1. On the other hand, an important feature in the design of any system is its robustness, which depends on the sensitivity of its components. In this way, a DC small-signal sensitivity analysis of Fig. 1 was done with respect to variations of the discrete and parasitic resistors as well as of the supply voltage and of the adjust process of VH and VV due to RaH , RbH , RaV and RbV , respectively. For this case and according to Table 1, Fig. 1 was configured for working to 860kHz for the compensated case and in each operation mode. Sensitivity analysis was performed on HSPICE and measured across vR1 (t). Results are reported in Table 2 and one can observe that the element more sensitive is the bias voltage. Nonetheless, the proposed topology is robust in small variations and near the operating point. However, this property gets lost in large variations. In order to research the variations of the frequency-dependent pinched hysteresis loop of Fig. 1 due to Rx and Ca , Monte Carlo simulations were done. It is worth mentioning that Rz was not considered since not only its contribution is insignificant, but also Rb has more impact on the variations, due that this element is connected in parallel with Rz and is used during the adjust process. Thus, Fig. 6(a) shows 15

!

!

(a)

(b) !

!

!

!

!

!

(c)

(d)

Figure 6: Monte Carlo analysis of Fig. 1 for: (a) parasitic and (c) adjust elements, at incremental mode; (b) parasitic and (d) adjust elements, at decremental mode.

numerical results for the incremental mode whereas Fig. 6(b) illustrates numerical results for the decremental mode, where the numerical value of Rx was randomly varied using a relative Gaussian distribution with 5% of tolerance on the nominal value given in Table 2 and for Ca =8.5pF as nominal value, was randomly varied using a relative Gaussian distribution with 20% of tolerance. Note that here, all parasitic capacitances at node 1 of Fig. 1, including Cbb , were taken into account. According to Fig. 6(a) and Fig. 6(b), one can observe that Fig. 1 is robust to variations due to the parasitic elements and hence, the frequency-dependent pinched hysteresis loop must not 16

be drastically modified when an active device is replaced by other. Similarly as above, Monte Carlo simulations were also done for those elements that are used to adjust the behavior of the hysteresis loop at a particular operating frequency. Therefore, Fig. 6(c) and Fig. 6(d) show numerical results for the incremental and decremental mode, respectively; where the nominal values of RaH , RbH , RaV and RbV given in Table 2 were randomly varied using a relative Gaussian distribution with 1% of tolerance, whereas for Rb a relative Gaussian distribution with 5% of tolerance was used. According to Fig. 6(d), one can observe that the decremental case has more variability than Fig. 6(c). Note that these two last figures have more variability than Fig. 6(a) and Fig. 6(b). After several experimental tests, it is concluded that RaH , RbH , RaV and RbV are the most sensitive elements and they are conditioning the robustness of the proposed circuit. 4. Experimental Tests Let us now validate the derived previously results and demonstrate the real behavior of the memristor emulator circuit. As expected, the proposed circuit shown in Fig. 1 was built with off-the-shelf devices and the numerical values of all discrete components given in Table 1 were also used during experimental tests and for each operation mode. In this manner, Fig. 3(a) (dashed line) and Fig. 3(b) (dashed line) show experimental results of the frequency-dependent pinched hysteresis loop for each topology and working to 16 Hz. It is worth to mention that at the decremental configuration, the voltage source VV was adjusted to 70mV, in order to pull the crossing-point of the hysteresis loop towards the origin. Furthermore, we can also note that the upper and lower lobe area of the hysteresis loop are relatively equals, resulting a symmetrical behavior. Afterwards, the operating frequency of vm (t) was increased to 500 Hz. Figure 3(c) (dashed line) and Fig. 3(d) (dashed line) show that the hysteresis loops become dominated by the linear time-invariant admittance, confirming the theory described before. Unfortunately, when the operating frequency was increased until 860 kHz, keeping VH =VV =0 and using the numerical values given in Table 1 for the uncompensated case, the memristor emulator circuit, at any operation mode, does not work, as illustrated in Fig. 4(a) (dashed line) and Fig. 4(b) (dashed line), respectively. Nevertheless, the DC voltage sources were updated according the compensated case and in each operation mode given in Table 1. As consequence, the frequency-dependent pinched hysteresis loops were 17

Table 3: NMSEs in percentages of vR1 (t) from Fig. 3 and Fig. 4.

Experimental vs. HSPICE vs. HSPICE Macromodel Macromodel In. Dec. Inc. Dec. Inc. Dec. For f =16 Hz 1.1884 1.1686 1.2329 1.2461 0.4313 0.0656 For f =500 Hz 0.1408 0.1415 0.231 0.222 0.0051 0.01715 For f =860 kHz uncompensated 8.2595 9.6835 11.2580 13.6409 3.6758 4.8863 For f =860 kHz compensated 0.7226 0.2635 0.6507 1.0904 0.1580 0.8846 again obtained, as depicted in Fig. 4(c) (dashed line) and Fig. 4(d) (dashed line). It is important to mention that to measure the voltage across the terminals of R1 , not only a differential amplifier based on CCII+ was used, but active scope probes were also employed, whose parasitic capacitance is less of 1pF. After several experimental tests we observe that for a wide range of frequencies, between 670 kHz and 860 kHz as top limit, the hysteresis loops cannot be widened so that k =0.5. For operating frequencies lower than 670 kHz, there is not any drawback. Furthermore, although the offset reduction technique suggests a viable and effective way to push or pull the crossingpoint of the hysteresis loop towards the origin, the numerical values of each DC voltage source must still be computed to trial and error. To validate the accuracy of the behavioral model compared with HSPICE simulations and experimental tests, the normalized mean-squared error (NMSE) of vR1 (t) was computed from Fig. 3 and Fig. 4. The NMSE for vm (t) is not computed since the voltage signal is the same for all simulations and experimental tests, respectively. Measured errors in percentages are given in Table 3. As it can be seen to f =16 Hz, the NMSE among experimental, HSPICE and macromodel results are relatively low; whereas the NMSE between HSPICE and macromodel results is lower, as shown at the third column in Table 3. Later, the NMSE among all data was reduced when the operating frequency increased to f =500 Hz. This is because the memductive behavior of the circuit becomes dominated by its linear time-invariant admittance. As expected, we observe that for the uncompensated case, with 18

CCII+ DDCC CCII+ CFOA Op Amp CFOA-OTA CCII+ Op Amp CCII+

Op Amp

CFOA

Op Amp

Topology based on

19 High Simple

Simple

Moderate Simple High

Simple

High

Complexity

First order

Memristance modeling Quadratic Cubic

Charge

Charge/Flux Charge Flux

Charge

Flux

Controlled by

Yes

No

Offset compensated

Frequency Maximum 1 kHz 400 Hz 100 Hz 800 Hz 1 kHz 100 kHz 100 kHz 20.2 kHz 700 Hz 1 kHz 590 Hz 160 kHz 1 kHz 860 kHz

[10] [12] [13] [14] [16] [17] [18] [19] [20] [22] [23] [24] [29] This work

Reference

Table 4: Comparison of the proposed memristor emulator circuit.

f =860 kHz, the NMSE increases in all data. Fortunately, after the offset compensation, the NMSE for all data decreased, as one can observe in the last row of Table 3. In this point, whereas the accuracy among experimental

(a)

(b)

Figure 7: Experimental measurement of v1 (t) in Fig. 1, when a pulse train is applied across the memristor emulator circuit: (a) Incremental mode; (b) Decremental mode.

vs. HSPICE data, along with experimental vs. macromodel data is high, the accuracy between HSPICE vs. macromodel data remains relatively higher. This is because HSPICE and macromodel results do not present at distortion at high-frequency, compared with experimental results shown in Fig. 4(c) and Fig. 4(d). After several experimental tests, we can conclude that the behavioral model given by (9) can be used from 16 Hz to 860 kHz, despite that the high-frequency behavior of the frequency-dependent pinched hysteresis loops, for both topologies, are dominated by the parasitic capacitance Ca . Finally, to experimentally test the non-volatility of the memristor emulator circuit with offset compensation, the voltage v1 (t) of Fig. 1 was measured for each configuration, incremental and decremental. In both cases, a rectangular pulse train of 5 V of amplitude with 82 µs is applied in the input of Fig. 1. Figure 7(a) shows the behavior of v1 (t) for the incremental case, whereas that Fig. 7(b) shows the decremental case. From Fig. 7, one can observe that the variation of v1 (t) is more pronounced for the decremental case, as has been predicted in Fig. 5. Observe, also, that the voltage is kept during non-pulse period. In order to plot the memductance as in Fig. 5, a post-processing must be done, by using (7) and the experimental data of v1 (t). It is worth to stress that the proposed emulator circuit was carefully analyzed in order to get a simple floating version and compensated in offset,

20

however, due to this feature, right now is not possible, since we glimpse an increase on the use of the active devices for getting that behavior. Furthermore, the proposed topology is compared with several topologies reported in the literature in terms of the kind of active device used to design the emulator circuit, its design complexity, the order of the modeling function, type of memristance, if it is or not compensated in offset and operating frequency, as summarized in Table 4. Here we can see that all topologies designed with different active devices are operating in low-frequency and are not compensated in offset, with the exception of the topology proposed herein. Besides, although the most of them use a first order function for modeling the chargecontrolled memductance, principally, some of them present a high design complexity. All in all and according to Table 2, Table 3 and Table 4, the proposed topology presents better features compared with those reported in the literature. Furthermore, as described in Section 3, the proposed topology can easy be designed in order to be used in real applications, since its design not only is fast, but also has low sensitivity, as given in Table 2 and illustrated in Fig. 6. 5. Conclusions A simple charge-controlled grounded analog memristor emulator circuit, that can be configured at incremental or decremental mode has been presented. The proposed emulator circuit was built with two active devices, two passive elements and two DC voltage sources, which results not only in being simpler than previously reported topologies, but also includes a mechanism to pull or push the crossing-point of the pinched hysteresis loop towards the origin. In this sense, although a quite number of complex memristor emulator circuits have been reported in the literature, they present a deviation of the crossing-point on the frequency-dependent pinched hysteresis loop, which is more evident when the operating frequency of the input signal increases, limiting their operation and application ranges. It is worth to mention that the charge-controlled incremental and decremental memductance not only is modeled by a first-order function and given by (9), but also to the best knowledge of the authors, a memristor emulator circuit working at highfrequency and compensated in offset has not been reported in the literature, until today. A design guide to keep the frequency-dependent pinched hysteresis loops, from 16 Hz until 860 kHz, was also described, which consists of how to select the numerical value of the time-constant of the emulator 21

circuit in function of the operating frequency and Am , such that k must be in the interval (0,1). Leveraging this design guide, a frequency analysis was also discussed for both topologies, showing how the frequency of vm (t) modifies the memconductive behavior. Experimental results using off-the-shelf devices were gathered, showing good agreement with numerical approximations according to Table 3. Finally, it is to be remarked that the proposed emulator circuit can be used in real-world applications and the behavioral model can also be used to better forecast the behavior of nonlinear circuits based on memristors [45], with low cost and easy reproducibility. 6. Acknowledgements This work was supported in part by the National Council for Science and Technology (CONACyT), Mexico, under Grant 222843; in part by the Universidad Aut´onoma de Tlaxcala (UATx), Tlaxcala de Xicohtencatl, TL, Mexico, under Grant CACyPI-UATx-2015; and in part by the Program to Strengthen Quality in Educational Institutions, under Grant P/PROFOCIE2015-29MSU0013Y-02. [1] Chua L.O. Memristor: The Missing Circuit Element. IEEE Trans. Circuit Theory. 1971; CT-18:507-519. [2] Chua L.O., Kang S.M. Memristive Devices and Systems. Proc. IEEE. 1976; 64:209-223. [3] Strukov D.B., Sneider G.S., Stewart D.R., Williams R.S. The Missing Memristor Found. Nature. 2008; 453:80-83. [4] Biolek Z., Biolek D., Biolkova V. SPICE Model of Memristor with Nonlinear Dopant Drift. RadioEng. 2009; 18:210-214. [5] Benderli S., Wey T.A. On SPICE Macromodelling of TiO2 Memristors. Electron. Lett., 2009; 45:337-338. [6] Sharifi M.J., Banadaki Y.M. General SPICE Models for Memristor and Application to Circuit Simulation of Memristor-based Synapses and Memory cells. J. Circuits, Syst. Comp., 2010; 19:407-424. [7] Shin S., Kim K., Kang S-M. Compact Models for Memristors Based on Charge-Flux Constitutive Relationships. IEEE Trans. Comput.-Aided Design. 2010; 29:590-598. 22

[8] Rak A., Cserey G. Macromodeling of the Memristor in SPICE. IEEE Trans. Comput.-Aided Design. 2010; 29:632-636. [9] Batas D., Fiedler H. A memristor spice implementation and a new approach for magnetic flux-controlled memristor modeling. IEEE Trans. Nanotechnology. 2011; 10:250-255. [10] Bo-Cheng B., Jian-Ping X., Guo-Hua Z., Zheng-Hua M., Ling Z. Chaotic memristive circuit: equivalent circuit realization and dynamical analysis. Chin. Phys. B. 2011; 20:120502:1-6. [11] Yakopcic C., Taha T.M., Subramanyam G., Pino R.E. Chapter 12: Memristor SPICE modeling. Advances in Neuromorphic memristor science and applications. Springer Series in Cognitive and Neural Systems. 2012; 4:211-244. [12] Bo-Cheng B., Fei F., Wei D., Sai-Hu P. The voltage-current relationship and equivalent circuit implementation of parallel flux-controlled memristive circuits. Chin. Phys. B. 2013; 22:068401:1-6. [13] Sodhi A., Gandhi G. Circuit mimicking T iO2 memristor: A plug and play kit to understand the fourth passive element. Int. J. Bifurcation Chaos. 2010; 20:2537-2545. [14] Kim H., Sah M.P., Yang C., Cho S., Chua L.O. Memristor Emulator for Memristor Circuit Applications. IEEE Trans. Circuits Syst. I, Reg. Papers. 2012; 59:2422-2431. [15] Kvatinsky S., Friedman E.G., Kolodny A., Weiser U.C. The desired memristor for circuit designers. IEEE Circuits and Syst. Magazine. 2013; 13:17-22. [16] Shin S., Zheng L., Weickhardt G., Cho S., Kang S-M. Compact circuit model and hardware emulation for floating memristor devices. IEEE Circuits and Syst. Magazine. 2013; 13:42-55. [17] Elwakil A.S., Fouda M.E. Radwan A.G. A Simple Model of Double-Loop Hysteresis Behavior in Memristive Elements. IEEE Trans. Circuits Syst. II, Exp. Briefs. 2013; 60:487-491.

23

[18] Yesil A., Babacan Y., Kacar F. A New DDCC Based Memristor Emulator Circuit and Its Applications. Microelectronics Journals. 2014; 45:282287. [19] S´anchez-L´opez C., Mendoza-L´opez J., Carrasco-Aguilar M.A., Mu˜ nizMontero C. A Floating Analog Memristor Emulator Circuit. IEEE Trans. Circuits Syst. II, Exp. Briefs. 2014; 61:309-313. [20] Abuelma’atti M.T., Khalifa Z.J. A New Memristor Emulator and Its Application in Digital Modulation. Analog Integr. Circuits Signal Process. 2014; 80:577-584. [21] Sah M.P., Yang C., Kim H., Muthuswamy B., Jevtic J., Chua L. A Generic Model of Memristors with Parasitic Components. IEEE Trans. Circuits Syst. I, Reg. Papers. 2015; 62:891-898. [22] Yang C., Choi H., Park S., Sah M.P., Kim H., Chua L.O. A Memristor Emulator as a Replacement of a Real Memristor. Semicond. Sci. Technol. 2015; 30: 015007. [23] Abuelma’atti M.T., Khalifa Z.J. A Continuous-Level Memristor Emulator and Its Application in a Multivibrator Circuit. Int. J. Electron. Commun. 2015; 69:771-775. [24] S´anchez-L´opez C., Carrasco-Aguilar M.A., Mu˜ niz-Montero C. A 16 Hz160 kHz memristor emulator circuit. Int. J. Electron Commun. 2015; 61;1208-1219. [25] S´anchez-L´opez C., Fern´andez F.V., Tlelo-Cuautle E., Tan X-D. Pathological Element-Based Active Device Models and Their Application to Symbolic Analysis. IEEE Trans. Circuits Syst. I, Reg. Papers. 2011; 58:1382-1395. [26] S´anchez-L´opez C. Pathological Equivalents of Fully-Differential Active Devices for Symbolic Nodal Analysis. IEEE Trans. Circuits Syst. I, Reg. Papers. 2013; 60:603-615. [27] S´anchez-L´opez C., Ruiz-Pastor A., Ochoa-Montiel R., Carrasco-Aguilar M.A. Symbolic Nodal Analysis of Analog Circuits with Modern Multiport Functional Blocks. Radio Engineering. 2013; 22:518-525. 24

[28] www.bioinspired.net [29] Sah M.P., Yang C., Kim H., Chua L.O. A Voltage Mode Memristor Bridge Synaptic Circuit with Memristor Emulators. Sensors. 2012; 12:3587-3604. [30] Fouda M.E., Elwakil A.S., Radwan A.G. Pinched hysteresis with inversememristor frequency characteristics in some nonlinear circuit elements. Micro. J. 2015; 46:834-838. [31] Pershin Y.V., Di Ventra M. Memristive circuits simulate memcapacitors and meminductors. Electron. Letters. 2010; 46:517-518. [32] Adamatzky A., Chua L. Memristor Networks. Springer International Publishing Switzerland 2014. [33] Biolek D., Biolek Z., Biolkova V. Pinched hysteresis loops of ideal memristors, memcapacitors and meminductors must be self-crossing. Electron. Letters. 2011; 47:1385-1387. [34] Biolek Z., Biolek D., Biolkova V. Computation of the area of memristor pinched hysteresis loop. IEEE Trans. Circuits Syst. II: Express Briefs. 2012; 59:607-611. [35] Biolek D., Biolek Z., Biolkova V., Kolka Z. Some fingerprints of ideal memristors. Proc. IEEE Int. Symp. Circuits Syst. 2013; 1:201-204. [36] Adhikari S.P., Sah M.P., Kim H., Chua L.O. Three fingerprints of memristor. IEEE Trans. Circuits Syst. I: Reg. Papers. 2013; 60:3008-3021. [37] Sah M.P., Adhikari S.P., Kim H., Chua L.O. Fingerprints of a memristor. Proc. IEEE Int. Cell. Nano. Netw. App. 2014; 1:1-2. [38] Chua L.O. Chapter 2: If its pinched its a memristor. Memristors and Memristive Systems. Springer. 2014; 1:17-90. [39] Biolek Z., Biolek D., Biolkova V. Specification of one classical fingerprint of ideal memristor. Micro. J. 2015; 46:298-300. [40] Valov I., Linn E., Tappertzhofen S., Schmelzer S., Van den Hurk J., Lentz F., Waser R. Nanobatteries in redox-based resistive switches require extension of memristor theory. Nature Comm. 2013; 4:1-9. 25

[41] S´anchez-L´opez C., Carrasco-Aguilar M.A., Morales-L´opez F.E. Offset reduction on memristor emulator circuits. Proc. IEEE Int. Conf. Electron. Circuits Syst. 2015; 1:296-299. [42] Data Sheet AD844AN: www.analog.com. [43] Data Sheet AD633JN: www.analog.com. [44] S´anchez-L´opez C. A 1.7 MHz Chua’s Circuit Using VMs and CF+s. Rev. Mex. F´ıs. 2012; 58;86-93. [45] Ortega-Torres E., S´anchez-L´opez C., Mendoza-L´opez J. Frequency Behavior of Saturated Nonlinear Function Series Based on Op Amps. Rev. Mex. F´ıs. 2013; 59;504-510.

26