A bottom-up approach for System-On-Chip reliability

Microelectronics Reliability 51 (2011) 1425–1439

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Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel

A bottom-up approach for System-On-Chip reliability V. Huard ⇑, N. Ruiz, F. Cacho, E. Pion STMicroelectronics, Crolles2 Alliance, 850 rue Jean Monnet, 38926 Crolles, France

a r t i c l e

i n f o

Article history: Received 20 July 2011 Received in revised form 25 July 2011 Accepted 25 July 2011 Available online 10 August 2011

a b s t r a c t We demonstrate here for the first time that it is possible by a bottom-up approach to build transistor- and gate-level models with enough accuracy to allow direct comparison with experimental degradations at system-level. This work opens new ways to optimize high level digital systems with respect to aging with great accuracy. Ó 2011 Elsevier Ltd. All rights reserved.

1. Introduction The existence of silicon dioxide plays a key role in the everlasting Si-based semiconductor industry. Since the mid eighty’s, the continuous scaling down of the dielectric thickness reaches dimensions in actual nodes close to atomic level (a 1.5 nm-thick dielectric is only 5 atoms-thick). In addition, at Si/SiO2 interface, both the electronic and structural properties are changed. As a result, Silicon Dangling Bond (SDB) defects are intrinsically present resulting in electrically active interface traps (Nit), also called Pb centers [1]. In order to minimize the effect of the electrically active states due to SDB-type defects, silicon devices are exposed to hydrogen through thermal annealing. The goal is that the H atoms will passivate these interfacial defects by forming Si–H bonds. Most of reliability degradation modes occurring in front-end part of the process are thought to be related to the dissociation of the Si– H bonds, like Negative Bias Temperature Instability (NBTI), Hot Carrier (HC) and Time-Dependent Dielectric Breakdown (TDDB) generally explained by hydrogen release at Si/SiO2 interface [2– 4]. Though all these degradation modes are related to the same initial SDB-type defect, many physical explanations have been proposed to explain the experimentally observed time-dependent hydrogen depassivation, ranging from direct electronic excitation, vibrational ladder climbing to diffusion-limited mechanisms. We have reported [5,6] a general framework to explain hydrogen depassivation at Si/SiO2 interface, based on the latest published results on Si–H bond local environment. This work explained several reported results in literature including both on NBTI and HC degradation modes in state-of-the art CMOS technology nodes. In such advanced nodes, reliability issues are becoming increasingly difficult to optimize at process level only due to diverse device offerings, complex products and overdrive requirements. Design-in Reliability (DiR) seeks to provide a quantitative assessment ⇑ Corresponding author. E-mail address: [email protected] (V. Huard). 0026-2714/$ - see front matter Ó 2011 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2011.07.086

of reliability – CMOS device reliability in this case – at design stage thereby enabling judicious margins to be taken beforehand. DiR methodology is the basic foundation for a bottom-up approach which aims to propagate upwards into the hierarchy of the design flow accurate information about the reliability physics. This methodology has been developed for designs in advanced nodes (starting at 90 nm) addressing the effects of both Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI). First, the modeling aspects of NBTI and HCI degradation modes will be thoroughly described. Subsequently, an implementation of an efficient and user-friendly reliability simulation engine inside the analog simulator ELDO is elaborated. This stage is the key enabler to propagate reliability informations in a useful format to designers. Implemented CMOS device reliability models can then be used to predict performance degradation of a wide class of digital IPs including standard-cells and SRAM libraries, as well as any analog IPs. Finally, we will present recent breakthrough results which demonstrate that it is now possible to start evaluating the reliability of a whole System-On-Chip (SOC) containing several billions of transistors. 2. Transistor-level reliability modeling A large set of NBTI and HCI experiments were conducted on various devices and oxide thicknesses present in advanced technology nodes (90 nm down to 32 nm) using different experimental methodologies from conventional Stress-Stop-Measure (SSM) to OnThe-Fly (OTF) methodology [7,8]. The degradation models will be described here below as well as the global approach (including required methodologies) to extract model parameters. The parameter chosen to represent the degradation forms the bridge between the physical degradation and the evolution of MOS parameter. The models are made linear with respect to time for being suitable for integration during circuit simulation. The boundaries of the integrals represent the window during which the stress assessment is made (during circuit simulation).

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2.1. Negative Bias Temperature Instability (NBTI) modeling Applying a careful look to all available NBTI data in literature, we have noted the following characteristics of NBTI degradation, which are common to all groups:  Conventional methodology loses some amount of degradation. In this context, either OTF or Fast methodologies are required to capture nearly all the degradation.  Recovery is present post NBTI stress.  There is some permanent damage – referred to as ‘lock-in’ damage [9] which cannot be recovered. This is the value of the degradation after long times of recovery. It is widely admitted that the threshold voltage Vth is the best monitor of NBTI degradation. As a consequence, Vth is taken as the degradation parameter. We have recently developed a new approach to model NBTI degradation [10,11] based on the coexistence of two components [12–14]:  A permanent part DDP which is related to Si–H bond breaking.  A recoverable part DDR which is most likely due to trapping/ detrapping of holes in the oxide. Over the time, we had gathered a large dataset of NBTI degradation on pMOS made of pure oxide (PO) SiO2, thermally nitrided oxide (TNO), plasma nitrided oxide (PNO) and high-k HfSiON stacks (HGK). Dielectric physical thicknesses are ranging from 1.3 nm to 12 nm. Electrical degradation is monitored by either using simple DC On-The-Fly (OTF) approach or in combination with relaxation sequences using a wide range of stress voltages (0.6 V to 2.2 V) and stress temperatures (25–200 °C). The recorded OTF degradation in IDlin was converted to DVth using the procedure described in [8].

As discussed and observed experimentally previously [7,10,15], the overall NBTI degradation is made of two macroscopic components. For short stress times (ts < 10s, depending on the gate stacks and stress conditions), the degradation is dominated by a recoverable component (DR) which is well described by a logarithmic time dependence (cf. Fig. 1 for typical example for two different gate stacks). The recovery phases can be described by the coexistence of the remaining part of the recoverable component DR as well as a roughly permanent contribution DP. The permanent part amplitude is solely impacted by the stress time and voltage [10,16]. The main question left today to solve out is whether or not these two components (DP and DR) are elements of the same microscopic mechanism, as suggested by [16], and so they are two tightly coupled components or quite differently they are strictly independent compo-nents, as suggested by [10]. This fundamental question can only be answered based on key experimental observations that we will briefly summarize before developing our model.

2.1.1. Degradation scalability The assumption of two tightly coupled components is based on the apparent broad scalability of the NBTI degradation in both stress and recovery phases for various stress voltages and temperatures [15]. This apparent scalability is observed even in our dataset when one component (here DR for instance) dominates over the other one. On the contrary, for conditions where both components are equivalent in importance, temperature and voltage scalability is no longer respected (Fig. 2 for temperature scalability (black symbols) and Fig. 3 for voltage scalability). This conclusion was reached for a broad range of gate stacks including SiO2, SiON, HfSiON gate stacks nature with electrical thicknesses ranging from 1.3 nm to 6.5 nm. Both components have different temperature and voltage acceleration factors which imply that two independent

5

SiON gate stack Normalized Vth degradation at 1s

HfSiON gate stack 4

Stress: 125°C Recovery: 125°C

3

2

2 weeks long recovery 1

Permanent part Dp 0 1.E-02 1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07

Use time (s) Fig. 1. NBTI degradation/recovery scaled at 1 s for 125 °C for both 1.7 nm SiON PNO (filled symbols) and 2.3 nm HfSiON (open symbols) gate stacks for 7 MV/cm vertical oxide field. Initial degradation phase (for ts < 10 s) is well reproduced by logarithmic time de-pendence (red line). Long recovery phases (up to two weeks, at 125 °C for one day, then 25 °C) had been conducted to evidence without ambiguity the permanent part DP contribution (in opposition with the fast recoverable part DR). (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.)

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2.1.2. Process dependence – hydrogen species Among all impurities, hydrogen is the most widely found in CMOS process. In a process viewpoint, hydrogen is an important impurity in due its ability to react with a wide variety of lattice imperfections. The passivation of dangling bonds present at the interface is an important step in improvement of transistor electrical parameters. Hydrogen has a stable isotope variant, the deuterium. Due to energetically similar valence band orbitals, deuterium and hydrogen atoms present similar binding energies on Si atoms. Nevertheless, SiD bonds are shown to be more resistant to hot-carrier stress than SiH bonds, the so-called isotope effect [17,18]. This effect is explained by the heavier mass of deuterium, making it more difficult to extract from interface, compared to the hydrogen atom [19]. Similarly to hot-carrier stress, deuterium was shown to reduce NBTI degradation [20]. Based on numerous hydrogen/deuterium splits, it was found that while the recoverable part DR remains identical independently of the anneal nature, the permanent part DP is reduced with deuterium anneal [11]. These results show that only the permanent part is related to any hydrogen species displacement at or close to the interface. The degradation reduction is proportional pffiffiffi to the square root of the deuterium/hydrogen mass ratio ð 2Þ, as expected for a diffusion phenomenon [21]. 2.1.3. Process dependence – nitrogen Many researchers already reported that increasing the nitrogen content into the oxide yields to a higher NBTI degradation [10,20]. The first step to understand the role of nitrogen incorporation is to compare NBTI degradation on pure oxide (i.e. no nitrogen) gate

Normalized degradation

4

HfSiON gate stack 3.2nm CET 125°C Oxide field increase

3

2

1

0 0.01

7MV/cm 6MV/cm 5MV/cm 0.1

SiON gate stack 1.7nm CET 6 MV/cm

1

10

100

1000

10000

Use time (s) Fig. 3. NBTI stress/recovery phases for 3.2 nm HfSiON gate stacks for various vertical oxide fields, scaled for 100 ms of stress. For short stress times, the voltage scalability is observed but for longer stress times, while the DP component starts getting importance, the voltage scalability cannot be longer observed.

stacks versus nitrided ones. It has been observed that the degradation increase is solely related to recoverable part DR enhancement while the permanent part DP is not impacted by nitrogen incorporation [11]. This apparent independence of the permanent part DP as a function of the nitrogen presence (either process-related incorporation and nitrogen dose) has been observed to demonstrate some ‘‘universal’’ behavior on a very broad gate stacks datasets (cf. Fig. 4). 2.1.4. Transistor NBTI degradation modeling As a consequence of these findings, the permanent part modeling is only stress time dependent.

Permanent part DP

5

4

5

Normalized degradation

microscopic mechanisms are at play in the overall degradation without any tight coupling. Though an advanced CMOS process route allows a large number of parameters to play with, only process splits which are known to have significant impact on NBTI degradation will be presented here to enlighten specific behaviors which would help to separate contributions of the different microscopic mechanisms.

DDP  K P V ag tbs

On the contrary, the recoverable part is stress duty dependent (i.e. dependent on both the stress and the recovery times). As shown above, this component is weakly temperature activated and strongly dependent on the nitrogen dose. Following the pioneer work of Tewksbury [22], it is possible to show that the recoverable part can be described by:

Temperature increase

3

  t s  se DDR  K R V cg ln 1 þ t r  sc

175°C

Recoverable part DR

125°C

where ts stands for ‘stress’ time and tr for ‘recovery’ time. In this case, ‘recovery’ means the time period when the gate voltage is lowered below the gate voltage of the previous activity phase. As a consequence, the global degradation (and recovery) is modeled by assuming a cumulative and independent contribution of both components in such a way that DD = DDP + DDR. Fig. 5 shows the good agreement of this approach to model both stress and recovery phases (black lines). Finally, the results of our quasi-static modeling approach are benchmarked with AC stress conditions which would be more representative of digital circuitry. First, we do confirm the lack of frequency dependence from 1 Hz up to 2 Ghz based both on ACstressed dummy inverter (i.e. within ring oscillator surrounding) and real ring oscillators. Fig. 6 shows both the absence of frequency dependence for experimental results but also the good agreement of the model. This result is true not only for one intra-cycle duty

2

1

0 0.01

75°C 25°C 0.1

1

10

100

1000

10000

Use time (s) Fig. 2. NBTI stress/recovery phases for 1.7 nm SiON PNO gate stacks for various stress temperatures ranging from 25–175 °C, scaled for 1 s of stress. For short stress times (red symbols), the DR component dominates over the DP one and an apparent temperature scalability is observed. For longer stress times, the DP component starts getting importance and the temperature scalability cannot be longer observed. (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.)

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9

10nm Pure 9nm Pure 8.5nm Pure 6.5nm PNO 5nm TNO 3.2nm Pure 2.1nm TNO 1.6nm PNO 2.3nm HfSiON 3.2nm HfSiON

8

Normalized degradation

7 6 5

DP ~ Eox4

4

125°C t stress =10ks

3 2 1 0 4

6

8

10

12

Oxide Field (MV/cm) Fig. 4. The independence of the permanent part DP generation with the nitrogen content and gate stack process is universally observed on different gate stacks: pure SiO2, SiON (thermally- or plasma-nitrided) and HfSiON gate stacks. All DP degradations were normalized to 6 MV/cm vertical oxide field. Dotted line represents the Eox4 dependence which fits correctly the overall broad dataset.

Threshold voltage shift

1.7nm PNO 125°C

RD model Composite model 1

10

100

1000

10000

100000

Stress time (s) Fig. 5. Composite NBTI (full line) and RD (dashed line) models benchmarked versus experiments for both stress and recovery phases.

factor but it is also the case for duty factor ranging from 100% (pure DC case) down to 0.1%.

2.2. Hot carrier injection (HCI) modeling Hot-Carrier Injection degradation presents a renewed interest in the more recent nodes where high level of device reliability is difficult to achieve at high temperature as a function of supply voltage VDD. This point is mainly explained by a continuous increase in lateral electric field since 120 nm node. Both digital and analog applications require HCI modeling of the whole Vgs/Vds design space described by devices either during transitions in between two logic levels or in analog mode. Recent experimental HCI analysis allowed separating the contributions of three independent modes. The first mode is related to carriers bringing individually enough energy to break the Si–H bond. The second mode is related to moderate carrier energy range where Electron–Electron Scattering plays a role to promote a single carrier to high energy and allow Si–H bond breaking [23]. Altogether, these two

modes can be considered as Channel Hot Carrier (CHC) modes since they are related to carrier energy. Finally, a third mode in low energy range was recently attributed for the first time without ambiguity to Multiple Vibrational Excitation (MVE) [24,25]. In this configuration, the degradation is lead mostly by the number of carriers ‘‘hitting’’ the bond and in a less important way by the acquired energy. This mode should be considered as Channel Cold Carrier (CCC) mode since the degradation is no longer related to carrier energy. This description in three modes allows modeling the HCI degradation in the whole Vgs/Vds design space (cf. Fig. 7). As a consequence, a full modeling of cold to hot carrier degradation is determined by device lifetime extraction (s) for all the stressing conditions by assuming that all three degradation modes P compete in parallel, which gives a general equation as 1s ¼ i s1i : s¼ K SVE 

1  a1  m  a2  m  a3   Ids emi  IIbs þ K EES  IWds  IIbs þ K MVE  V ads3 =2  IWds  exp E W kB T ds

ð1Þ

ds

where KSVE, KEES and KMVE are three constants determined in their respective dominant mode. We have validated this modeling for

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7

DC OTF 6

Ring oscillators

Dummy inverters

Frequency Cload Idsat nMOS

AC stress 125°C Vstress/0V 50% duty

Idsat degradation (a.u.)

5

Idsat pMOS 4

3

2

RD model Our model

1

0 1.E-04 DC 1.E-02

1.E+00

1.E+02

1.E+04

1.E+06

1.E+08

1.E+10

Frequency (Hz) Fig. 6. Frequency impact on Idsat shift during AC stress compared with model predictions (lines).

nMOS, 1.7nm, Vdd = 1.1V, 25°C Vds =

1.E+04

0.9V 1V 1.1V 1.21V 1.4V 1.6V 1.8V 2V

TTF

τ

(a.u.)

1.E+06

0.5/0.04
0

0.001

Age ¼

  a1  m  a2  m Ids Ibs Ids Ibs ¼ t  K SVE   þ K EES   s W Ids W Ids  a3   Ids Eemi  exp þK MVE  V ads3 =2  W kB T t

ð2Þ

The Age function allows merging degradations of the three modes on the same trend, confirming that the time dependence follows a power law with an exponent of 0.5 for all stressing conditions.

1.E+02

1.E+00

into MVE regime (mode 3), the activation energy is Eemi = 0.26 eV according to a large set of experimental data and previous results on H. Eq. (1) leads to the definition of an Age function:

0.002

Ids/W (A/µm) Fig. 7. HCI modeling (lines) at RT compared to experimental dataset covering the whole Vgs/Vds design space.

various gate-oxide thickness (Tox = 5 nm, 3.2 nm and 1.7 nm) under a large set of voltages conditions (Vgs, Vds), temperatures and device geometries (W/L), both on nMOS and pMOS. The complete modeling explains also the change in the damage behavior through the gate-length dependence (Fig. 8a) where at small Ids it originates from the Ids and Ibs gate-length dependence, while at higher Ids the lifetime becomes only dependent on Ids magnitude on not on L anymore. The influence of temperature is explained by the temperature dependence of each degradation modes Fig. 8b in ultra-thin gateoxides (1.7 nm) nMOS. Under EES corresponding to mode 2, temperature effect is included into the intrinsic temperature dependence of both currents Ids and Ibs (so Ibs/Ids) while entering

2.3. Degradation mapping to compact models A lot of research works over the past decade had allowed reaching a better understanding of the various degradation mechanisms at the origin of defects creation in a transistor. Complementary works have correlated this defect creation with the electrical impact on transistor performances. Based on this solid background, it remains to translate all these dataset in a way to provide a quantitative assessment of reliability – CMOS device reliability in this case – at design stage thereby enabling judicious margins to be taken beforehand. ELDO simulator has been enhanced to communicate with a proprietary Application Programming Interface named UDRM (Fig. 9), in which two set of equations/parameters are encoded. The first set named ‘Defect creation’ is related to stress models which aim to calculate the number of defects generated by the stimuli coming from the simulation. This set of equations is generally based on quasi-static modeling of both NBTI and HCI degradations (Fig. 9),

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(a)

(b)

Fig. 8. (a) Comparison between the complete modeling (lines) and the experimental data of Fig. 10 (symbols) showing a clear change in the gate-length dependence between mode 2 (EES) and mode 3 (MVE). (b) Comparison between experimental data of Fig. 13 and the complete modeling obtained for three temperatures in L = 40 nm nMOS with Tox = 1.7 nm.

Simulator

Netlist Fresh

Nominal

Model

OTF

Comparison

Aging

analysis

Update

Aged

Aged

Statistical Reliability Module User Defined Reliability model Defects SPICE UDRM impact creation Fig. 9. Schematics of the reliability simulation flow. Standard BSIM and PSP equations are equally understood.

The second set named ‘SPICE impact’ is related to the translation of the generated defects into SPICE parameters variations which finally turn into device performances degradation. 3. Circuit-level reliability modeling Design-in-Reliability (DiR) methodology has become a soughtafter capability for the current generation technologies. We will demonstrate here the powerful abilities of a practical DiR methodology in providing quantitative reliability assessment for CMOS designs by taking into account both HCI and NBTI degradation modes at circuit level, i.e. for designs up to 1 million transistors. 3.1. Digital circuits modeling In this first part, we will focus on the reliability modeling of the most basics elements of any digital circuits, the standard cells. 3.1.1. Silicon validation of CMOS device level reliability models At this point of the discussion, our device level models have been validated on single isolated devices using quasi static experimental results. It is thus important to examine the silicon validation of these reliability models in a context closer to real product

device use. In this viewpoint, High Temperature Operating Life tests (HTOL) have been led on testchip vehicles incorporating standard cells-based critical paths, used here as testcase. HTOL experiments consist on several stresses at different supply voltages ranging from 20% to 50% overhead compared to nominal supply voltage. The experimental frequency degradations have been monitored at various readpoints (up to 1000 h). The resulting drifts can be directly compared to reliability simulations run on the structure netlists including all parasitics. Correlation plot between simulated and experimental frequency degradations shows a 1:1 correlation (cf. Figs. 10 and 11), showing the accuracy of our modeling approach as well as validating our simulation flow. It is worth noticing that HCI is no longer negligible compared to NBTI due to constant lateral electric field increase in advanced nodes (cf. Fig. 12). Four main conclusions are arising from this analysis. First, our reliability modeling is very accurate in reproducing experimental frequency drifts which allows considering transistor-level model results as silicon results in the rest of the paper. The second conclusion is that NBTI RD model is pessimistic due to inaccurate recovery dynamics modeling. The third conclusion is that HCI degradation is no longer negligible in advanced modes. And the fourth conclusion is that various standard cells present very

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1.6

45nm logic gate - NBTI pMOS - HCI nMOS

HCI nMOS NBTI pMOS

1.4

1:1 correlation

Frequency degradation (a.u.)

CAD frequency degradation (a.u.)

V. Huard et al. / Microelectronics Reliability 51 (2011) 1425–1439

125C RP up to 1000hrs Different Vsupply

1.2

Vdd_1

Vdd_2 > Vdd_1

1 0.8 0.6 0.4 0.2 0

Silicon frequency degradation (a.u.)

IVX_V1 Fig. 10. At-Speed HTOL access time degradation can be explained by combining NBTI and HCI aging simulations while NBTI only simulations are needed for 100 kHz HTOL tests. It is worth noticing the good 1:1 correlation between silicon results and aging simulations on complex critical paths.

different response to reliability stimuli, i.e. they present different sensitivities.

3.1.2. Application to digital design flow One of the needs in the case of the digital circuits is to propagate the timings upwards into the design hierarchy, where reliability issues can be treated as a yet another verification corner [26], using the timings originate from the characterization of standard cells. The various timing arcs in a logic gate as a function of loading, input slopes, supply, temperature corners are characterized by simulation for each of the gates. The degradation was characterized for the var-

3

IVX_V2

ND2_A

ND2_B

NR2_A

NR2_B

Fig. 12. Relative strengths of NBTI and HCI in some standard cells for two supply voltages. Input B relates to the closest input pin to output.

ious timing arcs for a 700 cell core (LP 90 nm 2 nm gate oxide) transistor-based library operating at 1.1 V. In this case, the HCI degradation was evaluated to have negligible impact and only the NBTI impact was characterized. Fig. 13 shows the distribution of the degradation of the various timing arcs, which formed a new corner for timing assessment at the gate level. The negative timings are not a surprise as it results in situations where NMOS has to pull down a node balanced by a PMOS weakened by NBTI. Tests on calibration critical paths brought up 3–5% additional timing margin requirements. This is an example of pragmatic large scale deployment of reliability simulations. The main drawback of this approach is that the additional reliability-related corner is valid for one single

Composite model CAD values Experimental Drift values RD model CAD values

2.5

Frequency Drift (a.u.)

125C - 168 hrs

2

1.5

1

0.5

01 03 05 07 09 11 13 15 17 19 01 03 05 07 09 11 13 15 17 19 21 01 03 05 07 09 11 13 15 17 19 21 23 25 27 29 31 33 01 03 05 07 09 11 13 15 17 19 21 23 25 27 29 31 33 01 03 05 07 09 11 13 15 17 19 21 23 25 27 29 31 33 01 03 05 07 09 11 13 15 17 19 21 23 25 27 29 31 33

0 Set 1

Set 2

Set 3

Set 4

Set 5

Set 6

Fig. 11. Frequency drifts from 200+ standard cells-based ring oscillators separated in various sets measured on silicon (open symbols) on four lots (average shown) are well reproduced by our reliability modeling simulations (full lines) while NBTI RD model simulations (dashed lines) predict values 40% higher than observed silicon results.

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Fig. 13. Distribution of delay (timing arcs) changes due to NBTI stress in different cells in a 700 cell core library. ‘‘delay_cell’’ refers to the time from 50% input to 50% output for two categories of ‘‘rise’’ and ‘‘fall’’ outputs. ‘‘rising edge’’ refers to the output time to change from 10% to 90%.

mission profile, i.e. a single set of stress conditions including stress voltage and power-on time (POT), defined as the time related to product activity in the field. Providing a new corner for another set of parameters would require a new cell core library characterization, which would prove to be burdensome.

ready quite large with respect to circuit usage), our gate-level model is accurate within 0.1%. We considered this level of accuracy satisfactory to yield accurate timing analysis at system level.

3.2. Sram library reliability modeling 3.1.3. Gate-level reliability modeling We propose a new framework to propagate the timing degradations upwards into the design hierarchy while considering every single product mission profile by the use of a 3-parameters simplified model:

dt=t ¼ S  ðPOTÞn

ð3Þ

The first parameter is the gate sensitivity S, which depends mostly on factors such as input slope and/or load capacitance (design inputs). The second parameter is the power-on time (POT) which is the equivalent stress time with respect to the product mission profile and the nominal voltage. The third parameter is the time exponent n, assuming power law time dependence for the delay degradation. An in-depth analysis of a large number of 45 nm standard cells (hundreds of cells here) shows that, though both S and n might be timing arc-dependent, practically only the sensitivity parameter S presents a strong dependence with respect to the timing arcs [27] (cf. Fig. 14). To conclude, our gate-level model is based on power law time dependence of the delay degradation with a single time exponent n, independently of the design inputs. On another hand, the gate sensitivity to the degradation is modeled through the parameter S, which is strongly dependent to the design inputs and the nature of standard cell under consideration. Consequently, all standardcells in the core library must be characterized with respect to their sensitivity to the degradation. Fig. 15, presents the comparison between the predictions of our gate-level model with respect to the reference transistor-level mode. An absolute worst-case mission profile of 20 years at 125 °C was assumed in other to maximize potential discrepancies. This analysis shows that our gate-level model, though simplified, is very accurate to reproduce delay degradations with a margin of error of 1% of the total degradation. For example, if the mean delay degradation is 10% (which is al-

In this second part, we will focus on Static Random Access Memories (SRAMs) which are present nowadays in all CMOS products in large quantities. Besides, they are often very challenging both on process side (due to small dimensions) and on design side (due to performance request). As a consequence, managing their reliability is of prime importance, though it is quite complex due to their overall complexity. This part demonstrates a full reliability-based design flow for SRAM libraries. A SRAM library is typically divided in four main blocks as shown in Fig. 16 [28]. The operation in the clock cycle is computed in the control block. When a read or a write cycle is performed, the address is chosen by the decoder block before selecting the right word inside the memory array. In parallel, the input/output block is either collecting the data from the memory array for a read cycle, or collecting from outside of the memory the data which will be saved in the memory array for a write cycle. In order to reach the highest level of performance specific design techniques are implemented in SRAM libraries: dynamic logic for control and decoder, sense-amplifiers for reading the data in the bit-cell. However, this strategy yields the generation of enabling signals like internal clock circuitry which mimics the longest timing path. SRAM libraries are facing two main reliability challenges: the functionality must be maintained down to minimum supply voltage VMIN in spite of reliability drifts and the speed performance drift mostly driven by the control logic must be accurately characterized so that adequate timing characterizations are provided upwards into the design flow.

3.2.1. SRAM functionality modeling Though dedicated access to both control logic and SRAM arrays, we have first checked that the yield loss is solely controlled by the SRAM bitcell array (cf. Fig. 17).

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1800 Sensitivity parameter S Time exponent n

1600 1400

Frequency

1200 1000 800 600 400 200 0 0.0

0.1

0.2

0.4

0.3

0.5

0.6

0.7

Sensitivity and time exponent values Fig. 14. Sensitivity S and time exponent n dependencies on a large number of timing arcs (>10 k), showing that time exponent can be simplified to a single value (0.24 in this case) while it is needed to accurately describe the sensitivity parameter S dependence with respect to design timing arcs inputs.

Gate-level degradation

16 14

Percent

12

Mean StDev

0.9894 0.01351

10% degradation

10

Gate-Level model 0.1% error

8 6 4 2 0 0.90

0.95

1.00

Transistor-level dela

1.05

1.10

y de gradation

Fig. 15. Transistor-level delay degradation normalized with respect to gate-level model delay degradation predictions for 20 years mission profile (absolute worst case for high-reliability applications). Gate-level model is always slightly pessimistic with respect to transistor-level model by about 1% of the degradation. As an example, it means that if silicon mean degradation is 10%, our gate-level model is accurate within 0.1%.

Decoder Control

Control block

Memory array

Memory point

Sense Control Clock Control signals

Memory point

Memory point

decoder

Internal clock circuitry

Sense-Amp

Q<0>

Memory point

Input/Output

Sense-Amp

Q

Fig. 16. SRAM library schematics including wrapped control logic.

On another hand, in a recent study, we had set a new methodology to model the minimum supply voltage VMIN of any SRAM

bitcell array [28]. This methodology relies on modeling separately the bitcell failure probabilities related to either read failures or write failures. Since a bitcell has either a read (Fbit_read) or a write (Fbit_write) failure, the two failure probabilities are independent and can be straightforwardly added. The resulting Fbit is the expected total bitcell failure probability as a function of the supply voltage (also seen as the number of faulty cells). By combining this approach with our reliability modeling tools, simulations can be run to predict the evolution of the number of faulty cells during the operating life of SRAM arrays. This electrical simulation approach can be shown to be efficient to reproduce several stress times (cf. Fig. 18), providing confidence that our statistical reliability simulation setup is robust enough to reproduce SRAM arrays behaviors. By simulating the bitcell failure probability, this approach allows also being independent of the SRAM array size and thus can accurately reproduce experimental results even for large, product-sized SRAM arrays [28]. This approach was also demonstrated to be robust while simulating process corner impact versus aging. Fig. 19 shows median

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3

Control logic SRAM array

2 1

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0 -1 -2 -3

Minimum voltage (a.u.) Fig. 17. VMIN library is controlled by VMIN array solely. NBTI impacts differently the array (small change when bitcells are centered), while control logic is monotonously increased.

VMIN values for large arrays (several Mbytes) as simulated using our procedure described above and compared to silicon results. 3.2.2. SRAM timing performance reliability modeling SRAM library timing performances are not only related to bitcell properties (like Icell) but also to the whole SRAM IP including the control logic. We first wanted to be able to evaluate accurately which parts of the critical path are responsible for most of the degradation within the IP. For that purpose, reliability electrical simulations were performed on several SRAM libraries using our inhouse reliability modeling solution described above. In parallel, dedicated test vehicles are built in order to cross-check simulation results with silicon results. These test vehicles embarked specific structures which allow at-speed tests. Two kind of analysis were performed. First, an automated timing monitor embarked on sili-

con allows performing accurate timing characterization. Though useful, this timing monitor does not provide information on which parts of the critical path are most impacted by transistor aging parameters drift. Another possibility is to proceed to ebeam analysis on a statistically relevant set of test vehicles prior to and after the electrical stress. This ebeam analysis has been done on dedicated pads connected to inner nets at the interfaces of main blocks in order to perform correlations at block level, showing excellent silicon to CAD correlation in the prediction of SRAM critical path aging [28]. It is worth pointing out that the overall contribution of the bitcell speed is negligible and the whole performance degradation is driven by the control logic timing path. One of the main conclusions we obtained from reliability simulations at that point is that both NBTI and HCI are contributors of the timing path degradation. This result can be efficiently demonstrated by silicon measurements. Two sets of electrical stresses on identical SRAM IPs were done. The first set was dedicated electrical stresses using external clock at slower frequency (100 kHz). In this configuration, we expect the HCI contribution to be negligible due to its strong frequency dependence, while NBTI degradation should dominate due to its frequency independence (cf. Fig. 6). On another hand, a second set of electrical stresses were performed at-speed to trigger not only NBTI but also HCI degradation. Fig. 20 shows that though low-frequency results are well explained by NBTI-only reliability simulations, it is not the case for at-speed tests where HCI degradation needs to be taken into account to explain the whole degradation. This part studied the role of the different blocks composing a SRAM library as found in a product. At front-end side, the good accuracy of aging simulations versus silicon results allows on one side predicting the yield (or VMIN) of the SRAM bitcells array and on another hand optimizing the control logic design without

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3.3.1. Current mirror Though our reliability modeling tool offers the possibility to simulate the recovery of NBTI degradation, this is quite a new concept within reliability simulations. Fig. 21 shows the simulation of NBTI recovery during low bias operation of simple resistor-based current mirror. NBTI degradation occurred during high bias operation on both transistors M1 and M2. Subsequently, when the voltage is lowered, recovery sets in and some of the damage is recovered [29,30]. Nevertheless, a correct assessment of recovery dynamics is important since issues could arise from the lower than expected worst-case current, in particular for short time right after the stress. This could ultimately lead to initialization related malfunctions.

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Process corner Fig. 19. Simulations (CAD) and experimental results (SIL) of normalized VMIN values for large arrays of 45 nm HD bitcell both for non-stressed SRAM test vehicles (0 year) and after HTOL stress (HTOL) as a function of process corners. Some corners are showing degradation while some others are showing improvement. In all cases, our simulation setup can reproduce quantitatively the observed evolutions.

the cost of additional silicon verifications. At back-end side, a full automated flow was developed for the designers. This was made possible by the close collaboration between reliability experts, SRAM designers, and TCAD experts in partnership with the vendor (details to be found in [28]). Overall, we have evidenced in this study all the elements needed in order to insure adequate reliability-performance trade-off for customers in the SRAM libraries commonly found in all products.

3.3.2. Voltage-Controlled Oscillator (VCO) in a Phase-Locked Loop (PLL) Another example is a phase frequency detector which is typically the input block in a Phase-Locked Loop (PLL) which compares the incoming and generated low frequency clock and generates correction signals to set the output frequency to the charge pump. Any drift in this block induced by aging phenomena would directly result in drift of the output frequency, meaning that a jitter would be introduced. In-depth study of the impact of NBTI recovery on this block [29,30] shows that, apart from the initial abrupt recovery, small and gradual changes such as due to degradation and recovery effects act like low frequency signals which can be corrected by the PLL loop. 3.3.3. Two-stage operational amplifier For such analog custom blocks, the flexibility of the tool with respect to different types of analysis plays a crucial role. A two-stage operational amplifier (opamp) with a PMOS differential input is

3.3. Analog/RF circuits modeling

CAD access time degradation (a.u.)

In this third part, we will focus on how the DiR methodology applies to some representative analog/RF blocks.

1:1 correlation

HTOL At-Speed test -- NBTI-HCI ageing simulations HTOL 100KHz test -- NBTI ageing simulations

Silicon access time degradation (a.u.) Fig. 20. At-Speed HTOL access time degradation can be explained by combining NBTI and HCI aging simulations while NBTI only simulations are needed for 100 kHz HTOL tests. It is worth noticing the good 1:1 correlation between silicon results and aging simulations on complex critical paths.

Fig. 21. Effect of NBTI recovery in a simple current reference.

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stressed with asymmetric input voltages for a given operating conditions and extrapolation time. In this case, the degradation is mainly due to NBTI (long length devices are used for mismatch control, thus HCI can be neglected). The DC operating point calculation shows an input offset, which is approximately equal to the threshold shift of the MOS under stress. A transient simulation of this opamp as a voltage follower highlights this input offset. AC analysis shows that if this offset is taken into account, the open loop gain, its gain and phase margins do not alter much [29,30]. It is worth noticing that NMOS devices in analog circuits could be susceptible to HCI if their lengths are not long enough.

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3.3.4. Very high frequency RF blocks (60–80 GHz) Recent CMOS technologies are enabling integration of very high frequency applications like HDMI, WLAN or WPAN communications in the range of 60 GHz. Such AMS/RF applications present voltage transitions much faster than the conventional quasi-static experiments used to build up Hot Carrier models. Until now, it remains a challenge to demonstrate that a given HCI modeling approach might yield to accurate predictions in such aggressive contexts. Based on STMicroelectronics 65 nm process capability, we have designed a dedicated test structure to embed a single nMOS in common source configuration into a network of passive elements to adapt to 50 ohms external impedances at 60 GHz. This test structure acts like a millimeter wave one stage power amplifier (PA) with state-of-the-art specifications [32,33]. This test structure opens the way to realize both DC and RF (60 GHz) stresses on the same transistor so to validate the two steps approach of HCI modeling in a regime favoring non quasi static behaviors. Both DC methodologies using I–V curves and both small-signal and largesignal RF parameters are monitored among which the power gain, the input and output matching (S11 and S22), the output saturated power (Psat) and the output 1 dB compression point (OCP1 dB). The transistor is degraded by applying accelerated stress conditions on gate and drain voltage pads in a very similar way than product operating lifetests. As a first step, only a DC stress was applied in a way very similar to conventional Wafer Level Reliability. We wanted to check the accuracy of the set of equations related to SPICE parameters variations to reproduce RF parameters drift under DC stress. This approach allows referring to DC stress which are similar to our quasi-static approach modeling approach and only focus on validating our SPICE parameters strategy. Reliability SPICE simulations were run to reproduce all experimental set of conditions. Fig. 22 shows one example of good agreement between reliability modeling and experimental results for small-signal parameters. Similarly, large-signal measurements can also be modeled using our reliability tool. Once again, it is found that our reliability predictions are very well aligned with silicon measurements, in spite of the fact that measurements are led into millimeter wave domain (60 GHz). This first step of validation allows concluding that, for a HCI DC stress, our reliability SPICE simulation tool provides predictions well aligned to silicon for characteristics as different as DC ones (I–V curves), small-signal parameters (S parameters) and large-signal parameters (like ouput power). Overall, we can conclude at this point that the set of equations related to SPICE parameters impact is adequate for a large range of signals. The last step is related to the validation of quasi-static stress models (i.e. related to the equations driving defect generation) up to 60 GHz input frequency. RF stresses are applied by setting the input frequency to 60 GHz so to insure that most of input RF power is transferred to the transistor with minimum attenuation. Two input RF powers have been used as stress conditions: 0 dBm (corresponding to OCP1 dB) and 10 dBm.

Fig. 22. Comparison between measured and simulated 1 stage PA gain S21 as a function of stress time for HCI DC stress.

Similarly to the case of DC stress, we had also compared the results of our reliability simulations to small-signal and large-signal (Fig. 23) parameters drifts. Once again, very good agreement is achieved for various parameters, stress times and stress conditions. Overall, we have demonstrated that the quasi-static approach used to generate HCI reliability simulations is suitable to reproduce electrical aging phenomena up to 60 GHz. These important results were mandatory to demonstrate that AMS/RF applications can be supported by our reliability simulations but also High-Speed digital designs with fast transitions in range of tens of picoseconds. Finally, similar RF stress experiments have been led on a more realistic (on a product sense) four stages Power Amplifier (PA) [32,33], designed to work at 60 GHz with state-of-the-art performances. Similarly to simpler 1-stage testcase, reliability simulations are well aligned to silicon measurements prior and after both DC and RF stress conditions. We have demonstrated that the quasi-static approach used to generate HCI reliability simulations is suitable to reproduce electrical aging phenomena up to 60 GHz using both simple 1-stage PA testcase and a more realistic, state-of-the-art 4-stages PA. These important results were mandatory to demonstrate that AMS/RF applications can be supported by our reliability simulations but also High-Speed digital designs with fast transitions in range of tens of picoseconds. 3.4. Circuit reliability conclusions Overall, we have demonstrated over the past years of research that the reliability modeling module we have developed is flexible and accurate enough to reproduce all the most relevant circuit configurations that can be encountered in a real System-On-Chip (SOC). The main limitation of this transistor-level approach is the limited number of transistors that can be evaluated at the same time (typically lower than 1 million) when typical SOC are 10 OCP1dB = 6.5 dBm

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Fig. 24. Top circuit and LDPC decoder micro architecture.

containing several billions of instances. Overwhelming this limitation needs to lots of research work to reach an additional hierarchical level of description. 4. System-level reliability modeling Though this domain of research remains largely uncovered, few promising perspectives have been given recently for digital designs [27]. This work relies on the Gate-level reliability modeling approach described here above. In practice, it is rather easy to

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simplify the perspectives at gate level from a simulation (CAD) perspective. But, as far as our knowledge, gate-level reliability modeling approach has never been confronted to silicon reliability results obtained on fully implemented Systems-On-Chip (SOCs). For that purpose, a Low-Density Parity-Check (LDPC) codec circuit was carried out in a 45 nm Low-Power bulk technology. This LDPC codec supports the 12 modes required by the 802.11n standard (Wifi): 4 code rates (1/2, 2/3, 3/4, 5/6) over 3 possible block sizes (648, 1296 and 1944 bits). This IP was implemented on silicon using conventional 45 nm Low-Power design platform,

F max degradation inline with mean critical paths behavior

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Normalized delay degradation (a.u.) Fig. 26. Histograms of delay degradations of LDPC IP based on both composite model (black histogram) and on the RD model (red histogram) are shown with respect to the setup violations for a given stress conditions. For sake of comparison, the delay degradation is normalized to experimental Fmax degradation at 1. The RD model approach provides 40% additional margin in average with respect to experimental degradations thus directly impacting the design performance. Another approach is to apply arbitrary timing derate margin which should be defined as the worst-case critical path for the sake of pessimism. This approach provides 25% additional margin in this case.

introducing dedicated BIST features to allow at-speed testing during High-Temperature Operating Lifetests (HTOL) experiments. The top circuit and the LDPC decoder micro architecture are presented in Fig. 24. This IP was exercised with different stress conditions (10 conditions in total) including different stress voltages, stress time (up to 1000 h) and different stress temperatures for a total of 1200 parts tested. The different stress conditions were translated into different Power-On Time (POT). Static Timing Analysis of the LDPC IP was run using our reliability models fed by the POT values. Fig. 25 shows the histogram of the delay degradation. It was calculated using our gate-level model for the 60,000 more critical DATA paths with respect to setup violations (slowest paths). For the sake of

comparison, we also include the experimental Fmax degradation data (vertical lines), this measure is also linked to the most critical path with respect to setup violations. The observed Fmax degradation is very well aligned with the mean delay degradation of the whole critical path population under consideration. This approach provides for the first time an accurate way to predict product macroscopic feature (such as Fmax) degradation. It is also interesting here to compare various approaches to deal with reliability-induced delay degradation (cf. Fig. 26). The first approach is our gate-level model based on composite model (black histogram). As we can see in Figs. 25 and 26, it is intimately correlated with the macroscopic experimental Fmax degradation. The second approach is a gate-level model based on RD diffusion

Fig. 27. Correlation plot between the mean delay degradation of critical paths (y-axis) for both composite model (squares) and RD model (circles) with respect to experimental mean Fmax degradation. Our composite model approach demonstrates a 1:1 correlation for 10 stress conditions with a maximum 2% error of the amount of degradation (10% degradation will be known at 0.2%).

V. Huard et al. / Microelectronics Reliability 51 (2011) 1425–1439

(shown here as red histogram) which similarly to gate-level analysis demonstrates on average a 40% penalty with respect to the degradation. For example, if we have an average degradation of 10%, the predictive value of RD model would reach an average of 14%. The third approach was calculated using a timing derate margins at sign-off level. In order to stay pessimistic in absence of any knowledge about any critical path sensitivity with respect to the degradation, it should be considered the worst-case critical path delay degradation. In the specific case of Fig. 26, it means that this approach would bring an additional 25% margin. For example, it means that for an average degradation of 10%, the timing derate margin approach would predict on average a degradation of 12.5%. Fig. 27 summarizes the mean delay degradation for the 10 stress conditions considered here for both the composite model (squares) and the RD model (circles) as a function of the experimental mean Fmax degradation. The predictions of the composite model are 1:1 correlated with the experimental observations. The maximum margin of error is 2% at system level (10% mean degradation is known with 0.2% absolute error). In this work, we provided details on how DiR methodology is deployed hierarchically up to digital system level in advanced nodes addressing the effects of Negative Bias Temperature Instability (NBTI). We demonstrate here for the first time that it is possible by a bottom-up approach to build transistor- and gate-level models with sufficient accuracy to allow direct comparison with experimental degradations at system-level. This work opens new ways to optimize high level digital systems with respect to aging with great accuracy. 5. Conclusions DiR methodology has become a sought-after capability for the current generation technologies. We have described the development and demonstrated the powerful abilities of a practical DiR methodology in providing quantitative reliability assessment for CMOS designs by taking into account both HCI and NBTI degradation. It was demonstrated the importance of flexible tools so to introduce new items such as NBTI recovery, which plays a crucial role in most of digital and analog circuits. On top of that, we have evidenced that our approach can be used as solid foundations to

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start propagating reliability informations to system hierarchical level. It creates the unique opportunity to achieve a predictive reliability modeling to complex System-On-Chips containing billions of instance. References [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [32] [33]

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