A compact time digitizer in camac format

NUCLEAR

INSTRUMENTS

AND

METHODS

[38 (1976) 685-689;

©

NORTH-HOLLAND

PUBLISHING

CO.

A COMPACT TIME DIGITIZER IN CAMAC FORMAT* DIETRICH FREYTAG Stanford Lmear Accelerator Center, Stanford Unwerstty, Stanford, CA 94305, U S A

Received 26 April 1976 and m revised form 9 August 1976 A compact time dlgltlzer containing 128 words of 16 bits each on a single width CAMAC module Is described Eight data channels are prowded w~th a capacity of 16 words each. The umt has been used with a 50 MHz clock to encode data from magnetostrlctwe spark chambers and - w~th modifications - for the accumulatton of data from multlwlre propomonal chambers

1. Introduction A frequently encountered p r o b l e m in the electronic processing of mformatxon is the m e a s u r e m e n t and recording of the time separation of a sequence of electrical signals For example, in processing the l n f o r m a U o n from a large assembly of magnetostrlctwe spark chambers, as m a n y as 1000 I n d e p e n d e n t measurements of this type may have to be made for a single event R a n d o m access m e m o r y elements ( R A M ) offer great economical advantages for storage of such large q u a n t m e s of data However, it is often desirable to have better time resolution t h a n can be obtained directly from the standard device The goal of improved time resolution has been achieved m the present design by effectlng an intermediate storage of two low order bits m a fast m e m o r y with subsequent transfer of the complete Information to the R A M m synchronism with higher order clock bits (see block diagram, fig 1) The h m e resoluhon of the i n s t r u m e n t is 20 ns, but 10 ns can be achieved with only m i n o r modifications of the design It should be noted that the digitizer takes the timing i n f o r m a t i o n from the leading edge of the data pulse However, signals from magnetostrlctive chambers require timing of the centrold of the pulse for o p t i m u m resoluhon Since a digital d e t e r m i n a t i o n of the centrold would be quite impractical for the method of encoding used here, a preprocessmg of the signals, e g , through analogue center-finding circuitry, is necessary A further a p p h c a t l o n for the digitizer is the encoding of reformation from p r o p o r t i o n a l wire chambers (PWC) In this case the original i n f o r m a t i o n is contamed as a hit pattern in a long shift register which is then read out serially The dlgmzer performs the address e n c o d i n g of the true bits and, since the shift* Work supported by the Energy Research and Development Administration and the National Science Foundahon

clock frequency can be matched to the time resolution of the R A M , there is no need for intermediate storage of low order btts

2. Summary of data processing Prior to the arrival of the data pulses, the time separation of which is to be determined, most of the digitizer circuitry is without power A clear pulse provided on a bussed C A M A C patch pin brings power up, clears the address scalers for the R A M s , clears the central clock, clears the word c o u n t for the r e a d o u t of the i n f o r m a t i o n and sets the u m t into the mode for processing data pulses Immediately after the clear pulse, clock pulses are d t s m b u t e d to all units via a second patched C A M A C bus These clock pulses increment the central clock

I

GRAY CODE[ INPUT / STROBE~ FAST 2 BIT ~~C~L,TS sy o O OUS ] BUFFER AND FLAG EAR FLAG FLAG

1 B' ARY I

GRAYCODE

BITS

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16 BIT RAM

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CAMAC DATA BUS Fig 1 Block dmgram of data storage using a fast buffer for two low order b~ts

686

DIETRICH

FREYTAG

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Fig 2 C~rcmtry for m t e r m e d m t e storage of two low order bits and s ubs e que nt transfer to the ma i n m e m o r y ( R A M ) - one of e~ght channels

(one per module) After a predetermined number of clock pulses, each umt wall terminate the data acquisition cycle and be ready for readout of data wa the C A M A C data bus During data acquisition, the time separation of up to sixteen data pulses in each of eight independent channels will be encoded If more than 16 pulses are prowded, later data will override the information in the last word of a given channel Test pulses can be distributed instead of normal data via a bussed C A M A C patch pin to all eight channels of each module A computer program then tests the equahty of the data in all the channels of the system The last step in the sequence is the readout of the data, using the C A M A C block transfer Power is switched off automatically after a predetermined time interval of several mllhseconds, which must be matched to the read speed of the system. Alternately, power could be turned off after reading the last word, l e , module is addressed and generates no Q response 3. Circuitry for the intermediate storage of low order bits In order not to be hmlted by the time resolution of the RAM, a fast storage of two low order bits precedes storage of the complete information in the RAM (see block diagram, fig 1) Storage of only two bits rather than the complete word obviously results In significant

savings in circuitry However, due to the asynchronous arrival of signals relative to the internal clock, some logic has to be provided which locks in on the clock phase Storage and synchronlzaUon ~s achieved using the circuitry shown in fig 2 in each channel The lowest data bits (A and B In fig 2) are presented in the form of a Gray code which involves the change of only one bit m any short time interval An input signal activates the parallel clock input of the 7495 data storage register (CK2, fig 2), resulting in the storage of data bits A and B and raising of a flag at Q4 The flag clamps the parallel clock input and provides data to a latch bit (1/4 of 7495) The next pulse of the central clock starts the data transfer cycle by setting the latch bR which m turn switches the shift register into serial mode and removes the data to the latch bit A second clock pulse lowers the flag in the data register by serially loading the low level at Dse, and resetting the latch The input ~s now ready to accept the next signal The diagram shown in fig 3 ln&cates the time sequence of signal processing The period of the lowest clock bit directly transferred to the RAM (data bit 3) is 80 ns This sampling time interval is subdivided into 20 ns intervals by data bits A and B. (A third Gray code bit with a 20 ns half-period could be added to give 10 ns resolution) The Gray code bits are then decoded into regular binary code through exclusive or gates (1/2 7486 in fig 2) before being stored together

COMPACT

TIME RANGE OF INPUT S I G N A L S :

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DIGITIZER

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Fig ~ Time sequence of signal processing for storage and transfer or low order bits with the higher order bits at " s t r o b e " Ume ( + 4 0 n s m the dmgram, fig 3) into the R A M Input signals occurring near the hmits of the sampphng h m e interval may lock m on the previous or following s a m p h n g periods Consider a pulse arriving at - 2 1 ns on the h m t n g diagram (fig 3), l e , within the ' i n p u t ' range shown the strobe locks m on the low phase of data bit 3 and the decoded t]me reads 3 umts A n i n p u t s~gnal arriving at - 1 9 ns, l e , m the next s a m p h n g interval, will lock in on the phase where data bit 3 is high, corresponding to 4 t~me units The G r a y code b~ts have not changed, but their interpretation - wlth the help of data b~t 3 - now y~elds 0 (cf 3 previously) This method insures a m o n o t o n i c encoding of t~me Depending on the relatwe phase of clock and i n p u t pulses, a pulse pair will be resolved when the pulses are from 120 to 200 ns apart This zs relevant if data from PWC are to be encoded with the i n s t r u m e n t as designed for spark c h a m b e r r e a d o u t Data can be provided at a m a x i m u m rate of 5 M H z and all addresses will increment m steps of 10 with this choice of frequency

4. Address averaging for proportional wire chamber ( P W C ) data When the passage of a single charged particle results

m the setting of two adjacent wires, the average of

these addresses wdl m general be used in the subsequent processing of the data F o r this reason, a hardware

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F]g 4 Circuitry for address averaging of two (or more) input s~gnals arriving with a tame separation of one clock period between successwe s~gnals (Modified versmn for proportional wwe chamber readout )

688

DIETRICH

system averaging neighboring addresses was implemented in the version of the digitizer used for PWC readout This circuitry replaces the now unnecessary storage of low order bits In this scheme all wire addresses are encoded in increments of two When two adjacent wires are hit, the lowest order bit is also set, thus recording for n adjacent wires the ( n - l ) average posmons between them Note that with this method of encoding the original wire addresses can always be reconstructed In a particular experiment, we found that an occasional long sequence of wire addresses would overflow the data buffer, resultmg in a loss of lnformanon The radical approach of truncating any sequence after the first two addresses solved this problem The logic for achieving the address averaging, both for complete and for truncated sequences, is explained with the help of fig 4 Incoming data are strobed into the sift register 7495 and shifted right by a succession of clock pulses If a data bit is shifted into position Q2, an address will be stored in the R A M (except for the last bit in a sequence) In addition, the lowest bit will be set if position Q1 also contains data The truth table (table 1) indicates the storage operations resulting from the different b~t configurations

5. Synchronous clock The circuitry provides the time reference for encoding the data pulses It consists of a synchronous scaler generating the Gray code data bits A and B and the binary bits 3-16 for direct transfer to the R A M s In addition, it provides strobe and clock pulses controlling the transfer of data The highest bit in the cham indicates the end of the data acquisition cycle

6. Data format and addressing of the random access memory (RAM) As there is no ttme to clear memory before data acquisition, an alternative method is used to indicate valid data (see fig 5) Data are written into memory in ascending order from address zero up to a maximum address of fifteen, activating the count up input of the addressing scaler 74193 after each transfer. Reading of the data proceeds m descending order cycling through all sixteen addresses, with each C A M A C read command generating a count-down transition for the addressing scaler at the beginning of each read cycle Address zero, which contains the first written word, puts up a flag on a high order bit (we use bit 18) to indicate the last vahd word (Data words after the flagged word are to be d i s r e g a r d e d ) The

FREYTAG TABLE 1 Truth table of storage operations as a function of bit patterns stored m the shift register (Modified v e r s m n for p r o p o m o n a l wtre c h a m b e r re a dout )

Q1

Q2

Q3

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1 1 1

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0

1

1

Version to suppress Version for r e c o r d m g all but l e a dmg all wire addresses address of sequence

transfer single address transfer averaged address transfer subsequent no transfer averaged address no transfer

ambiguity between no data and 16 words of data can be resolved by fiduclal words or through the monotonic nature of the data Due to the power pulsing (described below), old data are destroyed after each event The u p - d o w n counter 74193 provides a carry signal which is used for clamping at address 15 when writing into ascending locations The last word will thus contain the arrival time of the last pulse of 16 or more The borrow signal, when reading in descending order, provides the flag to indicate the last valid word This can be used to transfer to the next channel if the transfer time has to be mlmmlzed (In a special application, this readout scheme was modified and the address scaler was read prior to decrementing, giving the word count in each channel ) Readout of the 128 words is done using the C A M A C block transfer mode (see fig 6) At the end of the encoding cycle, defined by the clock reaching a predetermined value, the first word is selected and will appear when the module is addressed with the read function (F0 or F2) Each S2-strobe advances selection to the next word On word 129 the card does not generate Q, signaling the end of the data block ADDRESS ADVANCE

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F L BIT

ADDRESS ALL RAM

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Fig 5 A d d r e s s m g scaler for storage m R A M (one of eight) The associated logic increments the address for wrUmg a nd decrements for readmg, h i l t S the address range from 0 to 15, and provides a flag bit for the last word

COMPACT RAM ADDRESS ADVANCE'

TIME DIGITIZER ENABLE rCAMAC READ

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SELECT FOR READ

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Fig 6 R e a d o u t logic for C A M A C block transfer Sixteen words m each of e i ght channels are read m response to C A M A C read commands

7. Gating of data onto CAMAC bus

9. Testing and monitoring

The R A M s used here put out data during the storage operation Thus, the presence of a dlgmzer m a C A M A C crate makes it impossible to read data from any module in the crate durmg data accumulation ff no further gating is prowded Furthermore, many crate controllers do not lock out data when transmitting L A M information, which without further gating, prevents determination of the L A M status of the C A M A C crate during the digitization. F o r these reasons, gating of data with the module address is advisable A gating method revolving a minimum of additional circuitry and wiring consists in buffering each bit through a section of a 7407 open collector driver Gating of the data is accomphshed by turmng the supply voltage of the 7407 on during read only The response of this arrangement easdy matches the speed requirements of the C A M A C read cycle

F o r a thorough check of the instrument, a computer is nearly indispensable It was found from experience that all bit combinations have to be tested repeatedly because of unavoidable wiring and soldering errors and because of malfunchons of individual memory locations in the R A M itself Through an or-clrcmt m the input (see fig 2), all channels are permanently connected to a common test line This test line carries computer-generated pulse trains of variable length and pulse separation The time separation of these pulses is encoded in all channels simultaneously and the result is read back and checked against the expected numbers from the known pulse sequence A n y detected errors cause a detailed printout which provides the lnformahon needed to track down the malfunction

8. Power pulsing The 32 units of 64-bit memory dissipate a considerable amount of heat with the complete module drawing 3 A at 6 V Ten or more modules side-by-side in a C A M A C crate cannot be effectively cooled. F o r this reason, a power pulsing scheme has been used which keeps the circuitry very cool, insuring a long life of the integrated cwcults. At event time, power is turned on and the logic cleared After 1 #sec, before arrival of the first signal, full dc power is estabhshed The power is kept on during several milliseconds, during whzch t~me data are accumulated and transferred to the computer Power is then switched off automatically

10. Operational experience The dlgmzmg system for encoding data from magnetostrlchve spark chambers has been used in an experiment at Brookhaven National L a b o r a t o r y since the winter of 1972 Up to ten modules with a total of 1280 words (filhng one half of a C A M A C crate) have been operated simultaneously and with a minimum of maintenance after debugging of the system The version for encoding P W C information - m which low order bit storage has been replaced by address averaging - has been in use in an experiment at SLAC since early 1975 1 am most grateful to Dr W E Cleland for the many discussions of the design and suggestions for improvements The computer-based test scheme, designed by him, proved m~aluable in finding eluswe or intermittent malfunctions