poly-gate complementary metal oxide semiconductor technology

Solid-State Electronics 54 (2010) 368–377

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Solid-State Electronics journal homepage: www.elsevier.com/locate/sse

A comparison of plasma-induced damage on the reliability between high-k/metal-gate and SiO2/poly-gate complementary metal oxide semiconductor technology Wu-Te Weng a,*, Yao-Jen Lee b, Horng-Chih Lin a,b, Tiao-Yuan Huang a a b

Institute of Electronics, National Chiao Tung University, 1001, Ta-Hsueh Road, Hsinchu 300, Taiwan National Nano Device Laboratories, 26, Prosperity Road 1, Science-Based Industrial Park, Hsinchu 300, Taiwan

a r t i c l e

i n f o

Article history: Received 10 April 2009 Received in revised form 3 January 2010 Accepted 5 January 2010 Available online 10 February 2010 The review of this paper was arranged by Prof. A. Zaslavsky Keywords: Plasma-induced damage High-k/metal-gate MOSFET PBTI NBTI

a b s t r a c t This study examines the effects of plasma-induced damage (PID) both on advanced SiO2/poly-gate and Hf-based high-k/dual metal-gates transistors processed with advanced complementary metal–oxidesemiconductor (CMOS) technology. In addition to the gate dielectric degradations, this study demonstrates the PID impacts on transistor reliability including the positive bias temperature instability (PBTI) of n-channel metal–oxide-semiconductor field-effect transistors (MOSFETs) and the negative bias temperature instability (NBTI) of p-channel MOSFETs with gate dielectric thickness scaling. This study shows that high-k/metal-gate transistors are more robust against PID than conventional SiO2/poly-gate transistors with similar physical thickness. Finally this study proposes a model that successfully explains the observed experimental trends in the presence of PID for advanced high-k/metal-gate CMOS technology. Ó 2010 Elsevier Ltd. All rights reserved.

1. Introduction Researchers first reported plasma-induced damage (PID) in 1983 [1] using the plasma steps during the interconnect formation processes. PID is well known to degrade both gate dielectric and metal–oxide-semiconductor field-effect transistors (MOSFETs) reliability [2]. The silicon wafer manufacturing employs many plasma-processing steps, including gate electrode etching [3], high density plasma chemical vapor deposition (HDP–CVD) [4], metal interconnect etching [5], and photoresist ashing [6]. During plasma processing, charges (i.e., ions or electrons) accumulated from a large interconnect area cause a local imbalance in the surface potential across the gate dielectric, and cause current to flow through the gate electrode. The plasma damage current can potentially break the gate dielectric bonds with increasing gate dielectric leakage current or decreasing breakdown voltage. Moreover, the defects or weak points that PID creates in the bulk dielectric and the dielectric/Si-substrate interfaces can further degrade the transistor reliability, such as threshold voltage instability after reliability stressing. However, SiO2 as the gate dielectric is now facing fundamental physical limitations, as film thickness comprises only a few atomic * Corresponding author. Tel.: +886 9 18252823; fax: +886 3 5678229. E-mail address: [email protected] (W.-T. Weng). 0038-1101/$ - see front matter Ó 2010 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2010.01.007

layers [7]. To solve this fundamental barrier, high-k/metal-gate transistors can be introduced into advanced complementary metal–oxide-semiconductor (CMOS) technology to replace SiO2/ poly-gate transistors in suppressing the gate leakage current and eliminating poly depletion effect [8]. Therefore, not only the process but also the electrical reliability of the high-k/metal-gate transistors must be compatible with current SiO2/poly-gate CMOS technology [9]. Previous studies on p-channel PMOSFETs have shown that positive charges (holes) become trapped at the SiO2/ Si-substrate interface under negative gate bias stress, causing shifts in the threshold voltage (VTH) during prolonged device operation (i.e., negative bias temperature instability (NBTI) effect) [10,11]. Electrons trapped in oxygen vacancies in high-k film for n-channel MOSFETs (NMOSFETs), cause a significant shift in VTH under positive gate bias stress (i.e., positive bias temperature instability (PBTI) effect [12]. Both NBTI and PBTI become important issues for high-k/metal-gate transistors. Paying significant attention to the PID-enhanced transistor reliability degradation is necessary as CMOS technology continues to scale. Previous studies show the PID impacts high-k/metal-gate transistors [13,14]. However, a comprehensive study for comparing the PID effects between SiO2/poly-gate and high-k/metal-gate transistors on the antenna ratio dependence and gate dielectric thickness dependence in terms of damage-enhanced gate dielectric failure and damage-enhanced transistor reliability degradation is still lacking.

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In this study we propose both damage mechanism and degradation models for high-k/metal-gate transistors, and comprehensively compare the damage-enhanced degradations between high-k/metal-gate and conventional SiO2/poly-gate transistors. In addition to gate dielectric degradation, this study investigates the high-k/metal-gate transistor reliability issues, including NMOSFETs’ PBTI and PMOSFETs’ NBTI with damage-enhanced generation in oxygen-vacancy-related defects, and electron captured in oxygen vacancies in the high-k film during reliability testing. This study shows the relationship between PID and gate dielectric thickness scaling. Moreover, this study demonstrates the power– law dependence between gate antenna ratio and the transistor’s reliability degradations. Furthermore, this study shows that proposed models can be used to accurately predict the failure distribution for NBTI and PBTI reliability degradation caused by PID. Researchers can use the proposed models to accurately predict gate dielectric failure and transistor lifetime in the presence of PID for advanced high-k/metal-gate CMOS technology.

thermore, to construct an equal plasma condition effecting on every transistor, high-k/metal-gate transistors and SiO2/poly-gate transistors are processed in a same process flow of full-layer CMOS technology. All transistors in this study are treated in a similar damaged processing except for a minor difference in the gate etching process. The gate antenna ratio, AR, is defined as

2. Experimental procedure

This study defines the gate dielectric failure of damaged transistors as a twofold increase in the dielectric leakage current compared to undamaged transistors (i.e., Ig/Igundamaged > 2, here the Igundamaged is the mean value of the gate leakage current on undamaged transistors with a small antenna ratio of AR = 3). The gate dielectric leakage current was measured under an electric field of 7–9 MV/cm (i.e., the measurement voltage is 1.4 V for transistors with thinner EOT = 1.5–2.0 nm, and 2.0 V for other transistors with EOT = 3.0 nm). The gate dielectric breakdown voltage VBD was measured by the voltage ramp method. In this study we define the failure ratio of gate dielectric leakage current and gate dielectric breakdown as the percentage of failure out of the total measured samples. Both for damaged and undamaged transistors, the NBTI measured on PMOSFETs and PBTI measured on NMOSFETs were performed under electric field of 10 MV/cm by HP-4156 system at 125 °C (i.e., the voltage stress is 2.0 V for transistors with EOT = 2.0 nm, and 1.5 V for transistors with EOT = 1.5 nm). The NBTI lifetime and PBTI lifetime were defined as the time until the transistor exhibited a 50 mV shift in threshold voltage. The EOT was extracted from the capacitance–voltage characteristics using a HP-4284 system at room temperature.

2.1. Wafer processing Advanced high-k/metal-gate and conventional SiO2/poly-gate transistors processed with full layers of CMOS technology were investigated in this study. Many process steps including shallow trench isolation (STI), and the formation of a triple well, shallow junction and Co salicide were all integrated for high-performance circuit applications. For the conventional SiO2/poly-gate transistors, the gate oxide thickness ranged from 1.5 nm to 3.0 nm, while for the Hf-based high-k/metal-gate transistors, the equivalent oxide thickness (EOT) ranged from 1.5 nm to 2.0 nm (i.e., with physical thickness of approximately 3.0–5.0 nm). The term EOT represents the theoretical thickness of dielectric layer required to achieve the same capacitance density as SiO2, expressed with EOThigh-k = physical thickness (Tph) of high-k(koxide/khigh-k) [9]. For example, a high-k layer with relative permittivity of 16 affords a physical thickness of approximately 2.0 nm for obtaining EOT = 0.5 nm. For high-k/metal-gate transistors, the dielectric consisted of a SiO2 interfacial layer (IL) and an HfSiO film, which were both treated with NH3 annealing. Then, EOTtotal = EOTIL + EOThigh-k = Tph,IL + Tph,high-k(koxide/khigh-k). A chemical oxide with a thickness of 0.8 nm was used as the IL layer, and HfSiO layers with different physical thicknesses ranging from 2.0 to 4.5 nm were fabricated for transistors with different EOT in this study. Dual metal-gate structures (i.e., TaC for NMOSFET’s metal-gate and MoNx for PMOSFET’s metal-gate) were manufactured to meet high-speed performance requirements. The high-k and metal films were deposited using atomic-layer deposition (ALD) and physical vapor deposition (PVD) techniques, respectively. In the case of ALD, the ratio of Hf/(Hf + Si) of HfSiO film was 50% for all high-k/ metal-gate transistors. A rapid thermal annealing (RTA) at 1000 °C for 5 s was performed for the source/drain activation. 2.2. Test structure design Fig. 1a illustrates that plasma-induced damage can usually be detected using various antenna structures. These antenna structures include a transistor with a large gate antenna attached to its gate electrode, which amplifies the charging damage produced under plasma processing during the full gate electrode formation process. During gate definition, side-wall spacer etching, and photo resistor ashing in etching systems, as well as in post gate dielectric film deposition in HDP–CVD systems, plasma will attack the gate antenna area and further damage the gate dielectric (Fig. 1b). Fur-

AR ¼

Area of gate antenna Area of gate oxide

ð1Þ

In this study we have fabricated a set of test structures with various AR of 3 (i.e., undamaged transistors), 100, 500, 1000, 5000, and 10,000 (i.e., significantly damaged transistors) to simulate the impact of the PID effects on real circuits during various stages of plasma processing. The gate oxide area of the monitoring transistor used in our experiment was 1 lm2, and the transistor length and width were 0.2 lm and 5 lm, respectively. 2.3. Electrical measurements

3. Results and discussion 3.1. Dielectric degradation 3.1.1. The prediction models of damage-enhanced dielectric degradation Dielectric breakdown of high-k/metal-gate transistor is due to the clusters of disconnected bonds. These clusters propagate through the dielectric film, and finally reach the high-k/metal-gate interface. It is generally believed that defects existing in the dielectric layers can produce weak spots or trap centers that trap charges. During plasma processing, the damage current flowing through the gate dielectric can be viewed as an equivalent voltage stress, Vst, or electric field stress, Est, across the gate dielectric. This Vst or Est is able to generate lots of defects for high-k/metal gate transistors [15]. Moreover, these PID effects can aggravate the degradations of the dielectric layer owing to the extra damage current paths generated by the Vst across the dielectric layers during the plasma processing. To simplify the analysis of damage impacts during the wafer fabrication, the dependence of the damage effect on AR is introduced in terms of the plasma damage current Iplasma to simulate the damage characterization. By assuming a fixed AR under a given plasma process, the term Iplasma can be considered as a constant current source of ‘‘damage current” that passes

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Plasma Damage Antenna area

Gate Gate

5 m STI 0.2 m

Gate oxide area

Active area MOSFET

(a)

STI

(b)

Fig. 1. Schematic diagrams of the transistor with its gate being connected to an antenna structure: (a) top view of the test structure and (b) cross section.

PMOSFETs

10-6

Current (A)

Iplasma (AR=1000X) Iplasma (AR=100X) Iplasma (AR=10X) Iplasma (AR=1X)

SiO2/poly, EOT=1.5 nm High-k/metal, EOT=1.5 nm SiO2/poly, EOT=2.0 nm High-k/metal, EOT=2.0 nm SiO2/poly, EOT=3.0 nm

Vst(AR=1000X)

10-7

AR=1000X

Vst(AR=100X) 10-8

AR=100X AR=10X

Vst(AR=10X) -9

10

10-10

AR=1X

Vst(AR=1X)

0

1

2

3

4

5

6

7

8

Voltage (V) Fig. 2. Characteristics of gate dielectric current and simulated plasma damage current with respect to voltage. The gate dielectric current curves are measured at various gate oxide thicknesses ranging from 1.5 nm to 3.0 nm for SiO2/poly-gate PMOSFETs, and EOT ranging from 1.5 nm to 2.0 nm for high-k/metal-gate PMOSFETs. This study simulates the plasma damage current for gate antenna ratios AR of 1, 10, 100, and 1000.

35

30

Electric Field Stress Est (MV/cm)

10-5

Comparing the plasma current–voltage with dielectric current– voltage characteristics, Iplasma corresponds to a voltage stress, Vst, on the gate electrode during plasma processing. Aggravated dielectric degradation from PID results in an increase in the effective stress voltage Vst across the gate dielectric during plasma processing. Clearly, Vst not only depends on AR, but is also influenced by EOT. Fig. 3 shows that the Est, defined as Vst/EOT, is a function of AR. A larger AR results in a larger Est, and therefore much more severe degradation in dielectric reliability for EOT ranging from 1.5 nm to 3.0 nm for both SiO2/poly-gate and high-k/metal-gate transistors. Moreover, Est strongly depends on EOT. For example, for SiO2/ poly-gate transistors with EOT = 3.0 nm, the tunneling mechanism of plasma current passing through the dielectric can be dominated by Fowler–Nordheim (F–N) tunneling, and Est exhibits a greater antenna dependence during plasma process. In contrast, when the EOT is reduced to 1.5–2.0 nm for high-k/metal-gate transistors and SiO2/poly-gate transistors, the tunneling mechanism shifts from Fowler–Nordheim to direct tunneling while applying a voltage stress Vst on the gate during the plasma process. This in turn produces a lower antenna dependence of Est compared to SiO2/ poly-gate transistors with a gate oxide thickness of 3.0 nm.

Electric Field Stress Est (MV/cm)

through the high-k/metal-gate electrode. As the AR increases, the total plasma current passing through the gate dielectric increases proportionally to AR. Fig. 2 shows the dielectric current–voltage curves of PMOSFETs with different gate dielectric thicknesses and values of AR. Iplasma can be expressed as Iplasma = P  AR, where P is the plasma damage current collected when AR = 1 (i.e., an antenna ratio of unity). The P value is assumed to be a constant under a given plasma processing and is expected to exhibit a process dependence due to changes in ion density, electron temperature, etc. as the plasma processing changes [16]. During plasma processing, dielectric breakdown occurs at plasma current density of approximately 2–20 A/cm2 [17]. Thus, the experiments in this study assume that the P value is approximately 2  1010 A with 1 lm2 transistors size (i.e., for the damaged structures with antenna ratio AR = 100, Iplasma = 2 A/cm2, and for structure with AR = 1000, Iplasma = 20 A/cm2). Fig. 2 depicts the dielectric current–voltage curves of PMOSFETs with different gate dielectric thickness for both high-k/metal-gates and SiO2/poly-gates. This figure also indicates the plasma damage current simulated for various AR.

30

20

25

High-k/metal (AR=1X) High-k/metal (AR=10X) High-k/metal (AR=100X) High-k/metal (AR=1000X)

SiO2/poly, EOT=1.5 nm High-k/metal, EOT=1.5 nm SiO2/poly, EOT=2.0 nm High-k/metal, EOT=2.0 nm SiO2/poly, EOT=3.0 nm

25

15 10

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10X

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SiO2/poly (AR=1X) SiO2/poly (AR=10X) SiO2/poly (AR=100X) SiO2/poly (AR=1000X)

5

0

1.5

2.0

2.5

3.0

EOT (nm) Fig. 3. Estimated electric field stress (Est) during plasma processing as a function of EOT for different AR. The inset shows the Est as a function of AR for different EOT.

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99.5 99 98

SiO2/poly, EOT=1.5nm High-k/metal, EOT=1.5nm SiO2/poly, EOT=2.0nm High-k/metal, EOT=2.0 nm SiO2/poly, EOT=3.0nm

95

80 70 60 50 40 30

PMOSFETs AR=5000X E-field: 7~9MV/cm

20 10 5 2 1 0.5 10-1

99.5 99 98

Criteria 1

101

Probability (%)

Probability (%)

90

95 90 80 70 60 50 40 30 20

PMOSFETs AR=5000X

10 5 2 1 0.5 2

SiO2/poly, EOT=2.0nm High-k/metal, EOT=2.0 nm SiO2/poly, EOT=3.0nm 3

4

5

6

Gate Dielectric Breakdown VBD (V)

102

103

104

105

106

Gate Leakage Increase (Ig/Igundamaged, arb. unit) Fig. 4. Failure probability of gate dielectric leakage measured on PMOSFETs with EOTs ranging from 1.5 nm to 3.0 nm for SiO2/poly-gate transistors, and EOTs ranging from 1.5 nm to 2.0 nm for high-k/metal-gate PMOSFETs. The inset is the failure probability of VBD measured for the above transistors with EOTs greater than 2.0 nm. The AR attached to these transistors is 5000.

35

PMOSFETs Gate Leakage Failure Ratio (%)

3.1.2. The results of damage-enhanced dielectric degradation Fig. 4 demonstrates the failure ratios in terms of gate dielectric leakage current and breakdown voltage for a given AR of 5000 for both SiO2/poly-gate and high-k/metal-gate PMOSFETs with various EOTs. It is evident that SiO2/poly-gate transistors with a gate oxide thickness of 3.0 nm show significant gate oxide leakage distribution and a higher VBD failure ratio as the plasma current Iplasma increases. Specifically, the failure ratios of gate dielectric leakage and VBD for SiO2/poly-gate MOSFETs with a gate oxide thickness of 3.0 nm increase by 26%. In contrast, for SiO2/poly-gate and highk/metal-gate transistors with an EOT of approximately 1.5– 2.0 nm, the oxide tunneling mechanism is dominated by direct tunneling. This in turn produces a smaller stress voltage Vst, on the gate electrode stacks during plasma process. Fig. 4 shows that the failure ratio of gate dielectric leakage and VBD degradation can be reduced to less than 6% by decreasing the EOT to below 2.0 nm.In addition, Fig. 5 demonstrates the dependence between failure ratios of gate leakage current and transistors’ EOTs ranging from 1.5 nm to 3.0 nm with different AR of 100, 500, and 5000. By reducing the EOT from 3.0 nm to 1.5 nm, the dielectric failure ratio of the antenna transistors connected to AR = 500 can be decreased from 12% to nil, and the failure ratio of the transistors connected to AR = 5000 can be further reduced to from 26% to 2%, as Fig. 5 indicates. These results confirm that the Est is linearly dependent on EOT, and can be decreased by reducing EOT from 3.0 nm to 1.5 nm as well as changing the test structure from SiO2/poly-gate to high-k/metal-gate transistors. In addition, the EOT dependence of damage-enhanced gate dielectric degradation is irrespective of the AR. The results of Figs. 4 and 5 are consistent with the damage models proposed in this study and shown in Figs. 2 and 3. Clearly, a transistor with an EOT of approximately 3.0 nm shows a strong AR dependence of Est. Based on the experimental trends, plasma damage effect impact on gate dielectric degradation strongly correlates with EOT rather than physical thicknesses. Under a similar damaged processing, the high-k/metal-gate transistors are more robust against PID than conventional SiO2/poly-gate transistors with a similar physical thickness of approximately 3.0–4.0 nm. This study confirms that the strong dependence of dielectric EOT causes significant damage to the input/output transistors with a thicker EOT of approximately 3.0 nm for SiO2/poly-gate transistors. Therefore, high-k/metal-gate

30

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20

SiO2/poly (AR=100X) SiO2/poly (AR=500X) SiO2/poly (AR=5000X) High-k/metal (AR=100X) High-k/metal (AR=500X) High-k/Metal (AR=5000X)

15

10

5

0 1.0

1.5

2.0

2.5

3.0

3.5

EOT (nm) Fig. 5. Failure percentages of gate leakage current as a function of EOT for both high-k/metal-gate and conventional SiO2/poly-gate PMOSFETs with EOTs ranging from 1.5 nm to 3.0 nm with ARs of 100, 500, and 5000.

transistors with a thinner EOT would be robust for PID compared to a thicker EOT, because damage induced dielectric degradation is not a serious issue for the thinner gate dielectric high-k/metalgate transistors needed to support operation voltage in the core circuit design. For example, the standby current of a six-transistor static random access memory chip (6T-SRAM) exhibits a functional dependence in gate leakage [18]. 3.2. BTI instability and SILC increase PID is usually evaluated by monitoring the dielectric leakage current [19] or breakdown voltage [20] with a given antenna ratio attached to the gate electrode, as demonstrated in Fig. 4. Therefore, the defect and trap generation in the gate dielectric leads to dielectric breakdown when reaching a critical trap density. The critical trap density at which a percolating path forms triggers the gate dielectric breakdown [21]. The occurrence of additional gate dielectric leakage implies the existence of additional current paths within the gate dielectric layers. Prior to conductive path formation within the dielectric layers, sufficient damage (i.e., traps and defects) accumulates to influence the initial VTH [13] and DVTH shifts after electrical stress [22]. Further, damaged transistors with a large antenna ratio have a significant difference in initial VTH and simultaneously depict great influence on DVTH shift after BTI stress compared with undamaged transistors. For example, for SiO2/polygate PMOSFETs with EOT = 3.0 nm, Fig. 6 shows NBTI lifetime which is dominated by SiO2/Si-substrate interface traps, and gate oxide breakdown voltage VBD, which is a measure of conductive path formation, as a function of damage induced gate leakage current caused by PID. From Fig. 6, NBTI lifetime is significantly degraded at lower gate leakage current regime, while VBD is unaffected until gate leakage current reaches much higher values. That suggests transistor instability and reliability degradation must be considered in addition to gate leakage distortion to fully comprehend transistor reliability impact resulting from the large tunneling current may hide increased gate leakage caused by PID. 3.2.1. Damage-enhanced NBTI degradation for SiO2/poly-gate PMOSFETs This study assumes that the PID effects in the transistors are similar to those caused by gate voltage stress Vst, and the damage current Iplasma is able to generate defects in gate dielectric during plasma process. These defects might not be evident after the plasma processing because the post metallization annealing (PMA)

W.-T. Weng et al. / Solid-State Electronics 54 (2010) 368–377

SiO2/poly-gate PMOSFETs

VBD AR=3X VBD AR=500X VBD AR=5000X

NBTI Lifetime (arb. unit)

EOT=3.0nm

Lifetime AR=3X Lifetime AR=500X Lifetime AR=5000X 10-12

10-11

10-10

Gate Oxide VBD (arb. unit)

372

10-9

Gate Leakage Current (A) Fig. 6. SiO2/poly-gate PMOSFETs NBTI lifetime and gate oxide breakdown voltage VBD as a function of damage-enhanced gate leakage current with EOT = 3.0 nm.

process passivates them [23]. However, NBTI reveals their existence. For SiO2/poly-gate PMOSFETs experiencing NBTI, holes in the inversion layer gain sufficient energy to dissociate the weak Si–H bonds. This in turn generates interface states with holes (positive charges) trapped in the SiO2/Si-substrate interface [10] as shown in Fig. 7. Fig. 7 shows that all SIO2/poly-gate PMOSFETs (both damaged and undamaged transistors) exhibit NBTI degradations; however, the damaged transistors are likely to have a higher number of defects of weak Si–H bonds at the interface as evidenced by the larger DVTH shift in the time dependence of threshold voltage instability. Fig. 7 depicts the NBTI dependence of SiO2/polygate PMOSFETs with an EOT of 3.0 nm for a damaged transistor with an AR of 10000 and an undamaged transistor with an AR of 3. The damaged transistors exhibit larger DVTH shift than the undamaged transistors as the stress time progresses. Specifically, after 1000 s of NBTI stress, the DVTH shift is 32 mV for the undamaged transistors, but 50 mV for the damaged transistors. The results are consistent with previous study of damage-enhanced SiO2/Si-substrate interface states generation and hole trapped in SiO2/Si-substrate for SiO2/poly-gate PMOSFETs during NBTI stress [24].

3.2.2. Damage-enhanced oxygen-vacancy-related defects generation and an increase of SILC for high-k/metal gate MOSFETs Because the difference in PID-induced gate leakage current between damaged and undamaged transistors is small compared with the gate tunneling current, conventional methods (i.e., monitoring increased gate leakage current by applying high electric field) may fail to detect PID, especially for high-k/metal-gate transistors fabricated with a thinner EOT operated at direct tunneling regime. Previous study shows that providing a short time constant voltage stress (CVS) on the gate electrode after wafer processing, and the traps created during plasma process can be revealed in the dielectric layers [25]. These traps can act as sites for assisting the electron tunneling from substrate to gate electrode (i.e., trapassisted tunneling effect) resulting in an increase in the gate dielectric leakage, as shown in Fig. 8. Moreover, the energy level of the traps can be calculated from the curve of stress induced gate leakage current (i.e., SILC) by monitoring how the peak of the increase of SILC responds to the gate voltage [26]. This result indicates that the PID preferentially degrades the high-k film or the interfacial layer for high-k/metal-gate transistors. Fig. 8 shows that damaged high-k/metal gate transistor exhibits an obvious and significant increase of SILC with a peak at around Vg = 0.9–1.0 V. The results are consistent with high voltage stress on transistor’s well resulting in substrate hot electron injection and generating defects in high-k film [26,27]. Defects dominate many electrical properties and transistor reliabilities of high-k/metal-gate transistors. The SILC increases as the PID enhances defect generations, as well as trap associated tunneling in high-k film. Furthermore, based on previous studies [28,29], it has been proposed that the charge state of oxygen vacancies could describe the energy signature of these traps and is responsible for the increase in SILC. To verify the assumption of PID effects on high-k/metal-gate MOSFETs are similar to that caused by gate voltage stress Vst, this study further monitors the increased SILC with applying electrical voltage stress (e.g., Vg = 3.3 V) on undamaged transistors for simulating the damaged transistors during plasma process. Fig. 9 shows the increased SILC as time progress on those undamaged transistors with EOT = 2.0 nm via a Time Dependence Dielectric Breakdown (TDDB) measurement. From Fig. 9, the SILC of high-k/ metal-gate transistor increases as stress time and the increased SILC depicts about one order magnitude higher than the initial value until gate dielectric breakdown. Moreover, high-k film leads to the increased SILC because it does not occur in SiO2/poly-gate tran-

101

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Poly

Si

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Interface trap

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PMOSFETs EOT=3.0nm

Interface trap

NBTI Stress Vg=-3V

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EOT=2.0 nm Stress Conditon (3V/1sec)

SILC Increase (Ig/Igfresh)

102

e

trap

Metal Gate

High-k

SiO2

Si-Substrate

0

10

Damaged MOSFETs 100

101

102

103

104

Stress Time (sec.) Fig. 7. NBTI-induced DVTH shift as a function of stress time for damaged and undamaged SiO2/poly-gate PMOSFETs with EOT = 3.0 nm. The inset illustrates the mechanism difference between damaged and undamaged SiO2/poly-gate transistors during NBTI stress.

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

Sense Vg (V) Fig. 8. The increase of SILC as a function of gate voltage sensed from 1.5 V to 1.5 V for a damaged and an undamaged high-k/metal-gate NMOSFET. The inset illustrates trap-assisted electron tunneling through high-k film for a damaged high-k/metalgate NMOSFET.

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Undamaged NMOSFET IL High-k

High-k/metal-gate NMOSFET SiO2/poly-gate NMOSFET Undamaged transistors EOT=2.0 nm Vg stress=3.3V

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Si

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++

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Vo High-k trap (Oxygen vacancy) 102

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Fig. 9. The increase of SILC as a function of stress time for an undamaged high-k/ metal-gate NMOSFET and an undamaged SiO2/poly-gate NMOSFET. The EOT of those transistors is 2.0 nm.

Fig. 10. PBTI-induced DVTH shift as a function of stress time for damaged and undamaged high-k/metal-gate NMOSFETs. The inset illustrates the mechanism difference between damaged and undamaged transistors during PBTI stress.

sistors. The SILC increases as the electrical stress enhances defect generations, as well as trap associated tunneling in gate dielectric. During plasma process, the stress electric field splits over two dielectric layers (i.e., IL and high-k) and causes degradations in these two layers. Fig. 9 demonstrates that plasma damage can be viewed as an equivalent electrical voltage stress resulting in the degradation of the IL/high-k stack. Moreover, Fig. 8 suggests that oxygen-vacancy-related defects are responsible for high-k layer degradation with increased SILC under an electrical stress. Therefore, the IL degradation was not studied in this paper.

trons in oxygen vacancies within high-k film during PBTI stress. The increased degradation exhibited by damaged high-k/metalgate transistors shown in this study is consistent with PBTI physical models demonstrated in previous literatures [12,28,29]. The time exponent of the DVTH shift in damaged and undamaged transistors is identical, because the increased DVTH of these transistors are all dominated by electron trapping in the oxygen vacancies within high-k film during PBTI stress [12,22].

3.2.4. Damage-enhanced NBTI instability for high-k/metal-gate PMOSFETs For high-k/metal-gate PMOSFETs experiencing NBTI stress, holes in the inversion layer gain sufficient energy to dissociate the weak Si–H bonds. This in turn generates interface states with holes (positive charges) trapped in the SiO2/Si-substrate interface [11] as shown in Fig. 11. Fig. 11 further shows that oxygen-vacancy-related defects exist in the high-k film for a damaged high-k/metal gate transistor, and electrons injected from the metal-gate are captured by oxygen vacancies Vo++ during NBTI stress. Furthermore, the damaged transistors show less degradation because these transistors have higher concentrations of electron trap-

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IL

IL

High-k

Si

Metal

High-k

++

Vo High-k trap (Oxygen vacancy)

V TH shift (mV)

3.2.3. Damage-enhanced PBTI degradation for high-k/metal-gate NMOSFETs This study has assumed PID effects in the gate dielectric of highk/metal-gate transistors are similar to those caused by gate voltage stress, Vst. Furthermore, during the plasma process, the damage current flux Iplasma breaks the weak Hf-based dielectric bonds, generating oxygen-vacancy-related defects (Od) in high-k film. Note that the oxygen vacancy defect bonds are located below the conduction band of the Hf-based dielectric, and oxygen vacancies, Vo++, are produced from the following reaction: Od ? Vo+++ 2e + 1/2O2 [30]. Therefore, the oxygen-vacancy-related defects are evident after the plasma processing because the PMA process passivates them [23]. However, further electrical stress, such as PBTI and NBTI, reveals their existence. Under plasma charging, a large Est stress on high-k film creates many oxygen-vacancy-related defects within the high-k film. Applying PBTI stress to high-k/metal-gate NMOSFETs causes electrons in the inversion layer to gain sufficient energy to be injected into the dielectric layers. As a result, electrons are easily trapped in the oxygen vacancies within the high-k film [12,22]. Fig. 10 shows that all high-k/metal-gate NMOSFETs (both damaged and undamaged transistors) exhibit PBTI degradations: however, the damaged transistors are likely to have a higher number of oxygen vacancies as evidenced by the larger DVTH shift in the time dependence of threshold voltage instability. Fig. 10 depicts the PBTI dependence of high-k/metal-gate NMOSFETs with an EOT of 2.0 nm for a damaged transistor with an AR of 10,000 and an undamaged transistor with an AR of 3. This figure shows that the damaged transistors exhibit larger DVTH shift than the undamaged transistors as the stress time progresses. Specifically, after 1000 s of PBTI stress, the DVTH shift is 85 mV for the undamaged transistors, but 100 mV for the damaged transistors. This is because the damage induces increased oxygen-vacancy-related defects, capturing elec-

Interface trap

Si

++

Vo

High-k trap (Oxygen vacancy)

High-k/metal-gate PMOSFETs EOT=2.0nm

NBTI Stress

Interface trap

Vg=-2V

1

10

Undamaged MOSFETs Damaged MOSFETs 100

101

102

103

104

Stress Time (sec.) Fig. 11. NBTI-induced DVTH shift as a function of stress time for damaged and undamaged high-k/metal-gate PMOSFETs. The inset illustrates the difference between damaged and undamaged transistors during NBTI stress.

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ping (i.e., negative charges) in the high-k film, which mitigates the DVTH shift of hole trapping (i.e., positive charge) during NBTI stress. Fig. 11 depicts the DVTH shift as a function of NBTI stress time for damaged and undamaged high-k/metal-gate PMOSFETs with an EOT of 2.0 nm. This figure shows that the damaged transistors exhibit less threshold voltage shift DVTH than the undamaged transistors as the stress time progresses. Specifically, after 1000 s of NBTI stress, the DVTH shift is about 30 mV for the undamaged transistors, but only 25 mV for the damaged transistors. The time exponent of the DVTH shift in damaged and undamaged high-k/metalgate transistors is identical, because the increased DVTH of these transistors are all dominated by hole trapping in the SiO2/Si-substrate interface during NBTI stress [11,31]. To verify the trapping behavior for high-k/metal-gate PMOSFETs during NBTI stress proposed in this study, current separation measurements were carried out after NBTI stress (Vg = 2 V, 1000 s). Fig. 12 shows that after NBTI stress, the injected holes are monitored by the drain (source) current, while electrons are monitored by the substrate current. Moreover, to investigate the electron capturing effect, this study further examined both highk/metal-gate and SiO2/poly-gate PMOSFETs with an EOT of 2.0 nm. Fig. 12 shows the ratio of electron current (Ie) over the total current (i.e., hole current (Ih) + electron (Ie)) as a function of the sweeping gate voltage. Applying NBTI with 2 V and 1000 s, a large amount of holes in the inversion layer gain sufficient energy to dissociate the weak Si–H bonds, this in turn generates interface states with greater hole trapping at the SiO2/Si-substrate interface. This hole trapping behavior leads to a smaller value of Ie/(Ih + Ie) (i.e., Ih  Ie) for all transistors. Owing to the generation of damage-enhanced oxygen-vacancy-related defects and electrons captured in oxygen vacancies in high-k film during NBTI stress, the damaged high-k/metal-gate PMOSFETs depict the greatest ratio of Ie/(Ie + Ih) in all experiments as shown in Fig. 12. This suggests that, unlike the conventional SiO2/poly-gate PMOSFETs, the damage- induced electron trapping in the high-k film plays an important role in the NBTI characteristics of high-k/metal-gate PMOSFETs, as Fig. 11 indicates. In summary, the results of Figs. 8–12 show that the transient nature of the damage-enhanced electron trapping in high-k film affects the NMOFETs’ PBTI and PMOSFETs’ NBTI performance, consistent with the damage model of high-k/metal-gate CMOS technology proposed in this study.

3.3. Reliability instability and failure distribution 3.3.1. The prediction models of damage-enhanced instability in high-k/ metal-gate MOSFETs reliability Fig. 13 compares the plasma damage with gate dielectric current–voltage characteristics for a high-k/metal-gate NMOSFET with EOT = 2.0 nm, showing that Iplasma corresponds to a voltage stress, Vst, on the transistor gate dielectric during processing. Instability of PBTI and NBTI resulting from PID therefore represent an increase in the effective stress voltage DVst across the gate dielectric during plasma processing. Furthermore, the relationship between AR and DVst can be expressed as

lnðARÞ ¼ C  DV st

ð2Þ

where C is the slope of the gate dielectric current–voltage characteristics in Fig. 13, and is strongly dependent on the EOT, as Fig. 2 indicates. During the plasma processing, defects or traps are generated when the damage induced Vst or Est breaks the dipoles within the dielectric [32,33]. Several previous studies have shown that the increase of defects or traps could be a function of voltage stress [34], and these studies depict an exponential relationship between trap generation and electric field stress across the gate dielectric [35,31]. Thus, during the plasma process, an increase in the density of oxygen-vacancy-related traps within the high-k dielectric, DNOV from the gate stress can be written as an increase of voltage stress DVst as

DNov ¼ A  expðcp DEst Þ ¼ A  expðcp DV st =EOTÞ

ð3Þ

where A is a constant and cp is the electric field acceleration factor. Both of these terms are dependent on the plasma process and cp is approximately 0.1–0.2 (Dec-cm/MV) for plasma processing [36]. During PBTI or NBTI stress, the model proposed in this study shows that the injected electrons which are trapped in oxygen vacancies cause an increase in the negative charge and instability in the transistor threshold voltage. All transistors, irrespective of their antenna ratio, exhibit DVTH shift under PBTI or NBTI stress. However, transistors with larger AR have higher concentrations of negative charge trapped within the high-k layer. For a constant EOT, the DVTH instability resulting from the increase of negative charge trapped for antenna transistor can be modeled as

DV TH ¼ Ht n ARa

ð4Þ

30

(-)

Ihole 25

Metal e

e h

High-k

e h

h

High-k/Metal-gate NMOSFET EOT=2.0 nm Gate dielectric current

Undamaged high-k/metal Damaged high-k/metal Undamaged SiO2/poly Damaged SiO2/poly

SiO2

P+

10-6

P+ N-Well

Iplasma (AR=1X) Iplasma (AR=100X)

10-7

15

Current (A)

Ie/(Ie+Ih) (%)

h

20

PMOSFETs with EOT 2.0 nm NBTI stress(-2V/1000 sec)

Ielectron 10

10-8

Vst(AR=100X)

Slope=C

5

Iplasma=P*AR ln (AR)=C Vst

-9

10 0 0.0

Vst(AR=1X) -0.1

-0.2

-0.3

-0.4

-0.5

AR=100X

AR=1X

-0.6

Sense Vg (V) Fig. 12. The ratios of Ie/(Ie + Ih) as a function of sweeping gate voltage for damaged and undamaged PMOSFETs fabricated with high-k/metal-gate and conventional SiO2/poly-gate after NBTI stress (i.e., Vg = 2 V and 1000 s). The inset illustrates the current separation method to identify the injection carriers within the gate dielectric.

-10

10

0.5

1.0

1.5

2.0

2.5

3.0

Voltage (V) Fig. 13. The characteristics of measured dielectric current and simulated damage current as a function of voltage for various AR for a high-k/metal-gate NMOSFET with an EOT of 2.0 nm.

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where t is the duration of the NBTI or PBTI stress, n is approximately of 0.16 for both NBTI and PBTI [37], and H is a constant. The parameter a can be expressed as

ð5Þ

Note that a for PBTI stress is positive (i.e., DVTH increases with AR), while a for NBTI stress is negative (i.e., DVTH decreases with AR). The failure time tf, defined as the time required to reach the critical threshold voltage increase DVthc, is

t f ¼ G DVcARm

ð6Þ

where G is a constant for a given process, DVC = (DVthc)1/n, and m = a/n. Furthermore, the damaged SiO2/poly-gate PMOSFETs with a larger AR have a higher number of defects of weak Si–H bonds at the Si/substrate interface (i.e., DNit) leads the larger DVTH shift in the time dependence of threshold voltage instability. Correspondingly, for SiO2/poly-gate PMOSFETs NBTI, a in Eq. (5) is positive, and the antenna dependence of failure time follows power–law relationship as Eq. (6). 3.3.2. The effects of EOT on the damage-enhanced instability in BTI reliability Fig. 14 shows the PBTI lifetime and Fig. 15 plots the NBTI lifetime as a function of antenna ratio, respectively. These figures indicate that the antenna dependence m follows the power–law relationship, consistent with Eq. (6). For high-k/metal-gate transistors with an EOT of 2.0 nm, Fig. 14 shows m is 0.07 for NMOSFETs’ PBTI lifetime, but Fig. 15 indicates a larger m of 0.15 for PMOSFETs’ NBTI lifetime. The difference in the antenna dependence is caused by the difference of dielectric current–voltage characteristics. For a plasma process with a given Iplasma, PMOSFETs experience a higher stress-voltage that leads to a higher oxygen vacancy generation rate than NMOSFETs as shown in Figs. 2 and 13. In addition, Fig. 15 demonstrates a ‘‘reverse antenna effect” (i.e., the NBTI lifetime increases with AR) for high-k/metal-gate PMOSFETs. This effect is caused by damage-enhanced electron trapping within the high-k bulk film. This trend is contrary to in SiO2/poly-gate transistors, where damage-enhanced hole trapping within SiO2/Si-substrate is dominant. Furthermore, based on the power–law relationship demonstrated in this study, the reliability data obtained from existing antenna test structures can be extrapolated to the transistors with any antenna ratios used in the circuitry. Fig. 13 shows that C can be determined by the oxide conduction mechanism, and the antenna dependence m in Eq. (6) can be signif-

PBTI Lifetime (arb. unit)

NMOSFETs

100

Slope=-0.07 High-k/metal, EOT= 1.5 nm High-k/metal, EOT= 2.0 nm 1X

10X

100X

1000X

10000X

AR Fig. 14. PBTI lifetimes as a function of AR for high-k/metal-gate NMOSFETs with EOTs of 2.0 nm and 1.5 nm, respectively.

NBTI Lifetime (arb. unit)

a ¼ cp =ðEOT  CÞ

101

High-k/metal, EOT= 1.5 nm High-k/metal, EOT= 2.0 nm SiO2/poly, EOT= 3.0 nm SiO2/poly, EOT= 1.5 nm

PMOSFETs Slope=0.15

100

Slope=-0.3

10-1

1X

10X

100X

1000X

10000X

AR Fig. 15. NBTI lifetime as a function of AR for high-k/meta-gate PMOSFETs with EOTs of 2.0 nm and 1.5 nm, and SiO2/poly-gate PMOSFETs with an EOT of 3.0 nm and 1.5 nm, respectively.

icantly reduced with larger C for transistors with a thinner EOT. Figs. 2 and 3 show that a smaller Vst and Est dependence suggests that the plasma damage effects are mitigated for high-k/metal-gate transistors. As a result, Figs. 14 and 15 show that high-k/metal-gate transistors exhibit smaller antenna ratio dependence than SiO2/ poly-gate PMOSFETs with a similar physical dielectric thickness of approximately 3.0 nm. For example, SiO2/poly-gate PMOSFETs with an EOT of 3.0 nm exhibit the greatest plasma damage and the largest value of m (i.e., 0.3) among all samples. Furthermore, as the EOT of the high-k/metal-gate transistor decreases from 2.0 nm to 1.5 nm, Figs. 2 and 3 show that the stress voltage can be reduced to the operation voltage or below. Thus, the stress electric field Est becomes insignificant, which in turn produces a lower failure ratio of gate leakage and dielectric breakdown, as Figs. 4 and 5 indicate. Moreover, for damage-enhanced reliability degradation in high-k/metal-gate transistors, the increasing C value eliminates the oxygen-vacancy-related defects introduced within the high-k film. This suppresses the antenna dependence in reliability. Figs. 14 and 15 show that large C reduces the antenna dependence of PBTI lifetime and NBTI lifetime until it becomes almost negligible. The models proposed in this study are consistent with experimental results, and further confirm that damage-enhanced transistor reliability degradation is alleviated for advanced high-k/metal-gate CMOS technology that employs ultra thin high-k film with an EOT smaller than 1.5 nm. 3.3.3. The failure distribution prediction of damaged-enhanced instability in BTI reliability From Eqs. (2)–(6), one can predict the functional dependence of the PBTI and NBTI degradation on plasma damage and the design parameters of AR and EOT. However, the amount of plasma damage may vary among transistors owing to different plasma conditions and values of AR, and EOT due to variations during processing. It is believed that all these process variations should follow normal distributions, resulting in a lognormal distribution of DVst from Eq. (2). Accordingly, from Eq. (3) it is expected that the variation in DNov (or DNit) during PID should follow a normal distribution across a wafer. The PBTI (or NBTI) lifetime is affected by the variation in DNov (or DNit) from Eqs. (4)–(6). By assuming a nominally identical AR and EOT, and with the further assumption of a normal distribution of DNov (l, r), a corresponding distribution of threshold voltage shift will be generated during PBTI stressing. Therefore, the mean value l and standard variation r of the distribution of DNov are both parameters dependent on AR, as

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1

High-k/metal-gate NMOSFETs EOT=2.0nm AR 3X (Data) AR 500X (Data) AR 500X (Model) AR 5000X (Data) AR 5000X (Model)

LN (-LN(1-F))

0

-1

-2

-3

-4

-5

PBTI Lifetime (arb.unit) Fig. 16. Simulation results of high-k/metal-gate NMOSFET PBTI lifetime distribution for various AR for transistors with EOT = 2.0 nm.

pact of plasma damage for high-k/metal-gate transistors, and shows that the dielectric degradation and transistor instability are strongly dependent on the EOT and antenna ratio. Reducing the EOT suppresses the gate dielectric degradation, and the damage becomes minor when the EOT is smaller than 2.0 nm. In addition, the damage becomes negligible when the EOT is smaller than 1.5 nm. This study also discusses the power–law relationship between antenna ratio and transistor PBTI lifetime and NBTI lifetime. Furthermore, NBTI degradations for PMOSFETs can be mitigated with damaged-enhanced electron trapping in oxygen vacancy during NBTI stress, showing a ‘‘reverse antenna effect”. This study further shows the failure distributions of transistor reliability deviate significantly from lognormal with increasing AR, as a result of plasma processing variation between transistors. In summary, this study demonstrates that plasma-induced damage can be alleviated for advanced high-k/metal gate CMOS transistors fabricated with thin dielectric thickness. References

2

1

LN (-LN(1-F))

0

SiO2/poly-gate PMOSFETs EOT=3.0nm

-1

-2

-3

-4

AR 3x (Data) AR 500x (Data) AR 500x (Model) AR 5000x (Data) AR 5000x (Model)

-5

NBTI Lifetime (arb. unit) Fig. 17. Simulation results of SiO2/poly-gate PMOSFET NBTI lifetime distribution for various AR for transistors with EOT = 3.0 nm.

shown in Eqs. (3) and (4). In this way, it is possible to construct a Monte Carlo simulation of the distributions of PBTI from the corresponding DNov distribution across the wafer. Fig. 16 shows the PBTI lifetime distribution for high-k/metal-gate transistors with EOT = 2.0 nm and Fig. 17 shows the NBTI lifetime distribution for SiO2/poly-gate transistors with EOT = 3.0 nm, respectively as a function of AR. In both cases, the simulated distributions are in good agreement with those determined experimentally. From Figs. 16 and 17, the impact of plasma damage on the transistor failure distribution is that it causes a severe distortion of the lognormal distribution at high percentiles. At low percentiles, the distribution slope is almost independent of AR, and failure times are reduced in accordance with Eqs. (2)–(6). Moreover, there is no indication in the experimental data of the presence of an early failure distribution arising from a defective subpopulation, as required for our proposed model.

4. Conclusions For both SiO2/poly-gate and high-k/metal-gate transistors, plasma-induced charging damage creates many defects and weakened bonds that can be easily damaged during reliability testing. Importantly, for high-k/metal-gate transistors, the damage current breaks the bonds of Hf-based dielectric and produces more oxygen-vacancy-related defects to enhance the instability of NBTI and PBTI. This study develops a comprehensive model of the im-

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