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A compensating nanosecond delay stabiliser
NUCLEAR
INSTRUMENTS
AND
METHODS
i36 (I976)
I69-t71;
©
NORTH-HOLLAND
PUBLISHING
CO.
A C O M P E N S A T I N G N A N O S E C O N D DELAY STABILISER K.D.
G R O S E a n d J. P. R [ P P O N *
Department of Physics, University of Birmingham, Birmingham BI5 2TT, England Received II M a r c h 1976 T h e design o f a feedback controlled stabiliser for a n a n o s e c o n d delay unit is described, and its application to timing experiments on accelerators is discussed.
1. Introduction In pulsed accelerator neutron experiments requiring knowledge of the beam burst timing, provision of suitable timing signals may be accomplished in a number of ways. The use of a capacitive time-pick off t) is widespread but suffers from the disadvantage that it cannot easily be used at low beam currents. The use of charged particles scattered from the main beam by a thin metal foil, or of prompt g a m m a rays from stops intercepting a fraction of the beam, generally results in a low efficiency, whilst the monitoring of target g a m m a rays may present problems both with geometry and with discrimination against g a m m a rays from other sources e.g. neutron capture after pulse injection. If, as in the present case, a cyclotron is used the rf itself can provide a time reference, and has the advantages that the efficiency is 100% and the timing pulse can always be from the same point in the cycle. The only disadvantage of using the cyclotron rf as a reference is that changes in machine parameters may alter the phase between the rf and extracted beam. Although such phase change may only represent a few nanoseconds change in timing, in the slowing down time measurements concerned / ) the times to be measured were of the same order as possible drift, so that such a shift was unacceptable. It was in order to overcome this problem that the delay stabiliser which uses a beam sampling technique to continually adjust the delay in an rf derived timing pulse, was designed. The timing pulse is then maintained in fixed phase with respect to the extracted beam.
stop, the timing output from this scintillator being used as the start pulse for a time to pulse height converter (TPHC). The stop pulse was derived from an rf pickup fed through a frequency selective wave-shaper, the latter being designed to minimise the influence of interference. These pulses were then fed into a master controller which used digital scaling and gating techniques to provide a range of output pulses with pre-settable delay and duration, the output being fed to the T H P C via the phase stabiliser to be described. The output from the T P H C was therefore related to the phase difference between the rf and the target pulse, the dispersion about the mean depending on the width of the burst, typically 5-7 ns fwhm. This output was divided and fed into two timing single channel analysers (TSCA) with windows set symmetrically to monitor the count rate either side of the peak of the beam burst (fig. I b). CYCLOTRONRF
~
~
P
U
[MASTER ~
L
S
E
R
ION SOURCE
INPUT
I [
~Anp . . . .
[ ~
]
CORRECTED
"OUTPUT
(a)
MONITORING
2. Experimental principles
The overall arrangement is shown schematically in fig. l a. Beam pulses arriving at the target were monitored using an NE 111 scintillator to detect gamma rays produced by stray beam on a graphite * N o w at the Nuclear Power Co. (Whetstone) Ltd, C a m b r i d g e Road, Whetstone, Leicester LE8 3LH, England.
T PHC
OUJ FUr
(b) Fig. I. (a) Block diagram o f the complete system. (b) Position o f the beam m o n i t o r i n g channels.
170
K.D.
GROSE
AND
The two outputs were then fed into a bi-directional scaler, one channel adding and the other subtracting so that for a constant, steady phase difference the net sum of the two count rates was zero. Any change in the phase therefore resulted in an imbalance in the count rate between the two channels: using the bi-directional scaler output to control a variable delay 3) therefore allowed variations in phase to be compensated for. 3. Circuit description The block and circuit diagrams for the phase staPRESET ~ , INPUTDECREASEDELAY~__~'Up Bi-DIRECTIONAL INPUTINCREASE DELAY| DOWNBBIT COUNTER
rJA[tlPl
DrGITAL ,0 ANALOGUE
I TIMINGPULSE
~
CONVERTER ~
.
>
CORRECTEDDELAYED TIMING PULSP
Fig. 2. Block diagram of the delay stabiliser.
lOOp TRI
ICI
INCREASE
ICI2
J.P.
RIPPON
biliser are shown in figs. 2 and 3. The TSCA pulses used to increase or decrease the delay are shaped to suitable TTL levels by emitter followers (TRI and 2R3) and Schmitt triggers (ICI and 2). These outputs are then fed into an 8-bit reversible counter (IC 28 and IC 30) either directly or via decade dividers (IC 8 and IC 9) allowing the device to be used over a wide range of input count rates whilst keeping count rate differences within the range of the reversible counter. The output of the reversible counter is then fed to a digital-toanalog converter (DAC, IC 29) with an output range 0-10 V. Operating the "preset" button sets the reversible counter to 2 6, the D A C output then being 5 V. The timing signal from the master controller is fed via an emitter follower (TR 2) to the first monostable (IC7) which has a fixed 100 pF timing capacitor. The charging current is determined by two factors, one being the setting of the D E L A Y potentiometer and the other the output of the preset R A N G E potentiometer, the setting of the latter being such as to provide a range
÷
IC18
C
DLOAD~O~fNAB
C LO/~] D
74193
-DECREASE
L_~?
I
'100p .. TR3
*
7490
'
INPUTS
LSB
PRESCALE + SELECTOF] Ix'
IC3
NISB
+15v @
IC19
IC 29
- ~5v
7490
IC 20
:5K6
RAN 1K
DELAY
÷ I TR4
+12v
IC5
IC16 i
2K2
lOO, ... J.I
OVE RbOA
STOP
1
lOOp
IC___6
IC 17
L~_ ~1
TIMINpTG I [
IUK ~
i÷
IC7
8
~.
÷
~2K2
1
~_~ " IO0p
741 21
Fig. 3. Circuit diagram of the delay stabiliser.
74121
100K
@
p
TR6 47 R 1 ---,w'~4: P
CORRECTED OUTPUT
COMPENSATING
NANOSECOND
of monostable pulse lengths, corresponding to the range of phase correction times. The falling edge of this monostable is then fed into a second monostable IC 17, providing standard length pulses to feed into the output amplifier. Thus, a change in the output voltage from the DAC arising from an imbalance in the count rate from the two monitoring TSCAs produces a change in the charging current of IC 7 which, in turn, alters the monostable pulse duration. The change in pulse duration is equal to the change in phase, so that C O R R E C T E D O U T P U T is a phase change compensated timing pulse. Clearly, when the correction is sufficient to equalise the count rates in the two monitoring channels the mean bi-directional scaler reading (and hence the D A C output voltage) will not necessarily be at the midpoint of its range. It is important, therefore, to know when the equilibrium point is getting near the end of the range, either top or bottom, since compensation will cease if it overflows its range. For this purpose, a meter is provided, to show the D A C output; automatic action is also taken to cope with this situation, as follows. In addition, if bits 2-7 of the scaler are all set or all not set - corresponding to operating near the top or bottom of its range one of the N A N D gates IC 20 or IC 16 will be activated. The output of these is used to inhibit further delay time changes and turn on a warning light. The experimenter may then turn the prescaler selector switch to O F F and reset the counter to its midpoint by means of the button. The D E L A Y control may be adjusted to bring the delay to the centre of the range if this occurs or correction may be made
DELAY STABILISER
171
whilst still running. A manual STOP switch is also provided. 4. Performance To test the performance of the phase delay stabiliser it was necessary to do so under operating conditions, since changes in the beam burst profile clearly affect the relative count rates in the monitoring channels, and hence the operation of the device. In order to provide significant phase changes in the cyclotron the magnetic field was altered to off resonance conditions, and the beam burst profile was measured with and without the stabiliser in operation. Without it there was a change in phase between the extreme conditions of 11.2 ns; with the stabiliser in operation this change was reduced to 0.9 ns. Were the beam burst to be always of the same shape the latter figure could be reduced even further, this small phase drift being entirely consistent with a change in beam profile accompanying the change in cyclotron running conditions. We should like to thank Dr M. Scott for his many suggestions and comments. The work described forms part of an SRC supported programme of neutron slowing down measurements, and this support is acknowledged with gratitude.
References 1) D. Maydan, Nucl. Instr. and Meth. 34 (1965) 229. 2) j. p. Rippon and M. C. Scott, J. Phys. D. 7 (1974) 2525. 3) K. D. Grose, J. Phys. E 4 (1970) 57.
INSTRUMENTS
AND
METHODS
i36 (I976)
I69-t71;
©
NORTH-HOLLAND
PUBLISHING
CO.
A C O M P E N S A T I N G N A N O S E C O N D DELAY STABILISER K.D.
G R O S E a n d J. P. R [ P P O N *
Department of Physics, University of Birmingham, Birmingham BI5 2TT, England Received II M a r c h 1976 T h e design o f a feedback controlled stabiliser for a n a n o s e c o n d delay unit is described, and its application to timing experiments on accelerators is discussed.
1. Introduction In pulsed accelerator neutron experiments requiring knowledge of the beam burst timing, provision of suitable timing signals may be accomplished in a number of ways. The use of a capacitive time-pick off t) is widespread but suffers from the disadvantage that it cannot easily be used at low beam currents. The use of charged particles scattered from the main beam by a thin metal foil, or of prompt g a m m a rays from stops intercepting a fraction of the beam, generally results in a low efficiency, whilst the monitoring of target g a m m a rays may present problems both with geometry and with discrimination against g a m m a rays from other sources e.g. neutron capture after pulse injection. If, as in the present case, a cyclotron is used the rf itself can provide a time reference, and has the advantages that the efficiency is 100% and the timing pulse can always be from the same point in the cycle. The only disadvantage of using the cyclotron rf as a reference is that changes in machine parameters may alter the phase between the rf and extracted beam. Although such phase change may only represent a few nanoseconds change in timing, in the slowing down time measurements concerned / ) the times to be measured were of the same order as possible drift, so that such a shift was unacceptable. It was in order to overcome this problem that the delay stabiliser which uses a beam sampling technique to continually adjust the delay in an rf derived timing pulse, was designed. The timing pulse is then maintained in fixed phase with respect to the extracted beam.
stop, the timing output from this scintillator being used as the start pulse for a time to pulse height converter (TPHC). The stop pulse was derived from an rf pickup fed through a frequency selective wave-shaper, the latter being designed to minimise the influence of interference. These pulses were then fed into a master controller which used digital scaling and gating techniques to provide a range of output pulses with pre-settable delay and duration, the output being fed to the T H P C via the phase stabiliser to be described. The output from the T P H C was therefore related to the phase difference between the rf and the target pulse, the dispersion about the mean depending on the width of the burst, typically 5-7 ns fwhm. This output was divided and fed into two timing single channel analysers (TSCA) with windows set symmetrically to monitor the count rate either side of the peak of the beam burst (fig. I b). CYCLOTRONRF
~
~
P
U
[MASTER ~
L
S
E
R
ION SOURCE
INPUT
I [
~Anp . . . .
[ ~
]
CORRECTED
"OUTPUT
(a)
MONITORING
2. Experimental principles
The overall arrangement is shown schematically in fig. l a. Beam pulses arriving at the target were monitored using an NE 111 scintillator to detect gamma rays produced by stray beam on a graphite * N o w at the Nuclear Power Co. (Whetstone) Ltd, C a m b r i d g e Road, Whetstone, Leicester LE8 3LH, England.
T PHC
OUJ FUr
(b) Fig. I. (a) Block diagram o f the complete system. (b) Position o f the beam m o n i t o r i n g channels.
170
K.D.
GROSE
AND
The two outputs were then fed into a bi-directional scaler, one channel adding and the other subtracting so that for a constant, steady phase difference the net sum of the two count rates was zero. Any change in the phase therefore resulted in an imbalance in the count rate between the two channels: using the bi-directional scaler output to control a variable delay 3) therefore allowed variations in phase to be compensated for. 3. Circuit description The block and circuit diagrams for the phase staPRESET ~ , INPUTDECREASEDELAY~__~'Up Bi-DIRECTIONAL INPUTINCREASE DELAY| DOWNBBIT COUNTER
rJA[tlPl
DrGITAL ,0 ANALOGUE
I TIMINGPULSE
~
CONVERTER ~
.
>
CORRECTEDDELAYED TIMING PULSP
Fig. 2. Block diagram of the delay stabiliser.
lOOp TRI
ICI
INCREASE
ICI2
J.P.
RIPPON
biliser are shown in figs. 2 and 3. The TSCA pulses used to increase or decrease the delay are shaped to suitable TTL levels by emitter followers (TRI and 2R3) and Schmitt triggers (ICI and 2). These outputs are then fed into an 8-bit reversible counter (IC 28 and IC 30) either directly or via decade dividers (IC 8 and IC 9) allowing the device to be used over a wide range of input count rates whilst keeping count rate differences within the range of the reversible counter. The output of the reversible counter is then fed to a digital-toanalog converter (DAC, IC 29) with an output range 0-10 V. Operating the "preset" button sets the reversible counter to 2 6, the D A C output then being 5 V. The timing signal from the master controller is fed via an emitter follower (TR 2) to the first monostable (IC7) which has a fixed 100 pF timing capacitor. The charging current is determined by two factors, one being the setting of the D E L A Y potentiometer and the other the output of the preset R A N G E potentiometer, the setting of the latter being such as to provide a range
÷
IC18
C
DLOAD~O~fNAB
C LO/~] D
74193
-DECREASE
L_~?
I
'100p .. TR3
*
7490
'
INPUTS
LSB
PRESCALE + SELECTOF] Ix'
IC3
NISB
+15v @
IC19
IC 29
- ~5v
7490
IC 20
:5K6
RAN 1K
DELAY
÷ I TR4
+12v
IC5
IC16 i
2K2
lOO, ... J.I
OVE RbOA
STOP
1
lOOp
IC___6
IC 17
L~_ ~1
TIMINpTG I [
IUK ~
i÷
IC7
8
~.
÷
~2K2
1
~_~ " IO0p
741 21
Fig. 3. Circuit diagram of the delay stabiliser.
74121
100K
@
p
TR6 47 R 1 ---,w'~4: P
CORRECTED OUTPUT
COMPENSATING
NANOSECOND
of monostable pulse lengths, corresponding to the range of phase correction times. The falling edge of this monostable is then fed into a second monostable IC 17, providing standard length pulses to feed into the output amplifier. Thus, a change in the output voltage from the DAC arising from an imbalance in the count rate from the two monitoring TSCAs produces a change in the charging current of IC 7 which, in turn, alters the monostable pulse duration. The change in pulse duration is equal to the change in phase, so that C O R R E C T E D O U T P U T is a phase change compensated timing pulse. Clearly, when the correction is sufficient to equalise the count rates in the two monitoring channels the mean bi-directional scaler reading (and hence the D A C output voltage) will not necessarily be at the midpoint of its range. It is important, therefore, to know when the equilibrium point is getting near the end of the range, either top or bottom, since compensation will cease if it overflows its range. For this purpose, a meter is provided, to show the D A C output; automatic action is also taken to cope with this situation, as follows. In addition, if bits 2-7 of the scaler are all set or all not set - corresponding to operating near the top or bottom of its range one of the N A N D gates IC 20 or IC 16 will be activated. The output of these is used to inhibit further delay time changes and turn on a warning light. The experimenter may then turn the prescaler selector switch to O F F and reset the counter to its midpoint by means of the button. The D E L A Y control may be adjusted to bring the delay to the centre of the range if this occurs or correction may be made
DELAY STABILISER
171
whilst still running. A manual STOP switch is also provided. 4. Performance To test the performance of the phase delay stabiliser it was necessary to do so under operating conditions, since changes in the beam burst profile clearly affect the relative count rates in the monitoring channels, and hence the operation of the device. In order to provide significant phase changes in the cyclotron the magnetic field was altered to off resonance conditions, and the beam burst profile was measured with and without the stabiliser in operation. Without it there was a change in phase between the extreme conditions of 11.2 ns; with the stabiliser in operation this change was reduced to 0.9 ns. Were the beam burst to be always of the same shape the latter figure could be reduced even further, this small phase drift being entirely consistent with a change in beam profile accompanying the change in cyclotron running conditions. We should like to thank Dr M. Scott for his many suggestions and comments. The work described forms part of an SRC supported programme of neutron slowing down measurements, and this support is acknowledged with gratitude.
References 1) D. Maydan, Nucl. Instr. and Meth. 34 (1965) 229. 2) j. p. Rippon and M. C. Scott, J. Phys. D. 7 (1974) 2525. 3) K. D. Grose, J. Phys. E 4 (1970) 57.