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A comprehensive approach to IC design and fabrication
194
World Abstracts on Microelectronics and Reliability
electron dynamics of GaAs to achieve ultralow propagation delay and/or ultralow power-delay product (dynamic switching energy) logic circuits. The intent of this paper is to give an overview of some of these GaAs device approaches, including their principal attractions, expected performance levels, etc. (Much more detailed analyses of some of these structures are presented in other papers in this issue.) This overview is extended to a comparison of the relative merits of these GaAs device approaches vis-fi-vis their applicability for achieving ultrahigh-speed logic of large-scale integration (LSI) or very large-scale integration (VLSI) levels of complexity (as opposed to simpler SSI/MSI applications ).
Silicon crystal growing needs vs. equipment. PIETER S. BURGGRAAF.Semiconductor Int., 33 (February 1982). Up-todate crystal growing furnaces seem capable of handling a decade of requirements. Six-inch diameters, nearly perfect crystals and more economical, safer production capabilities are available now. Integrated injection Iogic--a review of its status and prospects. LEIF HALBO. Microelectron. J. 13 (2), 5 (1982). In this paper the performance of Integrated Injection Logic (I2L) is reviewed, and its potential for on-chip combinations with other bipolar logic as well as analog circuitry and integrated sensors is discussed. Examples are given which demonstrate the wide variety of applications of |2L. New logic devices, based on the IZL concept are mentioned. An attempt is made to assess the role of IEL in the coming years.
LSI chip for monochrome TV steals the show from multiple ICs. GERALD K. LUNN. Electronics, 143 (10 March 1982). Replacing external capacitors with on-chip nitride devices. this bipolar circuit improves on the discrete-component picture at less cost. Combined analog/digital LS1 design using I2L gate arrays. ALAN B. GREBENE. Microelectron. J. 13 (2), 12 (1982). In the design of complex LSI systems, the Integrated Injection Logic (IEL) technology offers a unique advantage over MOS technologies: it can combine high-density logic arrays on the same monolithic chip with precision analog circuitry. Thus, it is ideally suited for designing LSI systems requiring both analog and digital circuitry on the same chip. This paper describes the features and the capabilities of an I/L semicustom IC chip particularly designed for combined analog/ digital LSI designs. The semi-custom IC, designated as the XR-400 Master-Chip, contains an array of 256 five-output I2L gates, along with a wide choice of linear bipolar components on the same monolithic chip.
A comprehensive approach to IC design and fabrication. GEROLD W. NEUDECK and MARK S. LUNDSTROM. IEEE Trans. Components Hybrids mfg Technol. CHMT-5 (1), 102 (1982). A comprehensive integrated circuit (IC) engineering curriculum is presented. The motivation for this curriculum and its implementation at Purdue University are discussed. The emphasis of the paper concerns two IC laboratory courses.
Gate arrays for VLSI design. DAVID E. FULKERSON. IEEE Trans. Components Hybrids mfy Technol. CHMT-5 (1), 133 (1982). Because of the increasing complexity of new integrated circuits (IC's) and the limited supply of IC designers. structured design approaches are necessary. A gate array is a common approach to structuring, formalizing, and thus simplifying the design process. Existing gate arrays in various technologies (ECL, CML, ISL, STL, S-TTL, NMOS, CMOS, I2L, and linear) are described in terms of structure, gate count, and gate delay. A new gate array (the GAB-4000) contains more than 4000 five-collector (I2L) gates. The GAB-4000 was designed for architectural flexibility and ease of layout. An entire microcontroller or microprocessor can be designed on one gate array chip. A new "wafer-scale" linear/digital master slice (the MSA-1000) is also described. The circuit emphasizes diode loads, active loads, and current sources rather than resistors. One can choose any chip size by sawing wherever desired.
Custom chip adds frequency to hand-held meter's repertoire. DAVID RYAN TAYLOR. Electronics, 119 (5 May 1982). CMOS measurement-acquisition chip controlled by a singlechip, 4-bit computer resolves frequency, voltage, and impedance to 4½ digits.
C-MOS chip set streamlines floating-point processing. FREDERICK WARE and WILLIAM MCALLISTER. Electronics, 149 (10 February 1982). VLS1 simplifies scalar, vector and array processor design while maintaining the speed of its discrete-component predecessors.
The SSTC integrated circuit facility. W. A. BOSENBERG.Solid St. Technol., 122 (March 1982). The Solid State Technology Center (SSTC) clean room has been upgraded over the last few years. The photoresist area is a class 100 vertical laminar flow room with tight temperature and humidity control. The main processing area has increased exhaust capabilities of 45,000 cfm with corresponding increased make-up air. A new 480 volt 2000kva distribution system has been installed for heavy users of electricity such as diffusion furnaces. Closed loop cooling of 200 gpm is provided for the process equipment. The chlorine fumes used for furnace cleaning are sucked into aspirators which use a separate 200gpm recirculation loop with pH control and purging of the salt solution when it exceeds a certain value. All common gases come from liquid sources and do not require further purification.
Computer-generated models abridge thermal analysis of packaged VLSI. MASOOD MURTUZA. Electronics, 145 (10 February 1982). A realistic calculation of thermal resistance takes package, socket and board factors into account.
Production techniques with S.O. packages. JOE RESENDES. Electron. Packaqin9 Prodn, 115 (March 1982). Surface mounted, small outline packages offer packaging engineers the opportunity to further miniaturize their products. How rapidly the components achieve wide use will depend on the availability of cost effective substrate assembly production techniques.
GIMOS--a nonvolatile MOS memory transistor. S. T. Hsu. RCA Rev. 42, 424 (198 l ). Characteristics of electrically alterable stacking gate nonvolatile MOS memory transistors are presented. The fabrication processes for this device is compatible with most MOS technologies. The memory mechanism is charge storage at the floating gate. The charges stored at the floating gate are injected into the floating gate from the control gate by the Fowler Nordheim tunneling process. This memory device is shown to have a very large memory window, extremely long retention time, and excellent endurance and temperature stability. Transistors have been fabricated in SOS technology. Threshold voltages for a self-aligned GIMOS p-channel device can be varied from + 15 V to - 2 5 V. Similar characteristics were obtained for n-channel transistors. Based on limited data the retention time is at least 1,000 years at room temperature. Transistors were stable after 20,000 write-erase cycles and 3 x 109 read cycles. Other stability data are also presented.
World Abstracts on Microelectronics and Reliability
electron dynamics of GaAs to achieve ultralow propagation delay and/or ultralow power-delay product (dynamic switching energy) logic circuits. The intent of this paper is to give an overview of some of these GaAs device approaches, including their principal attractions, expected performance levels, etc. (Much more detailed analyses of some of these structures are presented in other papers in this issue.) This overview is extended to a comparison of the relative merits of these GaAs device approaches vis-fi-vis their applicability for achieving ultrahigh-speed logic of large-scale integration (LSI) or very large-scale integration (VLSI) levels of complexity (as opposed to simpler SSI/MSI applications ).
Silicon crystal growing needs vs. equipment. PIETER S. BURGGRAAF.Semiconductor Int., 33 (February 1982). Up-todate crystal growing furnaces seem capable of handling a decade of requirements. Six-inch diameters, nearly perfect crystals and more economical, safer production capabilities are available now. Integrated injection Iogic--a review of its status and prospects. LEIF HALBO. Microelectron. J. 13 (2), 5 (1982). In this paper the performance of Integrated Injection Logic (I2L) is reviewed, and its potential for on-chip combinations with other bipolar logic as well as analog circuitry and integrated sensors is discussed. Examples are given which demonstrate the wide variety of applications of |2L. New logic devices, based on the IZL concept are mentioned. An attempt is made to assess the role of IEL in the coming years.
LSI chip for monochrome TV steals the show from multiple ICs. GERALD K. LUNN. Electronics, 143 (10 March 1982). Replacing external capacitors with on-chip nitride devices. this bipolar circuit improves on the discrete-component picture at less cost. Combined analog/digital LS1 design using I2L gate arrays. ALAN B. GREBENE. Microelectron. J. 13 (2), 12 (1982). In the design of complex LSI systems, the Integrated Injection Logic (IEL) technology offers a unique advantage over MOS technologies: it can combine high-density logic arrays on the same monolithic chip with precision analog circuitry. Thus, it is ideally suited for designing LSI systems requiring both analog and digital circuitry on the same chip. This paper describes the features and the capabilities of an I/L semicustom IC chip particularly designed for combined analog/ digital LSI designs. The semi-custom IC, designated as the XR-400 Master-Chip, contains an array of 256 five-output I2L gates, along with a wide choice of linear bipolar components on the same monolithic chip.
A comprehensive approach to IC design and fabrication. GEROLD W. NEUDECK and MARK S. LUNDSTROM. IEEE Trans. Components Hybrids mfg Technol. CHMT-5 (1), 102 (1982). A comprehensive integrated circuit (IC) engineering curriculum is presented. The motivation for this curriculum and its implementation at Purdue University are discussed. The emphasis of the paper concerns two IC laboratory courses.
Gate arrays for VLSI design. DAVID E. FULKERSON. IEEE Trans. Components Hybrids mfy Technol. CHMT-5 (1), 133 (1982). Because of the increasing complexity of new integrated circuits (IC's) and the limited supply of IC designers. structured design approaches are necessary. A gate array is a common approach to structuring, formalizing, and thus simplifying the design process. Existing gate arrays in various technologies (ECL, CML, ISL, STL, S-TTL, NMOS, CMOS, I2L, and linear) are described in terms of structure, gate count, and gate delay. A new gate array (the GAB-4000) contains more than 4000 five-collector (I2L) gates. The GAB-4000 was designed for architectural flexibility and ease of layout. An entire microcontroller or microprocessor can be designed on one gate array chip. A new "wafer-scale" linear/digital master slice (the MSA-1000) is also described. The circuit emphasizes diode loads, active loads, and current sources rather than resistors. One can choose any chip size by sawing wherever desired.
Custom chip adds frequency to hand-held meter's repertoire. DAVID RYAN TAYLOR. Electronics, 119 (5 May 1982). CMOS measurement-acquisition chip controlled by a singlechip, 4-bit computer resolves frequency, voltage, and impedance to 4½ digits.
C-MOS chip set streamlines floating-point processing. FREDERICK WARE and WILLIAM MCALLISTER. Electronics, 149 (10 February 1982). VLS1 simplifies scalar, vector and array processor design while maintaining the speed of its discrete-component predecessors.
The SSTC integrated circuit facility. W. A. BOSENBERG.Solid St. Technol., 122 (March 1982). The Solid State Technology Center (SSTC) clean room has been upgraded over the last few years. The photoresist area is a class 100 vertical laminar flow room with tight temperature and humidity control. The main processing area has increased exhaust capabilities of 45,000 cfm with corresponding increased make-up air. A new 480 volt 2000kva distribution system has been installed for heavy users of electricity such as diffusion furnaces. Closed loop cooling of 200 gpm is provided for the process equipment. The chlorine fumes used for furnace cleaning are sucked into aspirators which use a separate 200gpm recirculation loop with pH control and purging of the salt solution when it exceeds a certain value. All common gases come from liquid sources and do not require further purification.
Computer-generated models abridge thermal analysis of packaged VLSI. MASOOD MURTUZA. Electronics, 145 (10 February 1982). A realistic calculation of thermal resistance takes package, socket and board factors into account.
Production techniques with S.O. packages. JOE RESENDES. Electron. Packaqin9 Prodn, 115 (March 1982). Surface mounted, small outline packages offer packaging engineers the opportunity to further miniaturize their products. How rapidly the components achieve wide use will depend on the availability of cost effective substrate assembly production techniques.
GIMOS--a nonvolatile MOS memory transistor. S. T. Hsu. RCA Rev. 42, 424 (198 l ). Characteristics of electrically alterable stacking gate nonvolatile MOS memory transistors are presented. The fabrication processes for this device is compatible with most MOS technologies. The memory mechanism is charge storage at the floating gate. The charges stored at the floating gate are injected into the floating gate from the control gate by the Fowler Nordheim tunneling process. This memory device is shown to have a very large memory window, extremely long retention time, and excellent endurance and temperature stability. Transistors have been fabricated in SOS technology. Threshold voltages for a self-aligned GIMOS p-channel device can be varied from + 15 V to - 2 5 V. Similar characteristics were obtained for n-channel transistors. Based on limited data the retention time is at least 1,000 years at room temperature. Transistors were stable after 20,000 write-erase cycles and 3 x 109 read cycles. Other stability data are also presented.