- Email: [email protected]
A CONTROL BUS COMMUNICATION
IFAC MCPL 2007 The 4th International Federation of Automatic Control Conference on Management and Control of Production and Logistics September 27-30, Sibiu - Romania
A CONTROL BUS COMMUNICATION George Mahalu, Radu Pentiuc ”Ştefan cel Mare” Suceava University Electrical Engineering and Computer Science Department
Abstract: In this paper work are proposing some original solutions particular to the data transfer mean and protocols corresponding. The bus imagined has some specific features that conferring originally behaviours. The protocol involved is thinking in this application to working in logical mean with the hardware-designed structure. In this sense is performed entire hardware in relation with the signal type generated by the various kinds of sensors. Was be given attention to the adapting electronic signal structures like as an interface between sensors involved, from one the side, and the physical bus system (with all its conflict problems which can appear). In this paper work are proposing some original solutions particular to the data transfer mean and protocols corresponding. The bus imagined has some specific features that conferring originally behaviours. The protocol involved is thinking in this application to working in logical mean with the hardware-designed structure. In this sense is performed entire hardware in relation with the signal type generated by the various kinds of sensors. Was be given attention to the adapting electronic signal structures like as an interface between sensors involved, from one the side, and the physical bus system (with all its conflict problems which can appear). Copyright @ 2007 IFAC Keywords: bus, signal, transfer, protocol, synchronization .
1. INTRODUCTION
minimum transfer time and of the international electromagnetic compatibility actual norms; - using of the intelligent circuits which work into the master-slave tandem – request of the functional compatibility with the modern microprocessor/microcontroller system structures involved in the communication and processing data; - assure data transfer through a channel set with different physical nature and redundant functionality, that warn the informational link fault and rise the reliability of the data transfer and security mechanisms. From software viewpoint the system bus must respond to the actual access technologies and data security adapting requests, with implementing of the protocols and compatibilities between different management structure types.
The modern data process control has like necessary a high informational traffic. This is valuable both in the data quantity and the data velocity transfer and in this sense are involved some functionality requests which put in front the efficient arbiter and control protocols. All these specificity can rise an architectural problem set which resolving both hardware and software level. A data bus communication can constitutes a challenge for system designer. A same task imposes some features which use the compromise solutions. In this mode, from hardware viewpoint, a system bus request: -
minimize the number of physical lines – responding by the simplify of the field structure request, and implicit to the simplify of the all interfaces, of the
759
2. THE APPROACH SLUTION
-
In the try of identify the bus type which responds most of the above hardware and software requests, we focused about the I2C (Inter - Integrated Circuits) bus type. This bus uses three physical lines:
-
-
START – transition from 1 in 0 logical for SDA STOP – transition from 0 in 1 logical for SDA
The bus is considered busy after performed START condition and is considered set free after performed STOP condition. These signal combinations are generating by the master device (microsystem). In figure 2 is shown the above conditions. The data is transferred on the bus like packets of bits which called words. Most usual example of word is the byte. Each transferred word between transmitter
a data bidirectional line, noted SDA (Serial DAta); a clock bidirectional line, noted SCL (Serial CLock); a ground line, noted GND (GrouND).
VDD RP
RP
SDA SCL LCD-DRV
MEM μSA
DAC μSB
Fig. 1. More devices connected by I2C bus Each bus connected component is recognized by unique address and can function to the distinct times like a data transmitter/receiver in relation with the role played into system. To the I2C bus can be connected more master and slave devices. The initiative to execute one data bus transfer is of the master device. Each time, only one master device has the bus control and this will access only one slave device. The master-slave pair will make a data transfer from master to slave (writing regime) or from slave to master (reading regime). An example of bus connection by more devices is shown in the figure 1. The data and clock are bidirectional lines. The free state of these lines is 1 logical. The traffic participant devices are connected to all these lines through logical access gates of open collector (or open drain) type which performing the AND-cabled logical operator. The means of the notations are: -
and receiver is accompanied by one confirmation bit. In this mode transferring data on the word constitutes an easy controllable operation. More that, can be possible finding a way to speed transfer adapting between transmitter and receiver. For this, after word complete reception, just to next word reception time, receiver forcing in 0 logical the SCL line. Thus, the transmitter is switched into the wait state and data transfer is resumption after the SCL line clearance. The transfer confirmation is performed by the receiver device, using a clock pulse which is generated by the master, called confirmation bit. After the last bit transmitted on line, the transmitter will clearance the data line (SDA=1). If the receiver has correct received data, it will force the SDA line in 0 logical on during of the confirmation bit (figure 3). The master has duty to confirm this bit transmitting and operate consequently. Thus, if detected confirmation, it continues with a new transfer command (for next word). Contrary, and in non-existent data transferring case, the master device forcing the STOP condition and release the SDA line.
RP – polarizing resistor MEM – memory block LCD-DRV – LCD driver DAC – digital-analog converter μSA, μSB – microsystems VDD – supply voltage SDA – serial data signal SCL – serial clock signal
3. THE BUS SYNCHRONIZATION During data transferring bus, each master device must generating clock signal. After logical synthesis on all these signals is performed the active clock signal. This act consists into synchronization mechanism for all master devices function. Consequently, is performing finally bus access arbitration. The arbitration mechanism can be useful understand on the figure 4 chronograms base. The clock signal that was forced in 0 logical by one master device,
The bus control access is performed by one concurrent process. Gain of the control and set free of the bus are processes signalling on the following conditions (enabled by the 1 logical on the SCL):
760
release a measuring process for a tlow length on each device, parallel with forcing SCL line in the low
logical value. If the two values are identically the devices will perform the next bit transmitting,
SDA SDA
SCL
SCL
START condition
Enable data
STOP condition
Fig. 3. Transfer data on the I2C bus example
Fig. 2. START and STOP specification
state. After this length exhaustion, the master devices will release one by one the SCL line. When the last device it released this line switching on high state. The switching SCL line from 0 in 1 logical conducts to releasing a new measuring process for the thigh length when the SCL line is released (let in high state by the master devices). The first master device which will exhausts thigh length measuring will command the SCL line in low state so that will be take again generating for a new clock period on the SCL line. To clock signal bus generating and to synchronization performing will contribute all bus connected master devices. The clock signal obtained is characterized by: -
Actualize data permission
following the same procedure. Results that in the limit case when more master devices will transmit simultaneously same information is not necessary inhibition in access to bus line, for some those. Unlike above case, when one or more devices transmitting a logical different value that all those from other master devices, the mechanisms are different. We’ll considerate two master devices which begin transmitting simultaneously. On the n-th bit transmit the first master device (noted M1) puts 0 logical on the SDA line and the second master device (noted M2) puts 1 logical on the same line. Thanks the AND-cabled structures of the bus access circuits, the data line will set in 0 logical. Thus, the M2 master device will detect a difference between transmitted logical value and existent on line logical value. Consequently, the M2 master device will decouple from data line and the M1 master device continue to transmit without access arbitration process to affect the current transfer cycle. In figure 4 is shown time delivery of the arbitration process.
tlow – the SCL forced in low state length – is referred to most big tlow duration which is generated by the bus connected devices; thigh – the SCL forced in high state length – is referred to most small thigh duration which is generated by the bus connected devices. 4. BUS ACCESS ARBITRATION
5. BUS CONNECTED DEVICES ADDRESSING
After detecting STOP condition, two or more connected bus master devices trying -sometimes simultaneous - to gain the bus control. In these situations is necessary to act an arbitration protocol which must solution all confliction states. The major advantages of approach solution of the I2C bus consist in arbitration management parallel with data transferring. The initiating arbitration protocol premises are:
Each slave device has allocated a unique address or a group address. When a master device gain the bus access will specify the slave device’s address with it whish communicate. This address is allocated to each device from the system, into united mode. The slave device address is specified on seven bits - in standard format, or on ten bits - in extended format. The format is specified in the communication protocol prescriptions. On other hand, the START and STOP pulses can be presets for a specific protocol kind, and this fact leads to the change of the command line. Into oscilloscope visualization performing, the synchronization of the signal trace cannot be performing because those two pulses broking the word’s periodicity. From these cases, the dynamical debugging is a difficult operation. If the electronic hardware part is performing with an 8-bit microcontroller board (like as PCB80C553
synchronization performing at bus level; performing AND-cabled logical operator by the access structures of the transmitter devices on SDA line. In the above example, the two master devices, synchronized, will provide the first bit on the data line. Another hand, the master devices will compare the transmitted logical value with the SDA attached state -
761
Philips), all the presets are implemented into software part of the system. The M2 device lose the bus access
SDA1 SDA2 SCL
Fig. 4. The bus access arbitration
The addressing process is same delivered: -
-
-
-
-
for example, the form: 1010XXX. In this mode we can allocate a group of eight devices like as RAM or EEPROM memories. Through the three last significant bits – noted XXX – is possible to specify an address into the group.
a master device whish to initiate a transfer after arise the STOP condition detected on the bus, forcing the START condition; the master device will provide in line, successive, the seven address bits of the slave device with it whish to change data; the bus connected slave devices which are in function, after the START condition detected on bus, will serial receiving the seven master’s transmitted address bits; after reception of the seven address bits, each slave device will compare the received bits with own address and because an address is allocated to only one slave device result that only one device will recognize own address; the next master’s transmitted bit will point the transfer direction (from master to slave in transmitting mode or from slave to master in receiving mode); the master device will release the data line and SDA switch in 1 logical; if address was be recognized by the slave device then it will force the data line in 0 logical on during of the clock pulse provided by the master device, and point so own address recognition and accepting transfer direction; if address was not be recognized by any slave device then SDA line stand in 1; logical on the next clock pulse length and point to master device that addressed devices is non-existent, and thus the master device will end the current transfer cycle forcing on the bus the STOP condition.
6. EXTENDED BUS DESIGNING An extended bus, at structural and functional level, will be configured in accord with following requests: -
-
-
-
-
assuring more many physical independent channels – different by nature an physical functional principle, but not like logical principle – used like as support for bus implementation; implementing at each channel level a protocol which is derived by that specific for I2C bus (in accord with the physical considered channel features); designing an functional coherent assuring techniques (at logical level) between the physical involved channels; designing some physical adapter structures with the physical channel of communication for the transfer involved devices; assuring data transfer and control signals protection (not-necessary for all channels simultaneously) in accord with perturbations; assuring traffic security on the bus. 7. BTHE SAUB IMPLEMENTATION
Into SAUB (Self-Arbitration Universal Bus) designing can be provided some distinctly physical channel with redundancy, such as:
Following way of address allocation become possible to connect more similar devices to bus. Each device belong to devices group for was be allocate an address domain. An address domain has,
762
electric lines; radio channels;
-
ultra-acoustic fields; infrared bands; laser fields.
The main modulation methods used in SSS techniques can be mentioned:
The transfer at the electrical lines is in accord with standard specifications for the classical I2C bus. The special problems that can rise are those specific to the parasite signals and to the electromagnetic compatibility considerations in relation with the ambient electronic equipments. In the radio communication case the problems which can rise can be multiple. Thus, is possible to appear the decision about spectral radiation field structure and type of modulation using. We selected for our design a spread spectrum system (SSS) case of implementation. The features for same system are:
-
-
-
the transmit signal band is bigger then data signal band; the transmitted band must be determined by an independent by message function, known at reception so.
direct sequence technique (DS) – consists in modulating main wave directly with the code pseudo-random sequence (PS); frequency hopping technique (FH) – represent a method of jamming avoid which switching permanently – into known rate – transmitted frequency, with the switching PS speed – named jump speed; time hopping technique (TH) – is referred by pulse modulation so that the pulse transmitter moments must be pseudorandom moments; pulsing FM technique (chirp) – consist in frequency modulation in accord with different rules, during some periodical pulses, resulting thus a complex large band signal;
ANT m(t)
ERROR CORECTOR CODE
1 bit
FREQUENCY SYNTHESIZER
u(t)
FREQUENCY MULTIPLICATOR
m-1 bits clock
PS GENERATOR
Fig. 5. The block schema for a SSS-FH transmitter
The main features of the SSS techniques are: -
-
-
-
high level of jamming/interference immunity degree, based on the big value of multiplicity factor which oblige jamming techniques to be independently of the signal characteristics; high security level of communications, specific to big value for the multiplicity factor, transmitting signal unpredictability and relative power spectrum which is uniform into large band; fine resolution in time, thanks correlate SSS signals reception; private character of the SSS transmissions, impose only persons that not known the pseudo-random code; multiple access possibility which is permit by using of different transmitter-receiver couples into orthogonally signals system, those working simultaneously into the same frequency band without secondary interferences.
hybrid techniques (DS-FH, FH-DS-TH, DS-TH etc.) – those are used in complex SSS with multiple access and special performances.
The option that was be made in SAUB design consists in the frequency hopping technique, using the discrete frequency modulation MFSK (Multiple Frequency Shift-Keying). This solution assume that using some proper circuits the frequency transmitting for very short time to be switched with a jump speed that is equal with the PS code. The successive values of frequency following the PS code that it commands the synthesizer. In this mode is assured unpredictable character and the large band for the transmitted signal. The typical block schema for a SSS-FH transmitter is shown in figure 5. SSS-FH systems are delivered in low rate frequency systems (LR) and high rate frequency systems (HR). In SSS-FH-HR systems case, the switching frequency speed is bigger then message speed (measured in bits/s). In SSS-FH-LR systems case, the
763
From possible solutions was be selected I2C type, extended to situation that in addition to classical used channel (electrical channel) appear new channels, with different physical nature, like as supplementary radio-channel SSS-FH with binary FSK modulation.
switching frequency speed is smaller then message speed. The frequency synthesizer performing one from those M=2m allocated frequencies for all distinctly m bits combinations. One bit is performed by message and rest of m-1 bits are generated by the PS code. If bit which is provided by message is the last significance bit then modification will products least frequency deviation, so that the output signal can be considered with binary FSK type. The rest of m-1 bits provided by the PS code generator will determine the jump signal in all possible frequency domains. Because selected solution is binary FSK modulation, must be fixed priority rule for transmitting signal in access of data bus line. For the extended bus which we design, the priority logical value is 0. In radio line case when transmitter working on the “all or nothing” principle, the priority signal is the active
REFERENCES 1. 2. 3.
Mihalcea, A., Şerbănescu, A. and Tabarcea, P. (1992). Sisteme moderne de comunicaţie, Editura Militară, Bucureşti. Creangă, I. and Pui, C. (1997). Microprocesoare de comenzi din receptoare TV, Editura Teora, Bucureşti. Mahalu, G. And Ciufudean, C. (2002). Radio-Transmitter System for PC Controlled Structures, Proceedings of the Second European Conference on Intelligent Systems and Technologies ECIT 2002, Iaşi,
RS SDA1 SDA2 SCL Fig. 6. The RF signal adapting to data electrical SAUB line signal (transmitting) and not the passive signal (pause in transmitting). Thus, the adapting circuits between the radio channel and the electrical data of SAUB will must implement the impose priority rule, so that signal chronogram shown like in figure 6. In figure above was assumed that radio-signal (RS) adapting to electrical data SAUB line is performed by an electronic structure which forcing output in low state when in the input is applied RS signal and switching in high state when the RS signal is null. The RS signal can be considered a data line implementing on the radio support. This line respects the priority rule in access if the RS state has in
4.
5.
correspondence 0 logical and the RS state has in correspondence 1 logical. In this mode, the result signal after adapting is noted SDA1. This signal can be processing together other signals (SDA2), like we seen above. Evidently, an adapter circuit with inverse function will be used when is necessary to make translate between electrical signal from SDA line and RS correspondent signal.
6.
CONCLUSIONS The SAUB design imposes a series of functional considerations, at physical level and at logical level respectively, specifying the conditions when a same bus can be used with a multiple physical channels support.
7.
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July 17-20, ISBN 973-8075-20-3, CD recorded. Mahalu, G., Graur, A. and Ciufudean, C. (2003). Virtual Interface in Control and Measurement Instrumentation, XIII-th International Symposium on Electrical Apparatus and Technologies SIELA 2003, Plovdiv, May 29-30, vol.I, pg. 147-151, ISBN 954-90209-2-4, Plovdiv, Bulgaria. Mahalu, G., Graur, A., Ciufudean, C. (2002). PC Signal Acquisition and Control Board for Technological Processes, ELMA, IEEE Section Bulgaria, Tenth International Conference on Electrical Machines, Drives and Power Systems, Sofia, Bulgaria, ISBN 954-902-091-6, vol.1, pp.263-268. Mahalu, G., Graur, A., Ciufudean, C., Pentiuc, R., Ioachim, P., Milici, M. and Milici, D. (2002). Intelligent Driver System for Technological Processes, ELMA, IEEE section Bulgaria, Tenth International Conference on Electrical Machines, Drives and Power Systems, Sofia, Bulgaria, vol.1, ISBN 954-902-091-6, pp.281-285. Mahalu, G., Graur, A. and Popa, V. (2006). Bus Communication in Robot System Control, CLAWAR 2005, Part 4, Springer Berlin Heidelberg, pp.229-236.
A CONTROL BUS COMMUNICATION George Mahalu, Radu Pentiuc ”Ştefan cel Mare” Suceava University Electrical Engineering and Computer Science Department
Abstract: In this paper work are proposing some original solutions particular to the data transfer mean and protocols corresponding. The bus imagined has some specific features that conferring originally behaviours. The protocol involved is thinking in this application to working in logical mean with the hardware-designed structure. In this sense is performed entire hardware in relation with the signal type generated by the various kinds of sensors. Was be given attention to the adapting electronic signal structures like as an interface between sensors involved, from one the side, and the physical bus system (with all its conflict problems which can appear). In this paper work are proposing some original solutions particular to the data transfer mean and protocols corresponding. The bus imagined has some specific features that conferring originally behaviours. The protocol involved is thinking in this application to working in logical mean with the hardware-designed structure. In this sense is performed entire hardware in relation with the signal type generated by the various kinds of sensors. Was be given attention to the adapting electronic signal structures like as an interface between sensors involved, from one the side, and the physical bus system (with all its conflict problems which can appear). Copyright @ 2007 IFAC Keywords: bus, signal, transfer, protocol, synchronization .
1. INTRODUCTION
minimum transfer time and of the international electromagnetic compatibility actual norms; - using of the intelligent circuits which work into the master-slave tandem – request of the functional compatibility with the modern microprocessor/microcontroller system structures involved in the communication and processing data; - assure data transfer through a channel set with different physical nature and redundant functionality, that warn the informational link fault and rise the reliability of the data transfer and security mechanisms. From software viewpoint the system bus must respond to the actual access technologies and data security adapting requests, with implementing of the protocols and compatibilities between different management structure types.
The modern data process control has like necessary a high informational traffic. This is valuable both in the data quantity and the data velocity transfer and in this sense are involved some functionality requests which put in front the efficient arbiter and control protocols. All these specificity can rise an architectural problem set which resolving both hardware and software level. A data bus communication can constitutes a challenge for system designer. A same task imposes some features which use the compromise solutions. In this mode, from hardware viewpoint, a system bus request: -
minimize the number of physical lines – responding by the simplify of the field structure request, and implicit to the simplify of the all interfaces, of the
759
2. THE APPROACH SLUTION
-
In the try of identify the bus type which responds most of the above hardware and software requests, we focused about the I2C (Inter - Integrated Circuits) bus type. This bus uses three physical lines:
-
-
START – transition from 1 in 0 logical for SDA STOP – transition from 0 in 1 logical for SDA
The bus is considered busy after performed START condition and is considered set free after performed STOP condition. These signal combinations are generating by the master device (microsystem). In figure 2 is shown the above conditions. The data is transferred on the bus like packets of bits which called words. Most usual example of word is the byte. Each transferred word between transmitter
a data bidirectional line, noted SDA (Serial DAta); a clock bidirectional line, noted SCL (Serial CLock); a ground line, noted GND (GrouND).
VDD RP
RP
SDA SCL LCD-DRV
MEM μSA
DAC μSB
Fig. 1. More devices connected by I2C bus Each bus connected component is recognized by unique address and can function to the distinct times like a data transmitter/receiver in relation with the role played into system. To the I2C bus can be connected more master and slave devices. The initiative to execute one data bus transfer is of the master device. Each time, only one master device has the bus control and this will access only one slave device. The master-slave pair will make a data transfer from master to slave (writing regime) or from slave to master (reading regime). An example of bus connection by more devices is shown in the figure 1. The data and clock are bidirectional lines. The free state of these lines is 1 logical. The traffic participant devices are connected to all these lines through logical access gates of open collector (or open drain) type which performing the AND-cabled logical operator. The means of the notations are: -
and receiver is accompanied by one confirmation bit. In this mode transferring data on the word constitutes an easy controllable operation. More that, can be possible finding a way to speed transfer adapting between transmitter and receiver. For this, after word complete reception, just to next word reception time, receiver forcing in 0 logical the SCL line. Thus, the transmitter is switched into the wait state and data transfer is resumption after the SCL line clearance. The transfer confirmation is performed by the receiver device, using a clock pulse which is generated by the master, called confirmation bit. After the last bit transmitted on line, the transmitter will clearance the data line (SDA=1). If the receiver has correct received data, it will force the SDA line in 0 logical on during of the confirmation bit (figure 3). The master has duty to confirm this bit transmitting and operate consequently. Thus, if detected confirmation, it continues with a new transfer command (for next word). Contrary, and in non-existent data transferring case, the master device forcing the STOP condition and release the SDA line.
RP – polarizing resistor MEM – memory block LCD-DRV – LCD driver DAC – digital-analog converter μSA, μSB – microsystems VDD – supply voltage SDA – serial data signal SCL – serial clock signal
3. THE BUS SYNCHRONIZATION During data transferring bus, each master device must generating clock signal. After logical synthesis on all these signals is performed the active clock signal. This act consists into synchronization mechanism for all master devices function. Consequently, is performing finally bus access arbitration. The arbitration mechanism can be useful understand on the figure 4 chronograms base. The clock signal that was forced in 0 logical by one master device,
The bus control access is performed by one concurrent process. Gain of the control and set free of the bus are processes signalling on the following conditions (enabled by the 1 logical on the SCL):
760
release a measuring process for a tlow length on each device, parallel with forcing SCL line in the low
logical value. If the two values are identically the devices will perform the next bit transmitting,
SDA SDA
SCL
SCL
START condition
Enable data
STOP condition
Fig. 3. Transfer data on the I2C bus example
Fig. 2. START and STOP specification
state. After this length exhaustion, the master devices will release one by one the SCL line. When the last device it released this line switching on high state. The switching SCL line from 0 in 1 logical conducts to releasing a new measuring process for the thigh length when the SCL line is released (let in high state by the master devices). The first master device which will exhausts thigh length measuring will command the SCL line in low state so that will be take again generating for a new clock period on the SCL line. To clock signal bus generating and to synchronization performing will contribute all bus connected master devices. The clock signal obtained is characterized by: -
Actualize data permission
following the same procedure. Results that in the limit case when more master devices will transmit simultaneously same information is not necessary inhibition in access to bus line, for some those. Unlike above case, when one or more devices transmitting a logical different value that all those from other master devices, the mechanisms are different. We’ll considerate two master devices which begin transmitting simultaneously. On the n-th bit transmit the first master device (noted M1) puts 0 logical on the SDA line and the second master device (noted M2) puts 1 logical on the same line. Thanks the AND-cabled structures of the bus access circuits, the data line will set in 0 logical. Thus, the M2 master device will detect a difference between transmitted logical value and existent on line logical value. Consequently, the M2 master device will decouple from data line and the M1 master device continue to transmit without access arbitration process to affect the current transfer cycle. In figure 4 is shown time delivery of the arbitration process.
tlow – the SCL forced in low state length – is referred to most big tlow duration which is generated by the bus connected devices; thigh – the SCL forced in high state length – is referred to most small thigh duration which is generated by the bus connected devices. 4. BUS ACCESS ARBITRATION
5. BUS CONNECTED DEVICES ADDRESSING
After detecting STOP condition, two or more connected bus master devices trying -sometimes simultaneous - to gain the bus control. In these situations is necessary to act an arbitration protocol which must solution all confliction states. The major advantages of approach solution of the I2C bus consist in arbitration management parallel with data transferring. The initiating arbitration protocol premises are:
Each slave device has allocated a unique address or a group address. When a master device gain the bus access will specify the slave device’s address with it whish communicate. This address is allocated to each device from the system, into united mode. The slave device address is specified on seven bits - in standard format, or on ten bits - in extended format. The format is specified in the communication protocol prescriptions. On other hand, the START and STOP pulses can be presets for a specific protocol kind, and this fact leads to the change of the command line. Into oscilloscope visualization performing, the synchronization of the signal trace cannot be performing because those two pulses broking the word’s periodicity. From these cases, the dynamical debugging is a difficult operation. If the electronic hardware part is performing with an 8-bit microcontroller board (like as PCB80C553
synchronization performing at bus level; performing AND-cabled logical operator by the access structures of the transmitter devices on SDA line. In the above example, the two master devices, synchronized, will provide the first bit on the data line. Another hand, the master devices will compare the transmitted logical value with the SDA attached state -
761
Philips), all the presets are implemented into software part of the system. The M2 device lose the bus access
SDA1 SDA2 SCL
Fig. 4. The bus access arbitration
The addressing process is same delivered: -
-
-
-
-
for example, the form: 1010XXX. In this mode we can allocate a group of eight devices like as RAM or EEPROM memories. Through the three last significant bits – noted XXX – is possible to specify an address into the group.
a master device whish to initiate a transfer after arise the STOP condition detected on the bus, forcing the START condition; the master device will provide in line, successive, the seven address bits of the slave device with it whish to change data; the bus connected slave devices which are in function, after the START condition detected on bus, will serial receiving the seven master’s transmitted address bits; after reception of the seven address bits, each slave device will compare the received bits with own address and because an address is allocated to only one slave device result that only one device will recognize own address; the next master’s transmitted bit will point the transfer direction (from master to slave in transmitting mode or from slave to master in receiving mode); the master device will release the data line and SDA switch in 1 logical; if address was be recognized by the slave device then it will force the data line in 0 logical on during of the clock pulse provided by the master device, and point so own address recognition and accepting transfer direction; if address was not be recognized by any slave device then SDA line stand in 1; logical on the next clock pulse length and point to master device that addressed devices is non-existent, and thus the master device will end the current transfer cycle forcing on the bus the STOP condition.
6. EXTENDED BUS DESIGNING An extended bus, at structural and functional level, will be configured in accord with following requests: -
-
-
-
-
assuring more many physical independent channels – different by nature an physical functional principle, but not like logical principle – used like as support for bus implementation; implementing at each channel level a protocol which is derived by that specific for I2C bus (in accord with the physical considered channel features); designing an functional coherent assuring techniques (at logical level) between the physical involved channels; designing some physical adapter structures with the physical channel of communication for the transfer involved devices; assuring data transfer and control signals protection (not-necessary for all channels simultaneously) in accord with perturbations; assuring traffic security on the bus. 7. BTHE SAUB IMPLEMENTATION
Into SAUB (Self-Arbitration Universal Bus) designing can be provided some distinctly physical channel with redundancy, such as:
Following way of address allocation become possible to connect more similar devices to bus. Each device belong to devices group for was be allocate an address domain. An address domain has,
762
electric lines; radio channels;
-
ultra-acoustic fields; infrared bands; laser fields.
The main modulation methods used in SSS techniques can be mentioned:
The transfer at the electrical lines is in accord with standard specifications for the classical I2C bus. The special problems that can rise are those specific to the parasite signals and to the electromagnetic compatibility considerations in relation with the ambient electronic equipments. In the radio communication case the problems which can rise can be multiple. Thus, is possible to appear the decision about spectral radiation field structure and type of modulation using. We selected for our design a spread spectrum system (SSS) case of implementation. The features for same system are:
-
-
-
the transmit signal band is bigger then data signal band; the transmitted band must be determined by an independent by message function, known at reception so.
direct sequence technique (DS) – consists in modulating main wave directly with the code pseudo-random sequence (PS); frequency hopping technique (FH) – represent a method of jamming avoid which switching permanently – into known rate – transmitted frequency, with the switching PS speed – named jump speed; time hopping technique (TH) – is referred by pulse modulation so that the pulse transmitter moments must be pseudorandom moments; pulsing FM technique (chirp) – consist in frequency modulation in accord with different rules, during some periodical pulses, resulting thus a complex large band signal;
ANT m(t)
ERROR CORECTOR CODE
1 bit
FREQUENCY SYNTHESIZER
u(t)
FREQUENCY MULTIPLICATOR
m-1 bits clock
PS GENERATOR
Fig. 5. The block schema for a SSS-FH transmitter
The main features of the SSS techniques are: -
-
-
-
high level of jamming/interference immunity degree, based on the big value of multiplicity factor which oblige jamming techniques to be independently of the signal characteristics; high security level of communications, specific to big value for the multiplicity factor, transmitting signal unpredictability and relative power spectrum which is uniform into large band; fine resolution in time, thanks correlate SSS signals reception; private character of the SSS transmissions, impose only persons that not known the pseudo-random code; multiple access possibility which is permit by using of different transmitter-receiver couples into orthogonally signals system, those working simultaneously into the same frequency band without secondary interferences.
hybrid techniques (DS-FH, FH-DS-TH, DS-TH etc.) – those are used in complex SSS with multiple access and special performances.
The option that was be made in SAUB design consists in the frequency hopping technique, using the discrete frequency modulation MFSK (Multiple Frequency Shift-Keying). This solution assume that using some proper circuits the frequency transmitting for very short time to be switched with a jump speed that is equal with the PS code. The successive values of frequency following the PS code that it commands the synthesizer. In this mode is assured unpredictable character and the large band for the transmitted signal. The typical block schema for a SSS-FH transmitter is shown in figure 5. SSS-FH systems are delivered in low rate frequency systems (LR) and high rate frequency systems (HR). In SSS-FH-HR systems case, the switching frequency speed is bigger then message speed (measured in bits/s). In SSS-FH-LR systems case, the
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From possible solutions was be selected I2C type, extended to situation that in addition to classical used channel (electrical channel) appear new channels, with different physical nature, like as supplementary radio-channel SSS-FH with binary FSK modulation.
switching frequency speed is smaller then message speed. The frequency synthesizer performing one from those M=2m allocated frequencies for all distinctly m bits combinations. One bit is performed by message and rest of m-1 bits are generated by the PS code. If bit which is provided by message is the last significance bit then modification will products least frequency deviation, so that the output signal can be considered with binary FSK type. The rest of m-1 bits provided by the PS code generator will determine the jump signal in all possible frequency domains. Because selected solution is binary FSK modulation, must be fixed priority rule for transmitting signal in access of data bus line. For the extended bus which we design, the priority logical value is 0. In radio line case when transmitter working on the “all or nothing” principle, the priority signal is the active
REFERENCES 1. 2. 3.
Mihalcea, A., Şerbănescu, A. and Tabarcea, P. (1992). Sisteme moderne de comunicaţie, Editura Militară, Bucureşti. Creangă, I. and Pui, C. (1997). Microprocesoare de comenzi din receptoare TV, Editura Teora, Bucureşti. Mahalu, G. And Ciufudean, C. (2002). Radio-Transmitter System for PC Controlled Structures, Proceedings of the Second European Conference on Intelligent Systems and Technologies ECIT 2002, Iaşi,
RS SDA1 SDA2 SCL Fig. 6. The RF signal adapting to data electrical SAUB line signal (transmitting) and not the passive signal (pause in transmitting). Thus, the adapting circuits between the radio channel and the electrical data of SAUB will must implement the impose priority rule, so that signal chronogram shown like in figure 6. In figure above was assumed that radio-signal (RS) adapting to electrical data SAUB line is performed by an electronic structure which forcing output in low state when in the input is applied RS signal and switching in high state when the RS signal is null. The RS signal can be considered a data line implementing on the radio support. This line respects the priority rule in access if the RS state has in
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correspondence 0 logical and the RS state has in correspondence 1 logical. In this mode, the result signal after adapting is noted SDA1. This signal can be processing together other signals (SDA2), like we seen above. Evidently, an adapter circuit with inverse function will be used when is necessary to make translate between electrical signal from SDA line and RS correspondent signal.
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CONCLUSIONS The SAUB design imposes a series of functional considerations, at physical level and at logical level respectively, specifying the conditions when a same bus can be used with a multiple physical channels support.
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July 17-20, ISBN 973-8075-20-3, CD recorded. Mahalu, G., Graur, A. and Ciufudean, C. (2003). Virtual Interface in Control and Measurement Instrumentation, XIII-th International Symposium on Electrical Apparatus and Technologies SIELA 2003, Plovdiv, May 29-30, vol.I, pg. 147-151, ISBN 954-90209-2-4, Plovdiv, Bulgaria. Mahalu, G., Graur, A., Ciufudean, C. (2002). PC Signal Acquisition and Control Board for Technological Processes, ELMA, IEEE Section Bulgaria, Tenth International Conference on Electrical Machines, Drives and Power Systems, Sofia, Bulgaria, ISBN 954-902-091-6, vol.1, pp.263-268. Mahalu, G., Graur, A., Ciufudean, C., Pentiuc, R., Ioachim, P., Milici, M. and Milici, D. (2002). Intelligent Driver System for Technological Processes, ELMA, IEEE section Bulgaria, Tenth International Conference on Electrical Machines, Drives and Power Systems, Sofia, Bulgaria, vol.1, ISBN 954-902-091-6, pp.281-285. Mahalu, G., Graur, A. and Popa, V. (2006). Bus Communication in Robot System Control, CLAWAR 2005, Part 4, Springer Berlin Heidelberg, pp.229-236.