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A cross coupled low phase noise oscillator using an output swing enhancement technique
Microelectronics Journal 45 (2014) 1008–1013
Contents lists available at ScienceDirect
Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
A cross coupled low phase noise oscillator using an output swing enhancement technique Mohammad Bagheri a,n, Ahmad Ghanaatian a, Adib Abrishamifar a, Mahmoud Kamarei b a b
Department of Electrical Engineering, University of Science and Technology, Tehran, Iran Department of Electrical and Computer Engineering, University of Tehran, Tehran, Iran
art ic l e i nf o
a b s t r a c t
Article history: Received 23 December 2013 Received in revised form 12 April 2014 Accepted 18 April 2014
A new voltage controlled oscillator (VCO) in a 0.18 μm CMOS process is offered in this paper. This paper's argument is to provide an innovative approach to improve the phase noise which is one of the most controversial issues in VCOs. Contrary to most ideas that have been put forward to decrease phase noise which are based on higher current dissipation to increase output voltage swing, this new method offers better specifications with respect to traditional solutions. The presented circuit is capable of extra oscillation amplitude without increasing the current level, taking advantages of tail current elimination and topology optimization. Analysis of the presented peak voltage amplitude can verify the optimum performance of the proposed. Post-layout simulation results at 2.3 GHz with an offset frequency of 1 MHz and 3 MHz show a phase noise of about 125 dBc/Hz and 136.5 dBc/Hz, respectively, with the current of 1.3 mA from 1.8 V supply. Also, Monte Carlo simulation is used to ensure the sensitivity of the proposed circuit to process and frequency variations are very promising. & 2014 Elsevier Ltd. All rights reserved.
Keywords: Voltage controlled oscillator Ultra low phase noise
1. Introduction Local oscillators or crystals in traditional ways were often used for various applications which cannot meet nowadays dominant criteria, like low cost, small size, and low power consumption. As it seems impossible to put the frequency crystal on-chip, designing a crystal-less oscillator with an appropriate phase noise is attractive for future RF technology. Some different techniques have been used to overcome the inaccuracy issue of crystal-less oscillators. In order to achieve an acceptable phase noise performance in a VCO, some key factors such as temperature, supply voltage, and process variation should be considered. In 2009, Mcorquodale et al. [1] used a complementary structure for the oscillator. Using advantage of a feedback from a frequency divider, a novel compensator circuit, and a band gap reference circuit with the 2nd order temperature-coefficient compensation, Mcorquodale et al. [1] could achieve a brilliant phase noise as well as a jitter level just like crystal oscillators. With this innovating feedback and complex structure which improve the phase noise and jitter as well, high dissipating power and current are inevitable.
n
Corresponding author. E-mail address: [email protected] (M. Bagheri).
http://dx.doi.org/10.1016/j.mejo.2014.04.018 0026-2692/& 2014 Elsevier Ltd. All rights reserved.
In theory, increasing quality factor can be mentioned as one of the effective ways to gain the proper phase noise in LC oscillators. But, the technology properties limit the improvement of Q in the tank [2–4]. Therefore, it could not be regarded as a certain way in all technologies. Another possible method to decrease the phase noise in crystal-less oscillators is eliminating the tail current as a main factor in the oscillators final phase noise [5]. Also, a capacitor and an inductor should be placed in the tail part of the circuit. These passive elements work as a filter of the 2nd tail current harmonic which mainly affects the output phase noise. However, these components will make the final circuit somewhere big in size. In 2011, Brown et al. [6] replaced the tail current source with a couple of inductors to omit the source of the phase noise in the output. A proper phase noise level was achieved with an extremely high dissipating current of around 6 mA from 0.5 V of supply. It could be recognized that the most recent researches are derived from an innovative change in the Colpitts structure. Obviously, the Colpitts oscillation startup current is much larger than that of cross-coupled structures. Thus, most of works on the Colpitts structure could not present an impressive improvement from the side of dissipating power consumption. Consequently, Colpitts has smaller oscillation start up condition compared to the cross-coupled structures which present lower phase noise level as well as higher oscillating amplitude. In this paper, a cross-coupled
M. Bagheri et al. / Microelectronics Journal 45 (2014) 1008–1013
1009
circuitry is used as the rudimentary structure. In order to decrease the phase noise, two solutions based on amplitude enlargement are opted. First, a technique to enhance the signal amplitude after the cross-coupled transistors is used to boost the oscillating level. Second, a tail current source is eliminated to improve the phase noise level at the output. The rest of the paper is arranged as follows: Section 2 presents the mentioned technique. Complete circuitry and schematics are demonstrated in Section 3. Simulation and postlayout simulation results are placed in Section 4 and Section 5 concludes the paper finally.
2. Proposed architecture Fig. 1(a) presents a cross-coupled structure in which the phase noise is relatively high due to the direct injection of the phase noise from the switching transistors into the tank. The main idea of this paper arises from Fig. 1(b) with a k-block above the cross-coupled transistors so that their phase noise can be rejected before injecting to the tank. Supposing that the phase noise of the mentioned block is not contributed to the circuit, it can be stated that the phase noise rejections as well as the oscillating amplitude enlargement are the benefits of this block. In addition, the dc voltage level can be increased by omitting the tail current source. As the tail current source directly acts as a noise source in the output, its elimination would be beneficial to the final phase noise level improvement, too. Fig. 1(c) presents the exact idea mentioned above.
Fig. 2. Proposed VCO with its bias circuitry.
− VOUT M5
1
2 VB
3. Suggested circuitry 3.1. Suggested VCO circuitry
C1
M3 M
3
C2
Fig. 2 presents the schematic of proposed VCO along with the bias circuitry. M1 and M2 are switching transistors. The amplifying stage, k-block, is replaced with M3, M4, M5, M6, C1 and C2. Large capacitance of Cp can eliminate high frequency noise of the bias circuit. The circuit current is determined with M1 and M2 while
Fig. 3. k-Block circuitry.
their drain voltage is fixed with M5 and M6, respectively. So, the circuit current is controllable. 3.2. k-Block
k
k
k
k
Fig. 1. Cross-coupled structure (a) with its noise sources, (b) with k-blocks, (c) without tail current source.
Fig. 3 prepares a precise presentation of k-block. C1, C2 and assisting transistors (M3 and M5) can reduce the phase noise while increasing the swing level of the output voltage. The signal first meets the node M of switching transistor. As shown in Fig. 3, three paths of active and passive elements are now encountered. Active signal paths through M3 (Common-Gate) and M5 (Common-Drain) are a couple of those. The third path is through C1 which prepares a direct way to the node M. Finally, the estimated output signal would be the summation of three signals with the same phase, resulting in an amplified output swing. Meanwhile, the large capacitance of C2 will lead to a better filtering behavior in the circuit, but the oscillating frequency will be decreased. On the other hand, C2 is not a good noise blocker if it has a small value. Therefore, its value is a challenge and should be optimized by the simulation. The role of C1 in the circuit is blocking the injected noise of M3 and M5. Thus, the k-block can be considered low phase noise due to the enhanced final output and added noise filter (C1). In another analyze, it might be safe to say that the current noise of transistors will create the maximum phase noise when the output voltage crosses zero [7]. On the other hand, the k-block operates as an amplifier in this region and intensifies the signal amplitude. It means closing the signal angle to degree 90 around zero crossing region as shown in Fig. 4. Why this swing enhancement occurs is related to when the transistors enter the nonlinear
1010
M. Bagheri et al. / Microelectronics Journal 45 (2014) 1008–1013 + Vout
Amplitude Boosted signal L
Rtank
CVar
Cin
Rin
I1
Fig. 6. Equivalent large signal model to find resonance amplitude signal.
Critical moments t
Initial signal
Fig. 4. A comparison between initial and boosted signal.
VDD
L
Cvar
VC
L Fig. 7. A circuit showing how to find C.
Cvar
− Vout +
W5 ,6 = 100 µ m
M5 C1 M3
VB
M6 C1 VB
M4
W3 ,4 = 50µ m C2
W1,2 = 20 µ m
C2
M1
M2
Fig. 5. Final schematic of proposed VCO without bias circuitry.
region. The more the key transistor is near to their nonlinear region (the region between small signal trans-conductance and large signal one), the more swing will be achieved. Finally, it can be stated that the swing enhancement in the same current will improve the phase noise behavior.
3.3. Output voltage swing In order to find the output voltage of the tank in Fig. 5, the large signal trans-conductance must be calculated [8]: Gm ¼ 2I B =V gs
ð1Þ
Fig. 8. Suitable model to find Rx.
Table 1 The comparison of output oscillation amplitude VCOs with proposed VCO. Reference
Name
Output oscillation amplitude
[9] [9] [8] [10] [11] This work
Cross-coupled DS-VCO Colpitts Gm-Boosted Differential G-S Gm-Boosted Differential D-S Proposed VCO
ð2=πÞRB I B ð4=πÞRB I B 4IB Rtank ð1 nÞ 4IB Rtank n 4IB Rtank ð1 nÞ 4IB Rtank ½1 ðn=2Þ
In (1), IB is the bias current and Vgs is the gate-source voltage of the transistor. In order to find the voltage amplitude of the tank, the large signal model (half-circuit model) is predicted in Fig. 6 [7]. I1, Cin, Rin, Cvar, Rtank, and L are the amplitude of the first harmonic of drain current, the capacitance shown in Fig. 7, the impedance seen via the tank, the varactor of the tank, the series resistance of output inductance and the output inductance, respectively. Cin can be found from Fig. 7. Where C 1;T and C 2;T are as follows:
C 1;T ¼ C 1 þ C gs6
C 2;T ¼ C 2 þ C gs1
C 2;T C 2
ð2Þ
ð3Þ
Cgs1 and Cgs6 are negligible compared to C1 and C2. Thus (2) and (3) roughly can be simplified as ð4Þ
M. Bagheri et al. / Microelectronics Journal 45 (2014) 1008–1013
1011
3
VDD
4.7 V
2
M3
VC
Cvar
L
L
Cvar
Cvar
1 Voltage (V)
VDD
L
M4 L VC
−1
Cvar
−2
− Vout
− Vout
0
−3 2
M2
M1
M2
M1
2.05
2.1 Time (nS)
2.15
2.2
Fig. 11. The simulation result of the oscillation amplitude.
−60 −70 Fig. 9. Schematic of (a) cross-coupled and (b) double switch (DS) VCOs.
L
Cvar
VC
Phase Noise(dBc/Hz)
VDD
−80
L Cvar
− Vout +
−90 −100 −110 −120 −130
C1
M1
IB
IB
C2
M2
Vbias
C1
−140
C2
−150 4 10
10
5
6
10
7
10
Frequency(Hz) Fig. 12. The post-layout simulation result of the phase noise.
VDD L
L Cvar
VC
Cvar
Cvar
− Vout +
M3
C2
C1
C1
M2
M1
VC
L
C2 C2
C in ¼ C 1 =ðC 1 þ C 2 Þ
M3
Rx ¼ ½ð1=jωC gd4 Þ þ ð1=jωC gd6 jjr o4 Þ=ð1 þ ½Gm4 ð1=jωC gd6 jjr o4 ÞÞ
Vbias M4 M2
M1
ð6Þ
Fig. 8 is used to find Rin [7], where Z1 roles as an equivalent impedance at the source node of M6. Considering Fig. 8, i1 is approximately closed to zero and Rx can be shown as
Cvar
− Vout + VDD
M4 C1
Eventually, Cin can be presented [7] as (6)
VDD
L
C1 C2
For r o4 1 (7) is simplified to (8): Rx ¼ ½ð1=jωC gd4 Þ þ ð1=jωC gd6 Þ=½Gm4 ð1=jωC gd6 Þ
Mb
Vbias
Mb
ð8Þ
Obviously, C gd4 C gd6 and Rx can be simplified to (9): Rx 2=Gm4
Vbias
ð7Þ
ð9Þ
So, Rin can be found as below [7]: Rin ¼ Rx =n2
Fig. 10. Schematic of (a) Colpitts, (b) gm-boosted gate-to-source (G–S) Colpitts, and (c) gm-boosted drain-to-source (D–S) Colpitts VCOs.
where n is C 1 =ðC 1 þ C 2 Þ.
ð10Þ þ V out
can be calculated:
þ V out ¼ I 1 ½Rtank jjð2=ðn2 Gm4 ÞÞ
ð11Þ
þ Gm4 can be replaced by I 1 =ðnV out Þ [7], then (11) results to:
C 1;T C 1
ð5Þ
þ V out
¼ I 1 Rtank ½1 ðn=2Þ
ð12Þ
1012
M. Bagheri et al. / Microelectronics Journal 45 (2014) 1008–1013
Finally, in the differential mode, the output signal amplitude can be shown as below: þ V out ¼ V out V out ¼ 4I B Rtank ½1 ðn=2Þ
ð13Þ
Table 1 is provided in order to compare some of the presented output amplitude with (13). In [9], the output oscillation amplitudes of cross-coupled and double switch (DS) VCO were shown. The related structures are shown in Fig. 9. It is obvious that both structures have a lower output oscillation amplitude compared to the proposed VCO. Given that in the mentioned structures C1 and C2 are not used, factor n does not appear in their output oscillation amplitudes. As the noise of switching transistors is directly injected into the tank, both structures approximately have more phase noise than Colpitts, gm-boosted, and the proposed VCO. In [8,10,11], the output oscillation amplitudes of Colpitts, gm-boosted differential gate-to-source (G-S) feedback Colpitts, and gm-boosted differential drain-to-source (D–S) feedback Colpitts were calculated, respectively. The three structures are shown in Fig. 10. Taking a quick look at the presented equations, it can be easily
figured out that the output oscillating amplitude of the presented structure is higher than three mentioned VCOs. The simulation coming in the next part shows that a voltage swing improvement of at least 25% is gained compared to that of the three VCOs with the same current and n ¼0.5. Because of the existence of C1 and C2, the phase noise of three VCOs is lower cross-coupled structure. Based on the discussion above, it can be easily concluded that the output oscillating amplitude of the proposed VCO is higher than the output of previous ones.
4. Simulation and post-layout simulation results The proposed VCO is designed in 0.18 μm TSMC CMOS technology with 1.8 V power supply. Fig. 11 shows the simulation result of the output voltage swing in which the output signal peak to peak is about 4.7 V, the center frequency is 2.3 GHz, the tank quality factor is 7.5 and the output current is 1.3 mA. Fig. 12 shows the post-layout simulation result of the phase noise. As it is demonstrated, the phase noises at the offset frequency of 1 MHz and 3 MHz are 125 dBc/Hz and 136.5 dBc/Hz, respectively. It could be stated that output voltage level increment can improve the phase noise behavior of the circuit [8]. Also, Fig. 13 shows the layout schematic of the proposed circuit. A comparison among recently published CMOS-based VCOs is provided in Table 2. Also, a figure-of-merit (FoM) is considered as [6]. FoM ¼ 20 log ðf o =Δf Þ 10 log ðP DC =1 mWÞ þ LfΔf g
ð14Þ
where fo is the resonance frequency, Δf is the offset frequency, PDC is the power dissipation and LfΔf g is the phase noise (dBc/Hz). Although the comparisons are presented in this table are the measurement results, the amplitude results have been obtained from simulation. It should be mentioned that the reported amplitude result of [11] is obtained from simulation using 1.8 V power supply. To verify that the proposed VCO is promising through PVT variations, Table 3 is provided to show the post-layout simulation results. It is clear that FoM of the proposed VCO remains relatively constant throughout the PVT variations. 4.1. Monte Carlo simulation result
Fig. 13. The layout schematic of the proposed VCO.
The transistors W, L and also process variation were examined taking advantage of Monte Carlo simulation. The results show that the proposed design is very promising and confirm the performance of the circuit. In 100 times of simulation, the phase noise variation is less than 1 dBc/Hz and the frequency variation is less than 290 kHz over the center frequency of 2.5 GHz. Fig. 14 depicts the mentioned simulation results.
Table 2 Comparison of proposed VCO with newly published counterparts. VCO
Frequency (GHz)
Supply (V)
pdc (mW)
Phase noise (dBc/Hz)
FoM (dBc/Hz)
Amplitude (V)
Process (nm)
[11] [12] [13] [14] [15] [16] [17] [18] [19] This work
1.84 1.8 1.8 4.84 E6 3.1 3.4 1.96 13.15 2.3
0.9 2 1.4 1.2 1.8 1 1.2 1.8 0.75 1.8
1.35 7.2 15.8 3.4 E 2.16 1.57 6.6 14.4 2.4 2.3
126@1 MHz 128@1 MHz 145.6@3 MHz 125@1 MHz E 123@2 MHz 123@1 MHz 147@10 MHz 118.5@1 MHz 101.4@1 MHz 125@1 MHz 136.5@3 MHz
190 184.5 189.1 193 189 191.2 191 172.9 180 189 190.6
E2.6 N.A N.A E2.5 0.9 N.A E2 N.A E2.2 4.7
180 180 180 180 180 180 90 180 180 180
M. Bagheri et al. / Microelectronics Journal 45 (2014) 1008–1013
Table 3 PVT variations in proposed VCO. Process Corner
Frequency (GHz)
Current (mA)
Phase noise (dBc/Hz)
FOM (dBc/Hz)
TT ½27 1C FF ½ 40 1C SS ½125 1C
2.3 2.5 2.1
1.3 1.3 1.2
125@1 MHz 126.2@1 MHz 123.4@1 MHz
189 190.45 186.5
1013
enhancement. The post-layout simulation in 0.18 μm CMOS technology with oscillation frequency of 2.3 GHz, shows the offset frequency of 1 MHz and the phase noise of 125 dBc/Hz with the power supply of 1.8 V and a total current of 1.3 mA. Based on the mentioned results and the Monte Carlo simulation, the proposed idea shows a promising and improved performance compared to the other works published recently. References
Fig. 14. Monte Carlo simulation results (a) phase noise, (b) frequency variation.
5. Conclusion In this paper a basic idea of how to improve the phase noise behavior in conventional VCOs is presented. The dominant feature of this new structure is the improvement in output voltage swing compared to the recently published counterparts. This improvement is achieved through intensifying the output oscillating amplitude without increasing the circuit current and power as well. Large signal analysis is used to prove the voltage swing
[1] M.S. Mcorquodale, G.A. Carichner, J.D. ODay, S.M. Pernia, S. Kubba, E.D. Marsmam, J.J. Kuhn, R.B. Rown, A MHz self-referenced solid-state frequency source suitable for XO-replacement, IEEE Trans. Circuits Syst. I 56 (February (5)) (2009) 943–956. [2] P. Andreani, S. Mattisson, On the use of MOS varactors in RF VCO's, IEEE J. Solid State Circuits 35 (August (6)) (2000) 905–910. [3] T.S.D. Cheung, J.R. Long, Shielded passive device for silicon-based monolithic microwave and millimeter-wave integrated circuits, IEEE J. Solid State Circuits 41 (May (5)) (2006) 1183–1200. [4] M. Danesh, J.R. Long, Differentially driven symmetric microstrip inductors, IEEE Trans. Microw. Theory Tech. 50 (January (1)) (2002) 332–341. [5] E. Hegazi, H. Sjoland, A.A. Abidi, A filtering technique to lower LC oscillator phase noise, IEEE J. Solid State Circuits 36 (December (12)) (2001) 1921–1930. [6] T.W. Brown, F. Farhabakhshian, A.G. Guha, T.S. Fiez, K. Mayaram, A 475 mV, 4.9 GHz enhanced swing differential Colpitts VCO with phase noise of 136 dBc/Hz at a 3 MHz offset frequency, IEEE J. Solid State Circuits 46 (August (8)) (2011) 1782–1795. [7] A. Hajimiri, T.H. Lee, The Design of Low Noise Oscillators, Second Edition, First Printing, Published by the press Syndicate of the University Cambridge, Printed in the United States of America, 2004. [8] P. Andreani, X. Wang, A. Fard, A study of phase noise in Colpitts and LC-tank CMOS oscillators, IEEE J. Solid State Circuits 40 (May (5)) (2005) 1107–1118. [9] P. Andreani, A. Fard, More on the 1/f2 phase noise performance of CMOS differential-pair LC-tank oscillators, IEEE J. Solid State Circuits 41 (December (12)) (2006) 2703–2712. [10] J.P. Hong, S.G. Lee, Low phase-noise Gm-boosted differential gate-to-source feedback Colpitts CMOS VCO, IEEE J. Solid State Circuits 44 (November (11)) (2009) 3079–3091. [11] J.P. Hong, S.G. Lee, Gm-boosted differential drain-to-source feedback Colpitts CMOS VCO, IEEE Trans. Microw. Theory Tech. 59 (July (7)) (2011) 1811–1821. [12] C.P. Bean, Gm-boosted common-gate LNA and differential Colpitts VCO/QVCO in 0.18-m CMOS, IEEE J. Solid State Circuits 40 (December (12)) (2005) 2609–2619. [13] C.Y. Cha, A source coupled differential CMOS complementary Colpitts oscillator with on-chip transformer tank, Trans. Microw. Theory Tech. 56 (May (5)) (2008) 1076–1082. [14] W. Deng, K. Okada, A. Matsuzawa, Class-C VCO with amplitude feedback loop for robust start-up enhanced oscillation swing, IEEE J. Solid State Circuits 48 (February (2)) (2013) 429–440. [15] A. Mazzanti, P. Andreani, A pushpull class-C CMOS VCO, IEEE J. Solid State Circuits 48 (March (3)) (2013) 724–732. [16] J. Chen, F. Jonsson, M. Carlsson, C. Hedens, L. Zheng, A low power, startup ensured and constant amplitude class-C VCO in 0.18 μm CMOS, IEEE Microw. Wirel. Compon. Lett. 21 (August (8)) (2011) 427–429. [17] L. Fanori, P. Andreani, Highly efficient class-C CMOS VCOs, including a comparison with class-B VCOs, IEEE J. Solid State Circuits 48 (July (7)) (2013) 1730–1740. [18] W. Zou, X. Chen, K. Dai, X. Zou, Switched-inductor VCO based on tapped vertical solenoid inductors, Electron Lett. 48 (April (9)) (2012) 509–511. [19] T.P. Wang, Y.M. Yan, A low-voltage low-power wide-tuning-range hybrid Class-AB/Class-B VCO with robust start-up and high-performance FOMT, Trans. Microw. Theory Tech. 62 (March (3)) (2014) 521–531.
Contents lists available at ScienceDirect
Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
A cross coupled low phase noise oscillator using an output swing enhancement technique Mohammad Bagheri a,n, Ahmad Ghanaatian a, Adib Abrishamifar a, Mahmoud Kamarei b a b
Department of Electrical Engineering, University of Science and Technology, Tehran, Iran Department of Electrical and Computer Engineering, University of Tehran, Tehran, Iran
art ic l e i nf o
a b s t r a c t
Article history: Received 23 December 2013 Received in revised form 12 April 2014 Accepted 18 April 2014
A new voltage controlled oscillator (VCO) in a 0.18 μm CMOS process is offered in this paper. This paper's argument is to provide an innovative approach to improve the phase noise which is one of the most controversial issues in VCOs. Contrary to most ideas that have been put forward to decrease phase noise which are based on higher current dissipation to increase output voltage swing, this new method offers better specifications with respect to traditional solutions. The presented circuit is capable of extra oscillation amplitude without increasing the current level, taking advantages of tail current elimination and topology optimization. Analysis of the presented peak voltage amplitude can verify the optimum performance of the proposed. Post-layout simulation results at 2.3 GHz with an offset frequency of 1 MHz and 3 MHz show a phase noise of about 125 dBc/Hz and 136.5 dBc/Hz, respectively, with the current of 1.3 mA from 1.8 V supply. Also, Monte Carlo simulation is used to ensure the sensitivity of the proposed circuit to process and frequency variations are very promising. & 2014 Elsevier Ltd. All rights reserved.
Keywords: Voltage controlled oscillator Ultra low phase noise
1. Introduction Local oscillators or crystals in traditional ways were often used for various applications which cannot meet nowadays dominant criteria, like low cost, small size, and low power consumption. As it seems impossible to put the frequency crystal on-chip, designing a crystal-less oscillator with an appropriate phase noise is attractive for future RF technology. Some different techniques have been used to overcome the inaccuracy issue of crystal-less oscillators. In order to achieve an acceptable phase noise performance in a VCO, some key factors such as temperature, supply voltage, and process variation should be considered. In 2009, Mcorquodale et al. [1] used a complementary structure for the oscillator. Using advantage of a feedback from a frequency divider, a novel compensator circuit, and a band gap reference circuit with the 2nd order temperature-coefficient compensation, Mcorquodale et al. [1] could achieve a brilliant phase noise as well as a jitter level just like crystal oscillators. With this innovating feedback and complex structure which improve the phase noise and jitter as well, high dissipating power and current are inevitable.
n
Corresponding author. E-mail address: [email protected] (M. Bagheri).
http://dx.doi.org/10.1016/j.mejo.2014.04.018 0026-2692/& 2014 Elsevier Ltd. All rights reserved.
In theory, increasing quality factor can be mentioned as one of the effective ways to gain the proper phase noise in LC oscillators. But, the technology properties limit the improvement of Q in the tank [2–4]. Therefore, it could not be regarded as a certain way in all technologies. Another possible method to decrease the phase noise in crystal-less oscillators is eliminating the tail current as a main factor in the oscillators final phase noise [5]. Also, a capacitor and an inductor should be placed in the tail part of the circuit. These passive elements work as a filter of the 2nd tail current harmonic which mainly affects the output phase noise. However, these components will make the final circuit somewhere big in size. In 2011, Brown et al. [6] replaced the tail current source with a couple of inductors to omit the source of the phase noise in the output. A proper phase noise level was achieved with an extremely high dissipating current of around 6 mA from 0.5 V of supply. It could be recognized that the most recent researches are derived from an innovative change in the Colpitts structure. Obviously, the Colpitts oscillation startup current is much larger than that of cross-coupled structures. Thus, most of works on the Colpitts structure could not present an impressive improvement from the side of dissipating power consumption. Consequently, Colpitts has smaller oscillation start up condition compared to the cross-coupled structures which present lower phase noise level as well as higher oscillating amplitude. In this paper, a cross-coupled
M. Bagheri et al. / Microelectronics Journal 45 (2014) 1008–1013
1009
circuitry is used as the rudimentary structure. In order to decrease the phase noise, two solutions based on amplitude enlargement are opted. First, a technique to enhance the signal amplitude after the cross-coupled transistors is used to boost the oscillating level. Second, a tail current source is eliminated to improve the phase noise level at the output. The rest of the paper is arranged as follows: Section 2 presents the mentioned technique. Complete circuitry and schematics are demonstrated in Section 3. Simulation and postlayout simulation results are placed in Section 4 and Section 5 concludes the paper finally.
2. Proposed architecture Fig. 1(a) presents a cross-coupled structure in which the phase noise is relatively high due to the direct injection of the phase noise from the switching transistors into the tank. The main idea of this paper arises from Fig. 1(b) with a k-block above the cross-coupled transistors so that their phase noise can be rejected before injecting to the tank. Supposing that the phase noise of the mentioned block is not contributed to the circuit, it can be stated that the phase noise rejections as well as the oscillating amplitude enlargement are the benefits of this block. In addition, the dc voltage level can be increased by omitting the tail current source. As the tail current source directly acts as a noise source in the output, its elimination would be beneficial to the final phase noise level improvement, too. Fig. 1(c) presents the exact idea mentioned above.
Fig. 2. Proposed VCO with its bias circuitry.
− VOUT M5
1
2 VB
3. Suggested circuitry 3.1. Suggested VCO circuitry
C1
M3 M
3
C2
Fig. 2 presents the schematic of proposed VCO along with the bias circuitry. M1 and M2 are switching transistors. The amplifying stage, k-block, is replaced with M3, M4, M5, M6, C1 and C2. Large capacitance of Cp can eliminate high frequency noise of the bias circuit. The circuit current is determined with M1 and M2 while
Fig. 3. k-Block circuitry.
their drain voltage is fixed with M5 and M6, respectively. So, the circuit current is controllable. 3.2. k-Block
k
k
k
k
Fig. 1. Cross-coupled structure (a) with its noise sources, (b) with k-blocks, (c) without tail current source.
Fig. 3 prepares a precise presentation of k-block. C1, C2 and assisting transistors (M3 and M5) can reduce the phase noise while increasing the swing level of the output voltage. The signal first meets the node M of switching transistor. As shown in Fig. 3, three paths of active and passive elements are now encountered. Active signal paths through M3 (Common-Gate) and M5 (Common-Drain) are a couple of those. The third path is through C1 which prepares a direct way to the node M. Finally, the estimated output signal would be the summation of three signals with the same phase, resulting in an amplified output swing. Meanwhile, the large capacitance of C2 will lead to a better filtering behavior in the circuit, but the oscillating frequency will be decreased. On the other hand, C2 is not a good noise blocker if it has a small value. Therefore, its value is a challenge and should be optimized by the simulation. The role of C1 in the circuit is blocking the injected noise of M3 and M5. Thus, the k-block can be considered low phase noise due to the enhanced final output and added noise filter (C1). In another analyze, it might be safe to say that the current noise of transistors will create the maximum phase noise when the output voltage crosses zero [7]. On the other hand, the k-block operates as an amplifier in this region and intensifies the signal amplitude. It means closing the signal angle to degree 90 around zero crossing region as shown in Fig. 4. Why this swing enhancement occurs is related to when the transistors enter the nonlinear
1010
M. Bagheri et al. / Microelectronics Journal 45 (2014) 1008–1013 + Vout
Amplitude Boosted signal L
Rtank
CVar
Cin
Rin
I1
Fig. 6. Equivalent large signal model to find resonance amplitude signal.
Critical moments t
Initial signal
Fig. 4. A comparison between initial and boosted signal.
VDD
L
Cvar
VC
L Fig. 7. A circuit showing how to find C.
Cvar
− Vout +
W5 ,6 = 100 µ m
M5 C1 M3
VB
M6 C1 VB
M4
W3 ,4 = 50µ m C2
W1,2 = 20 µ m
C2
M1
M2
Fig. 5. Final schematic of proposed VCO without bias circuitry.
region. The more the key transistor is near to their nonlinear region (the region between small signal trans-conductance and large signal one), the more swing will be achieved. Finally, it can be stated that the swing enhancement in the same current will improve the phase noise behavior.
3.3. Output voltage swing In order to find the output voltage of the tank in Fig. 5, the large signal trans-conductance must be calculated [8]: Gm ¼ 2I B =V gs
ð1Þ
Fig. 8. Suitable model to find Rx.
Table 1 The comparison of output oscillation amplitude VCOs with proposed VCO. Reference
Name
Output oscillation amplitude
[9] [9] [8] [10] [11] This work
Cross-coupled DS-VCO Colpitts Gm-Boosted Differential G-S Gm-Boosted Differential D-S Proposed VCO
ð2=πÞRB I B ð4=πÞRB I B 4IB Rtank ð1 nÞ 4IB Rtank n 4IB Rtank ð1 nÞ 4IB Rtank ½1 ðn=2Þ
In (1), IB is the bias current and Vgs is the gate-source voltage of the transistor. In order to find the voltage amplitude of the tank, the large signal model (half-circuit model) is predicted in Fig. 6 [7]. I1, Cin, Rin, Cvar, Rtank, and L are the amplitude of the first harmonic of drain current, the capacitance shown in Fig. 7, the impedance seen via the tank, the varactor of the tank, the series resistance of output inductance and the output inductance, respectively. Cin can be found from Fig. 7. Where C 1;T and C 2;T are as follows:
C 1;T ¼ C 1 þ C gs6
C 2;T ¼ C 2 þ C gs1
C 2;T C 2
ð2Þ
ð3Þ
Cgs1 and Cgs6 are negligible compared to C1 and C2. Thus (2) and (3) roughly can be simplified as ð4Þ
M. Bagheri et al. / Microelectronics Journal 45 (2014) 1008–1013
1011
3
VDD
4.7 V
2
M3
VC
Cvar
L
L
Cvar
Cvar
1 Voltage (V)
VDD
L
M4 L VC
−1
Cvar
−2
− Vout
− Vout
0
−3 2
M2
M1
M2
M1
2.05
2.1 Time (nS)
2.15
2.2
Fig. 11. The simulation result of the oscillation amplitude.
−60 −70 Fig. 9. Schematic of (a) cross-coupled and (b) double switch (DS) VCOs.
L
Cvar
VC
Phase Noise(dBc/Hz)
VDD
−80
L Cvar
− Vout +
−90 −100 −110 −120 −130
C1
M1
IB
IB
C2
M2
Vbias
C1
−140
C2
−150 4 10
10
5
6
10
7
10
Frequency(Hz) Fig. 12. The post-layout simulation result of the phase noise.
VDD L
L Cvar
VC
Cvar
Cvar
− Vout +
M3
C2
C1
C1
M2
M1
VC
L
C2 C2
C in ¼ C 1 =ðC 1 þ C 2 Þ
M3
Rx ¼ ½ð1=jωC gd4 Þ þ ð1=jωC gd6 jjr o4 Þ=ð1 þ ½Gm4 ð1=jωC gd6 jjr o4 ÞÞ
Vbias M4 M2
M1
ð6Þ
Fig. 8 is used to find Rin [7], where Z1 roles as an equivalent impedance at the source node of M6. Considering Fig. 8, i1 is approximately closed to zero and Rx can be shown as
Cvar
− Vout + VDD
M4 C1
Eventually, Cin can be presented [7] as (6)
VDD
L
C1 C2
For r o4 1 (7) is simplified to (8): Rx ¼ ½ð1=jωC gd4 Þ þ ð1=jωC gd6 Þ=½Gm4 ð1=jωC gd6 Þ
Mb
Vbias
Mb
ð8Þ
Obviously, C gd4 C gd6 and Rx can be simplified to (9): Rx 2=Gm4
Vbias
ð7Þ
ð9Þ
So, Rin can be found as below [7]: Rin ¼ Rx =n2
Fig. 10. Schematic of (a) Colpitts, (b) gm-boosted gate-to-source (G–S) Colpitts, and (c) gm-boosted drain-to-source (D–S) Colpitts VCOs.
where n is C 1 =ðC 1 þ C 2 Þ.
ð10Þ þ V out
can be calculated:
þ V out ¼ I 1 ½Rtank jjð2=ðn2 Gm4 ÞÞ
ð11Þ
þ Gm4 can be replaced by I 1 =ðnV out Þ [7], then (11) results to:
C 1;T C 1
ð5Þ
þ V out
¼ I 1 Rtank ½1 ðn=2Þ
ð12Þ
1012
M. Bagheri et al. / Microelectronics Journal 45 (2014) 1008–1013
Finally, in the differential mode, the output signal amplitude can be shown as below: þ V out ¼ V out V out ¼ 4I B Rtank ½1 ðn=2Þ
ð13Þ
Table 1 is provided in order to compare some of the presented output amplitude with (13). In [9], the output oscillation amplitudes of cross-coupled and double switch (DS) VCO were shown. The related structures are shown in Fig. 9. It is obvious that both structures have a lower output oscillation amplitude compared to the proposed VCO. Given that in the mentioned structures C1 and C2 are not used, factor n does not appear in their output oscillation amplitudes. As the noise of switching transistors is directly injected into the tank, both structures approximately have more phase noise than Colpitts, gm-boosted, and the proposed VCO. In [8,10,11], the output oscillation amplitudes of Colpitts, gm-boosted differential gate-to-source (G-S) feedback Colpitts, and gm-boosted differential drain-to-source (D–S) feedback Colpitts were calculated, respectively. The three structures are shown in Fig. 10. Taking a quick look at the presented equations, it can be easily
figured out that the output oscillating amplitude of the presented structure is higher than three mentioned VCOs. The simulation coming in the next part shows that a voltage swing improvement of at least 25% is gained compared to that of the three VCOs with the same current and n ¼0.5. Because of the existence of C1 and C2, the phase noise of three VCOs is lower cross-coupled structure. Based on the discussion above, it can be easily concluded that the output oscillating amplitude of the proposed VCO is higher than the output of previous ones.
4. Simulation and post-layout simulation results The proposed VCO is designed in 0.18 μm TSMC CMOS technology with 1.8 V power supply. Fig. 11 shows the simulation result of the output voltage swing in which the output signal peak to peak is about 4.7 V, the center frequency is 2.3 GHz, the tank quality factor is 7.5 and the output current is 1.3 mA. Fig. 12 shows the post-layout simulation result of the phase noise. As it is demonstrated, the phase noises at the offset frequency of 1 MHz and 3 MHz are 125 dBc/Hz and 136.5 dBc/Hz, respectively. It could be stated that output voltage level increment can improve the phase noise behavior of the circuit [8]. Also, Fig. 13 shows the layout schematic of the proposed circuit. A comparison among recently published CMOS-based VCOs is provided in Table 2. Also, a figure-of-merit (FoM) is considered as [6]. FoM ¼ 20 log ðf o =Δf Þ 10 log ðP DC =1 mWÞ þ LfΔf g
ð14Þ
where fo is the resonance frequency, Δf is the offset frequency, PDC is the power dissipation and LfΔf g is the phase noise (dBc/Hz). Although the comparisons are presented in this table are the measurement results, the amplitude results have been obtained from simulation. It should be mentioned that the reported amplitude result of [11] is obtained from simulation using 1.8 V power supply. To verify that the proposed VCO is promising through PVT variations, Table 3 is provided to show the post-layout simulation results. It is clear that FoM of the proposed VCO remains relatively constant throughout the PVT variations. 4.1. Monte Carlo simulation result
Fig. 13. The layout schematic of the proposed VCO.
The transistors W, L and also process variation were examined taking advantage of Monte Carlo simulation. The results show that the proposed design is very promising and confirm the performance of the circuit. In 100 times of simulation, the phase noise variation is less than 1 dBc/Hz and the frequency variation is less than 290 kHz over the center frequency of 2.5 GHz. Fig. 14 depicts the mentioned simulation results.
Table 2 Comparison of proposed VCO with newly published counterparts. VCO
Frequency (GHz)
Supply (V)
pdc (mW)
Phase noise (dBc/Hz)
FoM (dBc/Hz)
Amplitude (V)
Process (nm)
[11] [12] [13] [14] [15] [16] [17] [18] [19] This work
1.84 1.8 1.8 4.84 E6 3.1 3.4 1.96 13.15 2.3
0.9 2 1.4 1.2 1.8 1 1.2 1.8 0.75 1.8
1.35 7.2 15.8 3.4 E 2.16 1.57 6.6 14.4 2.4 2.3
126@1 MHz 128@1 MHz 145.6@3 MHz 125@1 MHz E 123@2 MHz 123@1 MHz 147@10 MHz 118.5@1 MHz 101.4@1 MHz 125@1 MHz 136.5@3 MHz
190 184.5 189.1 193 189 191.2 191 172.9 180 189 190.6
E2.6 N.A N.A E2.5 0.9 N.A E2 N.A E2.2 4.7
180 180 180 180 180 180 90 180 180 180
M. Bagheri et al. / Microelectronics Journal 45 (2014) 1008–1013
Table 3 PVT variations in proposed VCO. Process Corner
Frequency (GHz)
Current (mA)
Phase noise (dBc/Hz)
FOM (dBc/Hz)
TT ½27 1C FF ½ 40 1C SS ½125 1C
2.3 2.5 2.1
1.3 1.3 1.2
125@1 MHz 126.2@1 MHz 123.4@1 MHz
189 190.45 186.5
1013
enhancement. The post-layout simulation in 0.18 μm CMOS technology with oscillation frequency of 2.3 GHz, shows the offset frequency of 1 MHz and the phase noise of 125 dBc/Hz with the power supply of 1.8 V and a total current of 1.3 mA. Based on the mentioned results and the Monte Carlo simulation, the proposed idea shows a promising and improved performance compared to the other works published recently. References
Fig. 14. Monte Carlo simulation results (a) phase noise, (b) frequency variation.
5. Conclusion In this paper a basic idea of how to improve the phase noise behavior in conventional VCOs is presented. The dominant feature of this new structure is the improvement in output voltage swing compared to the recently published counterparts. This improvement is achieved through intensifying the output oscillating amplitude without increasing the circuit current and power as well. Large signal analysis is used to prove the voltage swing
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