A Cu seed layer for Cu deposition on silicon

Solid-State Electronics Vol. 41, No. 5, pp. 695-702. 1997 0 1997 Elsevier ScienceLtd. All rights reserved Printed in Great Britain PII: !30038-1101(sa)oozs 0038-1101/97 $17.00+ 0.00

A Cu SEED LAYER FOR Cu DEPOSITION ON SILICON M. K. LEE, H. D. WANG and J. J. WANG Institute of Electrical Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan 80824, Republic of China (Received

9 July 1996; in revised form

I October

1996)

Abstract A novel copper deposition method has been developed in which the solution is composed of hydrofluoric acid and cupric sulfate. Here, we investigate the growth mechanism of Cu film on silicon. The copper film thickness is dominated by copper ion diffusion in the solution and, hence, follows a parabolic relation with deposition time and a linear relation with copper ion concentration. In addition, we study the Cu deposited on a silicon strip, which shows an isotropic etching property with an undercut against the mask. Furthermore, the deposited Cu on silicon shows a Schottky diode behavior. Its Schottky barrier height, leakage current and ideality factor are all studied in this paper. 0 1997 Elsevier Science Ltd

INTRODUCHON

In ultra-large-scale integration (ULSI) structures, the demand for manufacturing integrated circuit devices such as dynamic random access memory, static random access memory, and logic devices with high circuit speed, high packaging density and low power dissipation requires reduced interconnect feature size. Therefore, for ULSI metallization applications, innovations are needed for both material and process development. Generally, high resistivity interconnect will increase the resistance-capacitance time delay limiting the device performance[l]. On the other hand, the deposition of thin metal films at relatively high temperature could result in undesirable redistribution of impurities[2]. Hence, there is a need for low-resistivity metal and low-temperature deposition technology for ULSI applications. For deep submicron dimensions, there is an interest in replacing aluminum alloys by a lower-resistivity and higher-electromigration metal like copper[3]. In addition, compared to Al and its alloys, copper offers several intrinsic properties such as higher thermal conductivity, higher melting point and lower thermal expansion coefficient. The copper may be deposited by a variety of techniques, which can be divided into two general categories: (1) physical vapor deposition (PVD)[4,5l-_evaporation, sputtering etc.; and (2) chemical deposition[6,7E_vapor (CVD), electrolytic etc. However, these methods suffer from some problems in depositing copper. PVD deposition is limited by the shadow effect. Due to the high growth temperatures of CVD processes, CVD-Cu films are subject to greater film stress. We propose a novel copper deposition method, in which the deposition solution is composed of hydrofluoric acid and cupric sulfate. It has the

advantages of simple process, safety, low cost, low growth temperature, high purity and low resistivity. Here, we investigate the growth mechanism and its Schottky type behavior of Cu on silicon. EXPERIMENTAL

The wafers used in our work are n-type, phosphorous doped, (100) oriented silicon with a resistivity of l-10 n-cm and a thickness of 400-500 microns. The only solution used for the copper deposition is a combination of two chemicals: hydrofluoric acid (HF) and cupric sulfate (CuS0,.5H20) saturated aqueous solution. The Cu deposition was processed in a Teflon vessel at room temperature. The composition of the copper film is analysed by a Microlab 3 10D Auger electron spectroscope (AES). The exact thickness of the Cu film was measured by a JOEL JSM6400 scanning electron microscope (SEM). Furthermore, we utilize a Nomarski optical microscope to observe the top view of the copper strip on silicon. These strips are patterned by positive photoresist (PR) into different widths, 55, 7 and 5.5 pm. The Schottky barrier height (SBH) was determined using the current-voltage (Z-v) technique at room temperature and a HP4145B was used for this Z-l/characterization. The contact diameter of the Schottky diode is 1000 pm. RESULTS AND DISCUSSION

Composition Figure 1 gives the AES atomic concentration depth profile of the Cu film on the silicon substrate. The film thickness is 5000 A. Oxygen was observed over a large depth on the copper surface and a large 695

M. K. Lee et al.

696

90 A t

60 -

0 in

70 -

i c

60 -

c

50-

0

n

40 -

C 30 ( ;

2010 -

Time

(Seconds)

Fig. 1. AES atomic concentration profile of Cu film on silicon.

transition region from Si to Cu exists. Those transition regions are most likely to be the result of the roughness of the Cu film. The surface and interface roughness leads to graded transitions and related slopes in AES depth profile. The resistivity of LPD-Cu film is measured by a four-point probe, and its value is 2.16 @cm with the thickness of 5000 A.

Growth kinetics

The thickness of the Cu film was determined from SEM observation. Figure 2 shows the relation of copper film thickness vs deposition time. From this figure, the film thickness not only increases with the deposition time, but also with the diluted HF

0.9

0.8 HF concentration: 0.7

--c -e -+ -f

0.6

6.03E-3wt.% 4.13E-3wt.% 3.15E-3wt.K 2.54E-3wt.%

-z 20.5 z i

0.4

0.3 0.2

0. I

0 0

1

3 Tiie(min)

5

7

9

Fig. 2. Cu film thickness versus deposition time with HF concentration as a parameter. The inset is its growth rate vs deposition time.

697

Cu deposition on silicon

1.4 ^ 2500 28 2000 F 1500

1.2

HF concentration +3.15E-3 wt.% 4.13E-3 wt.%

+

E 1000 ? 500 1 8

O

HF=4.13E-3wt.% ------ HF=3.15E-3wt.% CuSO4 concentration:

0.4

0.2

l q

0.045M

A

:zz .

0 0

5

3

1

9

7

Time (mitt) Fig. 3. Cu film thickness on n-Si as a function of deposition time with CuSOd concentration as a parameter at fixed HF concentration. The inset is the growth rate at a fixed deposition time of 3 min.

concentration. derived from

In addition, the deposition rate this figure is a function of HF

concentration and decreases gradually with deposition time as shown in the inset of Fig. 2. It has a rapid growth rate at the beginning of copper

deposition

and implies a fast electrochemical

reaction

between silicon and cupric ion. The following slow growth rate may be due to the diffusion limitation of copper ion, and it will be discussed later. Figure 3 also shows the relation of thickness vs deposition time

1.2 HF concentration -..t.- 4.13E-3 ---m-- 3.15&3 +4.13&3 --r-3.15&3

1

‘$0.8 1 j

Wt.% Wt.% wt% Wt.%

.’

&SO4 = 0.087 M ------- 4100) Si -

p(100) Si

0.6

.r( ; 0.4

0.2 0 0

1

7

3 Time (ti)

9

’

Fig. 4. Cu film thickness on p-type Si as a function of deposition time. The preparation condition for copper film on n-type Si is also shown for comparison.

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M. K. Lee et al.

(a) Cu* cliffhe to silicon surface

C<

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(d) Etching and deposition

(b) Etching and deposition

cl?+

cu2+

\I/

siFh2- + de-

Si + 6F--

cu

CI.?+ + 2e- reaction

+

(e) Deposition fmished

(c) Deposition finished

Fig. 5. Electrochemical

I

cu2+

model for Cu deposition on silicon strip with PR mask.

with cupric sulfate as a growth parameter at a fixed HF concentration. It also indicates that the copper film thickness increases, not only with the deposition time,but also with the CuS04 concentration. The growth rate at a fixed deposition time of 3 min is shown in the inset of Fig. 3. It follows a trend that the growth rate increases with the cupric sulfate and the growth rate is about concentration, 2200 &min at 0.125 M CuS04 and 4.13 x lo-’ wt.% HF. It is faster than that of CVD-Cu (- 1000 A/ min)[8]. In summary, we can see that the deposition rate is a function of the diluted HF and CuSO, concentration. Electrochemical reaction involves the transport of charges at the heterogeneous interface between solution and LPD-Cu. The kinetics of the heterogeneous reaction is normally determined by a sequence of steps involving the transport of species through the solution aqueous phase and the transport of charges at the interface according to the following

simple electrochemical reaction: Cuz+,,j(bulk solution) + 2e- (substrate) -

Cu,,(substrate

surface)

(1)

where (aq) stands for in the aqueous phase and (s) is an adsorbed species on the surface. The reaction can be analyzed by two individual steps, i.e. Cu*+(,, (bulk solution) -

Cu2+&substrate/solution

interface)

(2)

surface).

(3)

Cu2+,,,(interface) + 2e- (substrate) -

G&substrate

Since these processes occur sequentially, then the rate of overall reaction is determined by the following two factors: (a) the transport rate of species to the interface; (b) the exchange rate of electrons at the interface.

Cu deposition

on silicon

699

relation with its concentration, which agrees well with the results of Figs 2 and 3 and with the results by Torcheux et 4111. In addition, the growth rate increases with the diluted HF concentration. The presence of fluorine

Usually, the rate of factor (b) is faster than that of factor (a)[9]. Therefore, the predominant factor is how the Cu ion transports to the interface. According to Fick’s diffusion law[lO], the species diffusion follows a parabolic relation with time and a linear

(b) Fig. bContinued

overleaf.

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w Fig. 6. Nomarski photographs of Cu interconnect. The deposition is in 4.13 x 10e3 wt.% DHF, and 0.045 M C&O4 solution for 5 min. The strip widths are: (a) 55 pm; (b) 7 pm; (c) 5.5 pm. the intermixing of Si and Cu[12]. The highly electronegative fluorine can diffuse and be bonded with silicon atom to form -Si-Si-F and induces a transfer of electrons from Si and, thus, weaken the Si-Si bond in the -Si-Si-F or even break it into Si- and -B-F. More Si-Si bonds will be broken with higher diluted HF concentration, and more electrons are available from broken silicons for copper ions to be metallized on silicon surface and induce a higher growth rate. As seen from Fig. 4, the Cu deposited on p-type Si(100) has a similar result as that on n-type Si(100). Except the growth rate of the Cu film p-type silicon is slower than that on n-type silicon, and it may be due to fewer electrons being available to reduce Cu ions. promotes

Model of copper deposited on stripped silicon

The model of depositing Cu line on Si with positive photoresist as a mask is illustrated in Fig. 5. Figure S(a) is the beginning of Cu deposition. Positive photoresist, an insulator, cannot provide electrons and induces no growth on it. When copper ions diffuse near the surface of bare silicon, they take electrons from silicon unmasked by PR and the Cu is deposited there. At the center of the window, the electrons mainly come from the underlying silicon. However, at the edge of the window, more electrons from more than one direction are available to reduce copper ions. Therefore, the Cu film thickness is thicker around the window than at the center of the

window. as shown in Fig. 5(b). After deposition, the silicon becomes a trench-like shape in cross-section and the deposited Cu has larger clusters around the window, as shown in Fig. 5(c). However, as the width of the window is small enough, the edge clusters will be quickly merged together as shown in Fig. 5(d). In this case, the copper in the window has a uniform thickness after deposition as shown in Fig. 5(e). In addition, the etch rate of silicon in the downward direction is faster than that of the lateral direction in the trench, owing to the orientation dependence. Figure 6 shows the top views of Cu deposited on the bare silicon with PR mask from Nomarski optical microscopic observation. The line widths are 55, 7, 5.5 pm in Fig. 6(a), (b) and (c), respectively. These lines are all on a Si wafer which is immersed in the solution of 4.13 x lo-’ wt.% diluted HF and 0.045 M CuS04 for 5 min. Figures 6(a) and (b) are the results of Fig. 5(c), and Fig. 6(c) is the result of Fig. 5(e), respectively. From the pictures, the threshold linewidth for uniform Cu interconnect is around 6 pm in this case. Of course, it is dependent on the copper thickness and the type of substrate. From the observation of SEM cross-section, an undercut is formed under S&N4or photoresist masks, which shows an isotropic etching property of the Cu deposition. Schottky barrier height The SBH value is determined by extrapolating the forward semilogarithmic Z-V characteristics of the

Cu deposition on silicon metal-semiconductor contact to zero applied voltage. In addition, from the Z-V characteristics measured in dark circumstance, we obtain the leakage current and ideality factor. From the forward Z-V characteristics of Cu on n-type (100) Si, we have found that the leakage current density, J,, is 3.628 x 10-4A/m2, the SBH (&,“) is 0.622 (eV) and the value of cut-in voltage is 0.28 V. The SBH value is larger than that of the report by Sze (0.58 eV)[13], and of 0.61 + 0.02 (eV) by Hirose et a1.[14]. It could be the result of no trace of oxide existing at the interface of Cu and Si from the in situ etching property of the Cu deposition method, but, the ideality factor (n) of the diode is 1.375 and it may be associated with the result of rough interface caused by the hydrofluoric acid[l5].

701

We investigate the relation of leakage current and ideality factor with deposition time as shown in Fig. 7 (a) and (b). The leakage current and the ideality factor increase with deposition time. It may be from that, that a rougher interface is obtained for longer deposition time owing to the substrate defects etching by HF. Therefore, copper is deposited with pits, which causes larger leakage current and ideality factor. We also derive the barrier height, leakage current density and ideality factor of Cu on p-type Si, and obtain the values, q&P= 0.54 eV, Js = 8.594 x lo-’ A/m2 and n = 1.236. This SBH value is again higher than the reports of Sze (0.46eV) and Hirose (0.50 eV)[ 11,131. The leakage current and ideality factor increase with deposition time, shown in Fig. 7 (a) and (b). Those results indicate that the Cu on

1.2OE-02

0.7

l.OOE-02

0.6

_ 8.00E03 1 3 6.OOEGO3

______ SBH l

z 4.ooE-03

n

Js n-Si p-Si

2.00E03 O.OOE+OO

1.6

5

Time (min)

Fig. 7. Leakage current (a) ideality factor (b) vs deposition time. The growth solution is of 4.13 x IO-’ wt.% DHF and 0.045 M CuSO,.

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p-type Si has a larger leakage current, which is due to a lower SBH value than that of Cu on n-type Si. As for the better ideality factor than that on p-type Si, it may be resulting from the fewer electrons available from p-type Si to reduce copper ions, then

deposition methods like CVD-Cu or electroless-Cu deposition etc.

cause the less roughness

under Contract no. NSC 79-0414EIIO-001.

at the interface.

From

the

Acknowledgements The authors would like to thank the support of National Science Council of Republic of China

above discussion, the dependence of Js and n on the thickness and roughness might be from the size of the copper grain.

REFERENCES

Pai, Pei-Lin and Ting, Chiu H., IEEE Transactions of Electron Device Letters, 1989, 10, 423. Carlsson, J., in Solid State Devices, eds G. Soncini and

CONCLUSION

Here we have investigated the kinetics of the novel Cu deposition on silicon. The copper film thickness varies with the square root of the deposition time and copper ion concentration. This indicates that the Cu film growth kinetics is diffusion limited. In addition, hydrofluoric acid is an important parameter to increase the film growth rate. It has a similar effect on depositing the Cu on n-type and p-type silicon, but yields a higher growth rate on n-type Si. The Cu growth rate could be increased to 2200 &min on n-type silicon when the CuS04 concentration is 0.125 M. The Cu deposited on silicon strip shows an isotropic etching property. Therefore, an undercut against the mask after copper deposition is observed. The Cu deposited on silicon shows a Schottky diode behavior with a barrier height & = 0.622 eV for n-type and &, = 0.540 eV for p-type silicon. These values are higher than those of other reports. The leakage current and ideality factor both increase with the deposition time. The novel Cu deposition method has a potential application in recess source and drain contacts for MOS and poly-TFT devices. In addition, in order to have a very cleaned interface, the copper film used in ULSI can be first deposited by this method by means of its in situ etching property and followed by other

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