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A Daisy architecture for the multiprocessor real time data acquisition system of the Thor Tokamak experiment
Memo~ Bagnall, P and Furnweger, C 'Hierarchical memory features multilevel access paths' Digital Des. Vol 16 No 8 (May 1986) pp 67-70 MOS memories have polarized towards the slow DRAM or the expensive SRAM. A hierarchical RAM (HRAM) from Visic, claim the authors, offers performance at reasonable cost by using a new three-level hierarchy in the memory organization, which gives three levels of access time. Features of the memory are presented.
Cantrell, T 'Static RAM uses smarts to control dual-port access' Electronic Des. Vol 34 No 15 (26 June 1986) pp 115120 Smart dual-port RAMs merge standard memory features with intelligence to cater for arbitration disputes in multiprocessor systems. An example of a smart dual-port RAM from Hitachi is described.
Microprogramming Davidson, S 'Progress in high-level microprogramming' IEEESoftware Vol 3 No 4 (July 1986) pp 18-26 Meuller, R A and Duda, M R 'Formal methods of microcode verification and synthesis'IEEESoftware Vol 3 No 4 (July 1986) pp 38-48 Vegdahl, S R 'Microcode optimization: examples and approaches' IEEESoftware Vol 3 No 4 0uly 1986) pp 59-68 Winner, R I and Carter, E M 'Automated vertical migration to dynamic microcode: an overview and example' IEEE Software Vol 3 No 4 (July 1986) pp 6-16 These four papers appear in a special issue on 'Firmware engineering: the interaction of microprogramming and software technology'. Davidson
398
examines several approaches to highlevel microprogramming. A high-level microprogramming language would decouple algorithm design from microcodinp~ he says, but although higher level languages are an active field of microprogramming research, a widely accepted language has not yet emerged. Microcode has traditionally been written in assembly language, but optimizing compilers can reduce the workload on firmware engineers. These compilers do not produce code as efficient as that produced by a good microprogrammer, however. Vegdahl examines compilers for micromachine target architectures.
Multiprocessors Axelrod, T S 'Effects of synchronization barriers on multiprocessor performance' Parallel Comput. Vol 3 No 2 (May 1986) pp 129-140 While most theoretical analyses predict that speed increases monotonically with the number of processors, actual experience with large numbers of processors shows that a speed maximum occurs at a 'discouragingly' small number of processors. The reason for this discrepancy, says Axelrod, is almost always due to the synchronization requirements of the algorithms used and on the method of implementing synchronization on the hardware. A form of synchronization, the barrier, and its effect on multiprocessor performance are discussed.
Chao, Y 'Multiple-microprocessor/microcomputer performance: what to acquire and how to evaluate: a status report' Microproc. Microprog. Vol 17 No 5 (May 1986) pp 267-276 Velardi, P and Forcina, A 'Reliability analysis of multipath interconnection networks' Microproc. Microprog. Vol 17 No 5 (May 1986) pp 255-265 Multistage interconnection networks (MINs) are employed for switching
systems and multiprocessor corn-. puters. The paper presents the architecture of a particular multipath MIN and compares its reliability performance with two multipath networks described in the literature.
Networks Nagasawa, M, Hiramatsu, Y and Takami, K 'Packet switching network access protocols for multi-media packet communications'JIERE Vo156 No 6/7 0une/July 1986) pp 243-247 Integration of data, voice and vide() communications based on packet switching principles is, say the authors, becoming promisingfrom the economic and user interface standpoints. Up to now, voice and video have been carried out on circuit switched networks. On the other hand, data communications use packet switched and circuit switched networks. The paper proposes a multi-media packet protocol for packetized data, voice and video communications.
Realtime systems Annunziata, M, Cima, G, Mantica, P and Sechi, G R 'A Daisy architecture for the multiprocessor real time data acquisition system of the Thor Tokamak experiment' Microproc. Microprog. Voi 17 No 5 (May 1986) pp 285-296 The Thor machine is a Tokamak type device for toroidal plasma magnetic confinement, and is used in thermonuclear fusion research, The hardware system built for the Thor Tokamak experiment consists of several microcomputers controlled by a central minicomputer. Solutions adopted for data acquisition, storing, processing and displayin~ and for error handling are described.
Halang, W A 'On methods for direct memory access, without cycle stealing' Microproc. Microprog. Vol 17 No 5 (May 1986) DD 277-283 microprocessors and microsystems
Cantrell, T 'Static RAM uses smarts to control dual-port access' Electronic Des. Vol 34 No 15 (26 June 1986) pp 115120 Smart dual-port RAMs merge standard memory features with intelligence to cater for arbitration disputes in multiprocessor systems. An example of a smart dual-port RAM from Hitachi is described.
Microprogramming Davidson, S 'Progress in high-level microprogramming' IEEESoftware Vol 3 No 4 (July 1986) pp 18-26 Meuller, R A and Duda, M R 'Formal methods of microcode verification and synthesis'IEEESoftware Vol 3 No 4 (July 1986) pp 38-48 Vegdahl, S R 'Microcode optimization: examples and approaches' IEEESoftware Vol 3 No 4 0uly 1986) pp 59-68 Winner, R I and Carter, E M 'Automated vertical migration to dynamic microcode: an overview and example' IEEE Software Vol 3 No 4 (July 1986) pp 6-16 These four papers appear in a special issue on 'Firmware engineering: the interaction of microprogramming and software technology'. Davidson
398
examines several approaches to highlevel microprogramming. A high-level microprogramming language would decouple algorithm design from microcodinp~ he says, but although higher level languages are an active field of microprogramming research, a widely accepted language has not yet emerged. Microcode has traditionally been written in assembly language, but optimizing compilers can reduce the workload on firmware engineers. These compilers do not produce code as efficient as that produced by a good microprogrammer, however. Vegdahl examines compilers for micromachine target architectures.
Multiprocessors Axelrod, T S 'Effects of synchronization barriers on multiprocessor performance' Parallel Comput. Vol 3 No 2 (May 1986) pp 129-140 While most theoretical analyses predict that speed increases monotonically with the number of processors, actual experience with large numbers of processors shows that a speed maximum occurs at a 'discouragingly' small number of processors. The reason for this discrepancy, says Axelrod, is almost always due to the synchronization requirements of the algorithms used and on the method of implementing synchronization on the hardware. A form of synchronization, the barrier, and its effect on multiprocessor performance are discussed.
Chao, Y 'Multiple-microprocessor/microcomputer performance: what to acquire and how to evaluate: a status report' Microproc. Microprog. Vol 17 No 5 (May 1986) pp 267-276 Velardi, P and Forcina, A 'Reliability analysis of multipath interconnection networks' Microproc. Microprog. Vol 17 No 5 (May 1986) pp 255-265 Multistage interconnection networks (MINs) are employed for switching
systems and multiprocessor corn-. puters. The paper presents the architecture of a particular multipath MIN and compares its reliability performance with two multipath networks described in the literature.
Networks Nagasawa, M, Hiramatsu, Y and Takami, K 'Packet switching network access protocols for multi-media packet communications'JIERE Vo156 No 6/7 0une/July 1986) pp 243-247 Integration of data, voice and vide() communications based on packet switching principles is, say the authors, becoming promisingfrom the economic and user interface standpoints. Up to now, voice and video have been carried out on circuit switched networks. On the other hand, data communications use packet switched and circuit switched networks. The paper proposes a multi-media packet protocol for packetized data, voice and video communications.
Realtime systems Annunziata, M, Cima, G, Mantica, P and Sechi, G R 'A Daisy architecture for the multiprocessor real time data acquisition system of the Thor Tokamak experiment' Microproc. Microprog. Voi 17 No 5 (May 1986) pp 285-296 The Thor machine is a Tokamak type device for toroidal plasma magnetic confinement, and is used in thermonuclear fusion research, The hardware system built for the Thor Tokamak experiment consists of several microcomputers controlled by a central minicomputer. Solutions adopted for data acquisition, storing, processing and displayin~ and for error handling are described.
Halang, W A 'On methods for direct memory access, without cycle stealing' Microproc. Microprog. Vol 17 No 5 (May 1986) DD 277-283 microprocessors and microsystems