A Distributed SPICE Model for Amorphous Silicon Solar Cells

Available online at www.sciencedirect.com

ScienceDirect Energy Procedia 60 (2014) 96 – 101

E-MRS Spring Meeting 2014 Symposium Y “Advanced materials and characterization techniques for solar cells II”, 26-30 May 2014, Lille, France

A distributed SPICE model for amorphous silicon solar cells Y. Vygranenkoa,b,*, M. Fernandesa,b, M. Vieiraa,b, A. Khosropourc, A. Sazonovc a

Electronics Telecommunications and Computer Engineering, ISEL, Lisbon, 1950-062, Portugal b CTS-UNINOVA, Quinta da Torre, 2829-516, Caparica, Portugal c Electrical and Computer Engineering, University of Waterloo, Waterloo, N2L 3G1, Canada

Abstract This article reports on amorphous silicon solar cells on plastic foils in the substrate configuration having a front metal grid. A two-dimensional distributed circuit model of the photovoltaic cell has been developed for performance analysis and device design optimization. The circuit simulator SPICE is used to calculate current and potential distributions in a network of sub-cell circuits. This approach enables a realistic device model that predicts output current-voltage characteristics and maps Joule losses in the TCO electrode and the metal grid. As an example of usage, the optimization of contact grid geometry at various TCO sheet resistances has been performed. © 2014 Published by Elsevier Ltd. This is an open access article under the CC BY-NC-ND license © 2014 The Authors. Published by Elsevier Ltd. (http://creativecommons.org/licenses/by-nc-nd/3.0/). Peer-review under responsibility of the scientific committee of the SiliconPV 2014 conference. Peer-review under responsibility of The European Materials Research Society (E-MRS) Keywords: Solar cell; SPICE; circuit modelling; amorphous silicon.

1. Introduction Solar cells on lightweight and flexible substrates have advantages over the glass- or wafer-based photovoltaic devices in both terrestrial and space applications [1]. Flexible devices can be installed on curved surfaces, they are less likely to be damaged by mechanical friction and vibrations, and are easier to install. These advantages could make it possible for mobile devices and various electric appliances to cover part of their power demand from solar energy. Even the integration of photovoltaics in clothes becomes a reality [2]. Also light weight photovoltaic (PV) * Corresponding author. Tel.: +351-21-831-7287; fax: +351-21-831-7114. E-mail address: [email protected]

1876-6102 © 2014 Published by Elsevier Ltd. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/3.0/). Peer-review under responsibility of The European Materials Research Society (E-MRS) doi:10.1016/j.egypro.2014.12.349

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modules on plastic foils are attractive for aerospace applications because they present a higher power-to-weight ratio in comparison to common GaAs-based PV devices [3]. In this work, we report on a monolithic a-Si:H-based photovoltaic module utilizing 100 μm thick polyethylenenaphtalate (PEN) film as a substrate. To reduce the mechanical stress in the n-i-p cells, the thickness of the top transparent electrode is reduced in comparison to thin-film solar cells utilizing transparent conducting oxide (TCO) with a sheet resistance of ~10 Ÿ/sq. Our device has a top metal grid that compensates the increase in TCO sheet resistance thus keeping low the emitter resistance. We also present a two-dimensional distributed circuit model for a cell of proposed design, which is used for device performance analysis and design optimization. Solar cell modelling based on electrical networks is a well-established technique [4-6]. The model implementation has been done similar to simulation tools described in the literature [7-9]. 2. PV module design Figure 1a shows a photograph of the developed PV module. The 10 cm × 10 cm area module integrates an array of 72 rectangular cells. The individual cells are connected in series forming eight rows with connection pads. The cell design and its interconnections are illustrated in Figs. 1b and 1c. To relieve the mechanical strain, the backside encapsulation and front buffer a-SiOxNy layers are oxygen-rich and nitrogen-rich, respectively. The cell is an a-Si:H n-i-p structure integrating Al/Cr and ZnO:Al as back and top electrodes, respectively. The sheet resistance of the 180-nm-thick ZnO:Al layer is about 60 :/sq. Two 0.3 mm wide Al fingers are symmetrically placed on the ZnO:Al electrode to reduce the emitter resistance. In the developed fabrication process, three shadow masks are used in sputtering steps to form the bottom and top electrodes, and top metallization. The n-i-p stack is deposited using a multi-chamber 13.56 MHz PECVD system at 150 oC. The deposition conditions for the a-Si:H n-i-layers and the a-SiC:H p-layer are reported elsewhere [10,11].

a

b

TopMetallization

aͲSi:HNIP

ZnO:Al

Bottom Electrode

aͲSi:HNIP

Buffer dielectric (a-SiOxNy) Substrate(100umthickPENfilm) Encapsulation dielectric (a-SiOxNy)

c

ZnO:Alelectrode

Df

Lf

Alfinger Bottom Electrode

H

Fig. 1. (a) Photograph of the PV module; (b) cross-sectional view of the cells; (c) top view of two cells connected in series.

3. SPICE model Figure 2 illustrates the proposed electrical model, where the individual cell is divided into equidimensional rectangular subcells with a node at the center of each sub-cell. The proposed equivalent circuit of the sub-cell includes a diode, a current source representing current generation in the n-i-p structure, a resistor, Rp, including both the resistance of the p-layer and contact resistance of the p/ZnO:Al interface, and resistors Rx and Ry representing the top metallization and (or) transparent electrode, respectively. Note that the sheet resistance of the bottom metal is at

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Y. Vygranenko et al. / Energy Procedia 60 (2014) 96 – 101

Node(i,j) Rx Ry

Ry

least two orders of magnitude lower than that of the ZnO:Al layer, and this series resistance component is not taken into account. Nodes at the front edge of the Al grid are defined as the current sink in this model with the boundary condition being the applied bias. Resistors Rx and Ry are defined as

Rx

Rp

Iph

Y

Rx

Rsheet Lx 2L y

(1)

Ry

Rsheet L y , 2 Lx

(2)

where Rsheet is the sheet resistance of the layer(s), Lx and Ly are the dimensions of the cell element in X-Y plane. The value of resistor Rp is

X

Rp

Algrid

Vbias TCO n

i

p

Al

Fig. 2. The cell element to be modeled and equivalent circuit of the sub-cell.

dp

V p Lx L y



Rc , Lx L y

(3)

where dp is the thickness of the p-layer, Vp the conductivity of the p-layer, and Rc the contact resistance of the p/TCO interface. The diode forward current is

I

q0V J o Lx Ly [exp(nkT )  1] ,

(4)

where qo is the elementary charge, Jo the saturation current density, n the photodiode ideality factor, k is Boltzmann’s constant, and T the temperature.

The output of the current source is given by

I ph

J ph Lx Ly ,

(5)

where Jph is the photocurrent density. For a-Si:H p-i-n cells, the Jph is a bias voltage dependent function [12] VP º , V  Vbi ª )» «1  exp( Vbi ¬ V  Vbi ¼

J ph

J sc

VP

d i2 ,

PW

(6a) (6b)

where Jsc is the short-circuit current, Vbi the built-in voltage, di the i-layer thickness, and PW the mobility-lifetime product also known as the range of the carriers (i.e., distance drifted before capture per unit field). We used HSPICE simulator to perform calculations, while MATLAB was used to create so-called “net list” file, to readout data from the output file, and to visualize the results. In particular, analyzing the simulated J-V curve, the developed tool calculates the maximum power point, Imax and Vmax, fill factor (FF), and power conversion efficiency (PCE), and saves them in a data structure. Then, the current and voltage drop across each circuit element are processed to plot the current density, potential and Joule losses distributions across the emitter.

Y. Vygranenko et al. / Energy Procedia 60 (2014) 96 – 101

4. Device modelling The device modelling was performed using the following input parameters: RTCO = 60 :/sq., Rmetal = 0.2 :/sq., Rp = 1.5 :˜cm2, Jo = 10-12 A/cm2, n = 1.5, Vbi = 1.1 V, VP = 0.1 V, and Jph,0 = 12.5 mA /cm2. Cell area was 5 x 10 mm2. The metal finger width (Wf) and length (Lf) were set to 0.3 and 8 mm, respectively. Figure 3a shows a simulated J-V curve. The indicated solar cell performance characteristics are in a good agreement with that for optimized a-Si:H solar cells under AM1.5 illumination conditions. Figure 3b shows simulated potential distribution across the emitter at Vmax = 0.722 V. Here, the voltage drop across the metal finger is 12 mV and voltage variation across the transparent electrode is up to 45 mV. The lateral current flow in the TCO and top metal layers is shown in Fig. 3c. The current density at node (i,j) is given by

a

b

6

Current (mA)

5 4

Cell area = 0.5 cm Vmax = 0.722 V

3

Voc = 0.8839 V

2

FF = 0.7027 PCE = 7.0 %

2

Imax = 4.8 mA Isc = 5.6 mA

1 0 0.0

0.2

0.4

0.6

0.8

1.0

Voltage (V)

c

d

Fig. 3. (a) Simulated current-voltage characteristics; (b) potential distribution across the emitter at a maximum power point; (c) current density distribution; (d) Joule losses in the TCO electrode and metal finger.

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I x2 (i, j ) / L2y  I y2 (i, j ) / L2x ,

J i, j

(7)

where Ix(i,j) and Iy(i,j) are the X-Y plane current components associated with resistors Rx and Ry, respectively. Figure 3d shows Joule losses in the emitter at the maximum power point. Two sharp peaks are observed in the TCO area because of the increased current density at the metal finger corners. The grid electrode optimization requires balancing the resistance losses against other related losses such as grid electrode shadowing. Figure 4 shows the PCE as a function of distance between metal fingers (Df) at various Lf. The calculations were performed at RTCO = 60 :/sq. and Rmetal = 0.2 :/sq. From the results, the values Df = 5 mm and Lf = 8 mm are to be optimal for 10 mm × 10 mm cell having two fingers. Figure 5 shows PCE-Df curves calculated at various sheet resistances of the TCO layer. For cells with 10 and 60 :/sq. TCO layers the difference in power conversion efficiency is up to 0.23%. In practice, this difference may be even lower due to an increased absorption loss in the thicker TCO layer.

Lf:

7.0

Lf = 8 mm

7.0

PCE (%)

6.9 PCE (%)

7.2

5 mm 6 mm 7 mm 8 mm 9 mm 9.5 mm

6.8 6.7

6.8 6.6 RTCO(:/ sq.): 10 60 100 150 200

6.4 Lf

6.6 6.5

6.2

0

2

4

6

8

10

Df (mm) Fig. 4. Power conversion efficiency as a function of Df at various finger lengths.

6.0

2

4

6

8

10

Df (mm) Fig. 5. Power conversion efficiency as a function of Df at various sheet resistances of the TCO layer.

5. Conclusion A two-dimensional distributed circuit model of the photovoltaic a-Si:H cell having metal grid electrodes has been developed. Solar cell parameters were estimated from the simulated current-voltage characteristics. Current and potential distributions across the emitter were determined. Joule losses in the TCO electrode and metal finger were also mapped. The optimal length of the metal finger in the proposed cell configuration is about 80% of the cell length at 60 :/sq. sheet resistance of the TCO layer. Due to the front metal grid, the optimized cell with a thinner transparent electrode yields almost the same power conversion efficiency in comparison to the cell of conventional design with 10 :/sq. TCO. Acknowledgements The authors are grateful to the Portuguese Foundation of Science and Technology through research Project PTDC/EEA-ELC/115577/2009 for financial support of this research, and to the Giga-to-Nanoelectronics Centre at the University of Waterloo for providing some necessary equipment and technical help to carry out this work.

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