A DSSS-Based Wireless Short Range Data-Link

A DSSS-Based Wireless Short Range Data-Link

© Urban & Fischer Verlag http://www.urbanfischer.de/journals/aeue A DSSS-Based Wireless Short Range Data-Link Stefan Lindenmeier and Anestis Terzis D...

281KB Sizes 3 Downloads 35 Views

© Urban & Fischer Verlag http://www.urbanfischer.de/journals/aeue

A DSSS-Based Wireless Short Range Data-Link Stefan Lindenmeier and Anestis Terzis Dedicated to Professor Peter Russer on the occasion of his 60th birthday Abstract: The system concept for the physical layer of a wireless high speed data-link is introduced for local-area-ad-hoc-networks in mobile applications. The high speed data-link is based on a direct sequence spread spectrum system. The dynamic losses in a incoherent receiver at 24.1 GHz are investigated. Keywords: DSSS, Mobile, Wireless, Demodulation, Signal processing

1. Introduction There is an increasing demand for low cost high speed wireless ad-hoc-networks in mobile applications for multi-media applications in mobile systems as e.g. WPAN [1] and WLAN-systems [2]–[4] being already available in cars, as well as inter vehicle communication [5],[6]. For mobile ad-hoc-networks there are special demands to be fulfilled like high dynamics, channel separation and high immunity against external interferers. Code Division Multiple Access-wireless systems have proven to fulfill these demands well, if there is enough bandwidth available [7]–[11]. The direct sequence spread spectrum (DSSS) of the CDMA-systems with high chiprate enables channel separation, a high immunity against external interferers and the transmission with low average emission level. In this paper we introduce the physical layer of a CDMA-DSSS wireless short range data-link where a flexible DSSS system is used for the data transmission of variable data rates. The main requirement for the data-link is to achieve a reliable ( pe < 2 · 10−4 ) wireless bi-directional data transmission with a variable data rate of up to 12 Mbit/s. The transmission should not be locatable from far distance and therefore the operation range should be limited to 10 m. Since the transmission is appropriate for sensitive data, it should be secure against jamming, interference and interception. The considered wireless link represents the physical layer of a wireless network with ad-hoc abilities. An ad-hoc wireless network is a collection of wireless mobile hosts forming a temporary network without the aid of any established

Received August 23, 2002. Revised November 12, 2002. DaimlerChrysler Research Center, Wilhelm-Runge-Strasse 11, 89081 Ulm, Germany. Phone: +49/731505-2024, Fax: -4102. Correspondence to S. Lindenmeier. E-mail: [email protected] ¨ 57 (2003) No. 3, 161−167 Int. J. Electron. Commun. (AEU)

infrastructure or centralized administration. This type of network is of great importance in situations where it is difficult to provide the necessary infrastructure e.g. in mobile wireless systems, but it is a challenging task to enable fast and reliable communication (and link establishment) within such a network. A small current consumption must be achieved in order to prevent a strong load of the batteries in the mobile system. In order to fulfill all these requirements, a special system concept has been compiled. The immunity against jamming and eavesdropping are to be achieved by a DSSS-transmission. In such a system data can be hidden in the background noise by spreading its bandwidth with a pn (pseudo random noise)-code and transmitting the resulting signal at a low average power. Because of its low power level, the transmitted signal has a low probability of being intercepted by an unauthorized participant. Furthermore the data can only be demodulated by a receiver which knows the applied pn-code. The transmitting power should be adjustable over an automatic control loop so that during a reliable transmission the position of the transmitters cannot be located (range < 10 m). By this “minimum power consumption” also battery operation is possible.

2. System architecture of the wireless data-link In the following the system concept is shown (Fig. 1). The homodyne data-link is divided into a digital signal processing unit and an RF-frontend. Since the concept of the data-link must be flexible with respect to variable data rates, also the baseband signal processing must be adaptable to variable data rates. That’s why for this stage of the investigation a field programmable gate array (FPGA) is chosen for the realization of the digital part since FPGAs are freely programmable and hence, a change of the data rate and the signal processing will not need a change of the hardware. An essential question for the RF-part is the operating frequency band. The frequency band determines also the antenna size and the available bandwidth. For the data-link the 24.1 GHz ISM band has been selected which is license-free available. The available bandwidth is 250 MHz and hence, the use of small antennas with adaptable gain and the application of digital beamforming is possible. While in the very common ISM frequency bands at 2.4 GHz and 5 GHz there are lots of services leading to possible interference’s, the probability of inter1434-8411/03/57/03-161 $15.00/0

162 S. Lindenmeier, A. Terzis: A DSSS-Based Wireless Short Range Data-Link

Fig. 1. System architecture of the physical layer of the wireless short range data-link.

ference’s are more improbable at 24.1 GHz from today’s view. In addition, the freespace path loss is also higher at 24.1 GHz. Therefore the emitted signals do not harm other systems and the own system can not be located easily from far distances. The digital circuit consists of two parts – the transmitting path and the receiving path. In the transmitting path, the binary data d(t) is multiplied with the pn-code c(t), to produce the transmitted baseband signal g(t) = d(t) · c(t). In order to be able to differentiate between the terms bit and bit rate of the pn code we designate it as chip and chip rate [8]. For a number of n chip in one code sequence the chip rate of the pn-code c(t) is n-times greater than the data rate of d(t). The effect of multiplication of d(t) with the pn-code is to spread the baseband bandwidth of d(t) to the baseband bandwidth of the pn-code c(t) witch is also much greater [11] and hence less sensible against interferences. The digital part must first synchronize the incoming data with the pn-code. This means that the starting time and stop time of the pn-code agree with the starting time and the stop time of the data bits. After this synchronization the multiplication is be performed. The chip rate C is a multiple of the data rate D with C = n · D where n is the number of chips in the pncode sequence. Hence the resulting transmitted baseband signal g(t) has got the chip rate C of the pn-code. This signal, produced in the digital part, is then modulated in the RF-part. In order to realise a BPSK-based transmission an RFfrontend with stable RF-source is required where the carrier frequency of the VCO is controlled via a phase locked loop which yields synchronization with the clock frequency. For the clock a stable quartz oscillator is used. After the demodulation of the received signal into the baseband the signal is transferred into the FPGA

via an A/D-converter. In the receiving path of the digital circuit the received signal has to be despreaded. In order to despread the received signal, it has to be correlated with the same synchronized pn-code (the pncode used in the transmitter). This operation is called despreading, since the effect is to undo the spreading operation at the transmitter [7]. Therefore a correlation receiver has been implemented into the FPGA. The received signal is then correlated with the pn-code. A decision logic derives then the transmitted data signal from the correlation. In the receiving path the amplitude of the received signal is determined by an A/D-converter after the demodulation. The output of the A/D-converter is also routed to the FPGA. Using a special closed loop control (witch is adapted to the characteristic of the output amplifier) the power of the transmitter is controlled. In what follows the gain of the correlation receiver due to the SS-system is investigated in dependence to the frequency deviation between the carrier frequency of the received signal and the frequency of the RF-source used for demodulation in an incoherent receiver. The correlation gain is used to increase the signal noise ratio of the spread spectrum system and is hence an essential value of the concept. After the received signal r(t) is transferred to the digital level in the FPGA the signal is sampled with a sampling rate of four time steps per chip using four parallel correlators. In Fig. 2. the signal is shown for the case of a pn-code of length n = 7. Because of the incoherent transceiver there is a frequency shift of ∆ω between the carrier frequency of the received signal and the frequency of the VCO used for down-conversion. This signal is correlated with the pncode sequence c(t). The sequence length is n, the duration of a chip is ∆t = 1/C and the pn-code duration

S. Lindenmeier, A. Terzis: A DSSS-Based Wireless Short Range Data-Link 163

Fig. 2. left side: received signal after demodulation in a coherent receiver; right side: received signal after demodulation in an incoherent receiver for a relative frequency deviation of 0.01% at 24.1 GHz and a data rate of 12 Mbit/s.

is T = 1/D = n · ∆t. (n−1)/2

c(t) =





 pn i−τ/∆t Π(t − i∆t − τ) ;



 pn i b(t − i∆t) · e− j∆ωt

i=−(n−1)/2 (n−1)/2

r(t) =



(1)

i=−(n−1)/2

The signal r(t) is derived from the pn-sequence which has been band limited by a bandpass filter with the function f(ω) in order to restrict the transmitted signal to a bandwidth of 250 MHz. b(t) = Π(t/∆t)∗ F −1 { f(ω)}

(2)

The correlation function between the pn-code and the received signal is 1 Rc (τ, ∆ω) = ∆t

T/2 c(t) · r(t − τ)dt .

Fig. 3. Correlation after demodulation in an incoherent receiver for a relative frequency deviation of 0.01% at 24.1 GHz and a data rate of 12 Mbit/s, comparison with the auto-correlation function Ra .

(3)

−T/2

The time shift of τ = 0 in the case of synchronization of the pn-code with the pn-code in the received signal which is ensured via a tracking algorithm realized in the FPGA. In Fig. 3. the correlation function is shown for the case of a frequency deviation of 0%, 0.01% at 24.1 GHz at a data rate of 12 Mbit/s. Now we want to consider the worst case for the correlation gain in dependence of the frequency shifts ∆ω. The gain can be obtained from the maximum values of the correlation function which occur at τ = 0. Following [8],[9] we obtain for the correlation gain   G(∆ω) = 10 lg  Rc (0, ∆ω) (4)

In the ideal case, for the auto-correlation of the pn-code, the gain is G max = 10 lg(n) where n is the number of chips in the code. In Fig. 4. the absolute value of the correlation function is shown for the case of a frequency deviation of 0%, 0.01%, 0.02% and 0.03% at 24.1 GHz at a data rate of 12 Mbit/s. As can be seen, even in a coherent receiver, for the frequency deviation of 0%, the maximum values of the correlation function and hence the correlation gain G are 16% lower than the ideal auto-correlation value. This is because of the bandpass filtering of the signal with a bandwidth of 250 MHz. We see that for a noncoherent receiver with a frequency deviation of 0.01%, we still obtain a good correlation gain which is only 7% lower than for the case of a coherent receiver. In order to obtain a general behavior of the Gain dependent to the fre-

164 S. Lindenmeier, A. Terzis: A DSSS-Based Wireless Short Range Data-Link For the worst case consideration we can assume the same pn-code pn i = (−1)i {i ∈ IN} for all frequency shifts ∆ω. Hence we derive   Rc (0, ∆ω)|min       1  4  πt   =  F cos · Π(t/T ) (8)    ∆t π ∆t ω=∆ω

Fig. 4. Absolute value of the correlation Rcm with a relative frequency deviation of m · 0.01% for m = 0, 1, 2, 3 at 24.1 GHz and a data rate of 12 Mbit/s; comparison with the auto-correlation function Ra .

quency deviation, the number n of chips in the code and the data bitlength T we consider the behavior of the correlation function more closely. From Eqns. (1), (2) and (3) we obtain ∞ (n−1)/2    1 Rc (0, ∆ω) = Π(t/T ) · pn i b(t − i∆t) ∆t −∞

(n−1)/2

×





i=−(n−1)/2

 pn i− Π(t/∆t − i) · e− j∆ωt .

(5)

i=−(n−1)/2

after some derivations we obtain 1 Rc (0, ∆ω) = F ∆t    (n−1)/2      pn i b(t − i∆t) · Π(t/T ) ×   i=−(n−1)/2

. (6)

ω=∆ω

The consideration is based on the assumption of an ideal filter function f(ω) = Π(ω∆t/4π). In the case of synchronization τ = 0 we obtain the minimal value of |Rc (0, 0)| with an “oscillating” pn-code pn i = (−1)i {i ∈ IN}. From (6) we obtain 1 |Rc (0, 0)|min = F ∆t    (n−1)/2     (−1)i b(t − i∆t) · Π(t/T ) ×   i=−(n−1)/2

   1 4  πt  = F cos · Π(t/T ) ∆t π ∆t  ω=0

 ω∆t for f(ω) = Π . 4π

ω=0

With the assumption of a codelength of n ≥ 7 chips we can approximate the correlation gain for the interesting range of ∆ω with high accuracy and a deviation δG of less then 1%.  

 8n ∆ωT (1 + δG ) G min = 10 lg 2 si π 2 

 8n ∆ωT ≈ 10 lg 2 si π 2 with |δG | < 1% for ∆ω <

2π T

(9)

In the case of the considered wireless link the data rate is D = 12 Mbit/s which means T = 83 ns. For a relative frequency shift of 0.01% at 24.1 GHz which can be reached without high effort in the above shown frontend concept, we obtain at least a correlation gain of 9.5 dB using the estimation of (9). This gain is sufficient for the above mentioned demands. Based on the observation of r(t) a digital receiver for the data recovery has been designed in the FPGA, minimizing the bit-error rate by enabling a high SNR due to the correlation gain [11],[13]. In order to implement such a receiver in the FPGA we have to divide the receiver into two parts – the demodulator and the digital detector. In the block demodulator the correlation function Rc (t) is calculated. The exit of this block supplies the value of the correlation function Rc (t), which depends on the match of the signals. The digital detector works according to the principle of a threshold-level-Detector for the search of the correlation maximum in order to synchronise the pn-code in the received signal with the pn-code in the receiver in a tracking algorithm. The basic structure of the correlation receiver (Fig. 5) works reliably only if the phase of the incoming signal r(t) agrees with the phase of c(t). In order to compensate this uncertainty, in the implementation several identical correlation receivers are used in parallel. These receive all the same signal r(t) at their inputs and differ only in the phase position from c(t). A special decision logic derives the signal value

n⋅Tc

r

∫ ( )dt 0

c(t)

Demodulator

R

Digital Detector

Digital Detector

(7) Fig. 5. Basic structure of the correlation receiver.

da(t)

S. Lindenmeier, A. Terzis: A DSSS-Based Wireless Short Range Data-Link 165

from the results of the individual receivers and assigns these to da (t). The complete correlation receiver is then implemented using the hardware description language VHDL. The circuit is flexibly developed so that without large expenditure other codes can be used. The threshold values are also adjustable flexibly. Thus the circuit can be extended to an automatic threshold level control as it is discussed in [14]. For the wireless data-link two advantageous spreading codes have been designed, having the length of 8 chip and 12 chip respectively. These codes are able to increase the signal noise ratio considerably by an order of magnitude but they cannot be used for the channel separation of more than three participants if we are using small codes with up to 12 chips. The small number of chips in the codes is restricted by the ratio between the allowed bandwidth and the data rate. In the system concept the channel separation is supported by an additional TDMA protocol.

3. Realization and measurements The entire circuit of the data-link has been described in VHDL, simulated and implemented into a commercially available FPGA. In order to keep the space requirement low a relatively small FPGA (50 000 SystemGates) is used. Fig. 6 shows the physical space requirement of the

Fig. 6. Physical space requirement of the circuit on the FPGA; covered space marked by the dots.

transmitted video data before spreading received video data after despreading

Fig. 8. Coded video data before spreading and after despreading.

circuit on the FPGA after the implementation. The space requirement corresponds to 63% of the FPGA capacity. In the actual demonstrator two transceiver modules are realized. In order to keep the space requirement and the weight small, patch-antennas of size 4 · 4 mm2 are used. The modules are small and hence they can be easily integrated into a car for demonstration of their function (Fig. 7). Since the digital circuit is realised in an FPGA and completely described in VHDL, it can be implemented also into other FPGA’s [15]. The signal processing is performed completely in a field programmable gate array which is base of a flexible design and also offers the possibility of flexible re-programming steered by the protocol layer. The capability of the wireless data-link has been tested in a video transmission. MPEG-2 coded video signals has been transferred at a data rate of 2.5 Mbit/s. In order to guarantee a reliable transmission, the error rate must be better than pe = 2 · 10−4 . These video data are transmitted and decoded correctly. Fig. 8. shows a comparison of the received and reconstructed data at the output of the data-link (see the below signal) and the coded data at the input of the data-link. As can be seen in Fig. 8, the entire time for the digital signal processing (transmitting and receiving path together), RF-modulation/demodulation and the transmission amounts to only 400 ns. That is very favourable for real time applications like video transmissions. To demonstrate the maximum data rate a 12 Mbit/s signal has been also transferred. All measurements were accomplished without jamming j(t). The concept shows that with relatively simple and cheap components a very small wireless DSSS demonstrator for the transmission of up to 12 Mbit/s can be developed and investigated.

Fig. 7. Demonstrator of the CDMA-DSSS-transceiver and possible positions for integration into a car.

166 S. Lindenmeier, A. Terzis: A DSSS-Based Wireless Short Range Data-Link

4. State of the art In the following we discuss different wireless communication systems for short range communication with respect to the demands described in the introduction. In the last years numerous wireless short range communication systems have been developed and standardized for different applications. Table 1 gives an overview of the different short range communication systems including the investigated data-link and its characteristics [4]. Bluetooth can manage a small number of low-cost point-to-point radio links between Bluetooth-enabled devices. It has the required ability to establish ad-hocnetworks and regulates the transmitting power by demand. It is operated in the license-free 2.4 GHz ISM frequency band, and applies Frequency Hopping Spread Spectrum (FHSS) with up to 1600 hops/sec for transmitting data at a rate of 1 Mbit/s over the air. Since the transmission and the transmitted power is burst oriented it can be located more easily. Although it has excellent network and system capabilities it achieves low data rates compared to the above described requirements. From today’s point of view a payload data rate of 12 Mbit/s can not be expected in the next years development. DECT (Digital Enhanced Cordless Telecommunications) is also a established system and doing well as a wireless telephony system. It achieves a data rate of 1.152 Mbit/s. The main benefit of DECT in comparison to the other standardized systems in Table 1 is the frequency band. It operates in its own dedicated frequency band which ranges from 1.88–1.9 GHz (in Europe) where there are applied only few services which could interfere the function as it is possible in the 2.4 GHz or 5 GHz ISM bands. A further difference is the transmission procedure. DECT makes use of a multi carrier transmission and works without a spread spectrum transmission. A data rate of 12 Mbit/s can not be expected in the next years development. This advantageous dedicated frequency band is relatively narrow and the transmission and the transmitted power is burst oriented. Therefore the system is easier locatable. The HomeRF system has good network characteristics and works in the 2.4 GHz frequency band. The data

rate is at present 1.6 Mbit/s and at the second generation (HomeRF 2.0) even 10 Mbit/s. This system uses a FHSS with 50 hops/sec. In the next years development the data rate is expected to be increased up to 20 Mbit/s. But this high-speed system is not available at present since it is under development. Since the transmission and the transmitted power of HomeRF is burst oriented it can be located more easily. Since a low transmitting power is required a DSSS system is to be preferred. The IEEE 802.11b is also an established standard with flexible network capabilities and doing well as a WLAN system. It achieves nearly the required data rate and uses DSSS for the transmission in the 2.4 GHz band. Several data bits determine the choice of the spreading code. That means that the pn-code transports also data information. That leads to a lower correlation gain for the DSSS. Therefore the system achieves the data rate of 11 Mbit/s only in relatively reliable radio channels. If the channel quality decreases it reduces the data rate up to 1 Mbit/s which is to low for the requirements of data-link although this system fulfills most of the requirements mentioned in the introduction. In the table one can see that some of the WLAN systems achieve the required data rate of 12 Mbit/s easily (IEEE 802.11a and HiperLan/2) [3],[12]. These OFDM based high-speed systems operate in the 5 GHz ISM band and reduce their data rates from 54 Mbit/s up to 6 Mbit/s if the channel quality decreases. In contrast to DSSS systems these systems transfer on several channels simultaneously. Therefore these systems are locatable more easily than DSSS systems. Although every of these powerful established systems fulfills some of the above described requirements e.g. adhoc-abilities or data rates, none satisfies all of these special demands. Table 1 shows that in the very common ISM frequency bands at 2.4 GHz and 5 GHz there are lots of services leading to possible interference’s. The system at 24.1 GHz generates less interference towards other distant systems because the path loss is relatively high at this special frequency and there are less services expected from today’s point of view. The system must be also flexible in changing the data rate and the code-length by demand and under consideration of the higher bandwidth at 24.1 GHz to achieve the best possible correlation gain. The higher

Table 1. Overview of the different wireless short range communication systems System

Application

Frequency band

Transmission

Max. Data rate

Typ. Range

Bluetooth DECT HomeRF (HomeRF 2.0) IEEE 802.11 FH IEEE 802.11 DS IEEE 802.11b IEEE 802.11a HiperLan/2 Data-Link

PAN Data and voice Home-Networks WLAN WLAN WLAN WLAN WLAN PAN

2.4 GHz 1.88–1.9 GHz 2.4 GHz 2.4 GHz 2.4 GHz 2.4 GHz 5 GHz 5 GHz 24 GHz

FHSS MC FHSS FHSS DSSS DSSS OFDM OFDM DSSS

1 Mbit/s 1.152 Mbit/s 1.6 Mbit/s (10 Mbit/s) 1–2 Mbit/s 1–2 Mbit/s 1–11 Mbit/s 6–54 Mbit/s 6–54 Mbit/s 12 Mbit/s

10/100 m 300 m 30 m 100 m 100 m 30 m 100 m 100 m 10 m

S. Lindenmeier, A. Terzis: A DSSS-Based Wireless Short Range Data-Link 167

carrier frequency also offers the use of digital beamforming with smart antennas of acceptable size. The wireless data-link at 24.1 GHz yields a flexible platform for data transmission fulfilling all of the above described requirements e.g. a flexible data rate, a flexible code-length, low emission power and low locateability.

5. Conclusions The system concept of a wireless DSSS data-link has been investigated enabling the transmission of variable data rates up to 12 Mbit/s with high reliability. In comparison to already available higher speed ad-hoc networks which use e.g. 2.4 GHz carrier frequency, this concept is based on a 24.1 GHz carrier frequency which allows a higher bandwidth of 250 MHz for the SS-signal. The digital raw data is spread by an advantageous 8-chip code. Optionally 12-chip-codes can be used for higher correlation gain and for higher channel separation. The wireless DSSS datalink has been realized and tested in a video transmission path after performing a digital data compression. The data compression required a bit error rate of less than 2 · 10−4 which could be fulfilled easily by the system. Acknowledgement. The authors would like to acknowledge the support of H. Ni, S. Mayer and J.F. Luy.

References [1] Nusser, R.; Pelz, R. M.: Bluetooth Based Wireless Connectivity in an Automotive Environment. IEEE VTS Fall VTC2000, Boston, 4 (2000), 1935–1942. [2] Sikora, A.: Wireless LAN Protokolle und Anwendungen. Addison-Wesley, 2001. [3] IEEE 802.11a Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications – Highspeed Physical Layer in the 5 GHz Band + Extension in the 2.4 GHz Band. IEEE, 1999. [4] Merkle, A.; Terzis, A.: Digitale Funkkommunikation mit Bluetooth. Franzis Verlag, 2002. [5] Lindenmeier, S.: High speed wireless data links for mobile applications. European Conference on Wireless Technology, Milan Sept. 2002, 19–22. [6] Lindenmeier, S.; Mayer, S.; Knöpfle, D.; Luy, J.-F.: Communicating Near Range Sensor System for Automotive Application. MTT-S Workshop Digest, Seattle, 2.–7.6.2002. [7] Lee, S. L.; Miller, L. E.: CDMA Systems Engineering Handbook. Artech House, 1998. [8] Goiser, A. M. J.: Handbuch der Spread-Spectrum Technik. Springer Verlag Wien, 1997. [9] Viterbi, A. J.: CDMA Principles of Spread Spectrum Communication. Addison Wesley, 1995.

[10] Polydoros, A.; Weber, C.: A unified Approach to Serial Search Spread-Spectrum Code Acquisitation. IEEE Trans. on Communications, COM-32(5) (1984). [11] Finger, A.: Pseudorandom Signalverarbeitung. B. G. Teubner Stuttgart, 1997. [12] IEEE Std 802.11b-1999 Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications: Higher-Speed Physical Layer Extension in the 2.4 GHz Band. IEEE, 1999. [13] Proakis, J. G.: Digital Communication. 4th edition McGrawHill, 2001. [14] Glisic, S. G.: Automatic Decision Threshold Level Control in Direct-Sequence Spread-Spectrum Systems. IEEE Trans. on Communications 39(2) (1991). [15] Asheden, P. J.: The Designer’s Guide to VHDL. Morgan Kaufmann Publishers, 1996.

Stefan Lindenmeier was born in Munich, Germany, in 1967. He received the Dipl. Ing. degree in 1994, the Dr.-Ing. degree in 1996 and the Dr.-Ing. habil degree in 2000 in electrical engineering at the Technical University of Munich, Germany. From 1994 to 1996 he has been with the Ferdinand Braun Institut in Berlin, Germany, where he was working on numerical techniques for the analysis of planar microwave circuits. In 1996 he joined the department of high frequency techniques at the Technical University of Munich, Germany as an assistant professor where he worked on antenna design, EMC, and radar techniques. In 1997 he was recipient of the Dr. Georg Spinner high frequency award. Since July 2000 he is with the DaimlerChrysler Research and Technology Center in Ulm, Germany, where he is director of a research group for microwave communication and near range sensors. His current research interests are the development of new mobile communication systems, signal processing, antenna design and near range radar sensors for automotive applications. Stefan Lindenmeier is member of the ITG FA. 9.1. He is author of more than 60 scientific publications in the field of high frequency and communication techniques.

Anestis Terzis was born in Heidenheim, Germany, on June 17, 1978. He received the Dipl.-Ing. (FH) degree in electrical engineering on February 2002 from the University of Applied Sciences Ulm, Germany. Afterwards he wrote a book concerning the communication system Bluetooth. In October 2002 he joined the department for Microwave Technology at the DaimlerChrysler Research Center in Ulm, Germany. His research interests include wireless short range communication systems, simulation and digital signal processing with VHDL. Anestis Terzis is member of VDE and VDI.