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A flash-based SOC technology using a split-gate cell
Microelectronic Engineering 59 (2001) 203–211 www.elsevier.com / locate / mee
A flash-based SOC technology using a split-gate cell Di-Son Kuo*, Chung Wang, Sam Chu, M.S. Liang, C.S. Tsai, H.J. Tao, Y.C. Huang, J.P. Wu, Y.T. Chen, Y.D. Chih, C.H. Hsieh, H.C. Sung, J.K. Yeh, C.J. Lin, S.C. Wong, S.H. Lin, C.T. Hsieh, W.T. Chu, H.P. Chen, C.Y. Hsu, D.S. Shyu, S.P. Peng, T.J. Fong, K.Y. Lee Taiwan Semiconductor Manufacturing Corporation, Hsinchu, Taiwan, ROC
1. Introduction The continuing advances of IC technology has reached a stage that allows room for a broad diversity of components, each in a significantly large number, to be integrated on the same chip. Such a high integration level opens the door to the realization of ‘system on a chip’ (SOC), a concept that had been a dream of the IC industry for many years. To provide the industry with the application opportunities offered by this technology advance, we have developed three generations (0.5 mm, 0.35 mm, and 0.25 mm) of flash-based SOC technology as part of our foundry service. The 0.18 mm generation is currently under development. In this paper, we present a discussion on the key components of an SOC technology, using our own experience as an example.
2. Process architecture This paragraph explains the principle in constructing the process architecture for SOC technologies. There are three key considerations in the principle. Table 1 is a snap shot of the technology profile for the most recent three generations. All three generations were built upon the foundation of highperformance logic process baselines. In addition, from the entry of gate oxide thickness, it can be seen that a wide variety of MOSFET, including low-voltage core devices, medium-voltage I / O devices, and high voltage devices, are included. The purpose of providing a diversity of devices is to allow the technology users a maximal degree of flexibility in integrating various types of functional blocks on the same chip, and / or mix-and-matching different types of device in each block. Table 2 lists the key device parameters in each generation. Both the design rule and key electrical performance of the low voltage device for the core logic are fully compatible to the high-performance baseline logic process. * Corresponding author. E-mail address: [email protected] (D.-S. Kuo). 0167-9317 / 01 / $ – see front matter PII: S0167-9317( 01 )00623-2
2001 Published by Elsevier Science B.V.
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Table 1 Basic technology profile of flash-based SOC processes
Technology Flash cell size Cell type SRAM cell size Cell type Gate oxide Isolation Gate / source / drain Precision capacitor for mixed-signal
0.35 mm
0.25 mm
0.18 mm
2P4M 1.89 mm 2 Split-gate 15.24 mm 2 6T 70 / 220 LOCOS Silicide PIP
2P5M 1.06 mm 2 Split-gate 7.56 mm 2 6T 47 / 70 / 200 STI Salicide MIM
3P6M 0.38 mm 2 Split-gate 4.65 mm 2 6T 32 / 70 / 170 STI Salicide MIM
The purpose of such an arrangement has a dual purpose. First of all, it ensures that the technology users can enjoy the maximal speed and density offered by the high-performance baseline logic process. Furthermore, it makes things easy for the users to extend into SOC applications their previously proven products or design blocks originally intended only for pure logic applications. The third key consideration in setting up the process architecture is to allow easy integration of high-performance logic blocks (e.g. DSP core), high density SRAM blocks, and high density flash blocks onto the same chip. The process architecture is also to allow easy addition of optional process modules, such as precision capacitor and thick-metal inductor, which are essential for mixed-signal circuit blocks and RF circuit blocks. The trend of including mixed-signal blocks and RF blocks in SOC products has become more and more prevalent in recent years. Section 4 will discuss the capacitor and the inductor in more detail. Fig. 1 is a summary cross section view of our 0.25 mm generation technology. It illustrates the wide diversity of device types and the optional availability of mixed-signal and RF component.
Table 2 Key device electrical performance
Vcc Low voltage NMOS Vt Low voltage NMOS Idsat Low voltage PMOS Vt Low voltage PMOS Idsat High voltage NMOS BV High voltage PMOS BV Cell programming time Cell erase time Cell current
0.35 mm
0.25 mm
0.18 mm
3.3 0.58 550 2 0.75 250 . 12 . 12 10 ms 10 ms . 50
2.5 / 3.3 0.55 610 2 0.55 270 . 12 . 12 10 ms 10 ms . 40
1.8 / 3.3 0.42 600 2 0.5 265 . 12 . 12 10 ms 10 ms . 20
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Fig. 1. Cross section view of TSMC 0.25 mm flash process.
3. The flash cell and the SRAM cell In recent years, flash memory has proven to be a highly valuable component of SOC products. Flash memory has been equally successful in both stand-alone applications and SOC applications. In all generations of our SOC technology, a split-gate flash cell pioneered by SST Inc. [1] has been used. The cross section view, operational principle, and operation biases of the cell are shown in Fig. 2. The programming is done through source-side hot-electron injection. The injection efficiency is two orders of magnitude higher than the more conventional drain-side injection. As a result, very low programming current ( , 5 mA per cell) is needed. In contrast, drain-side injection employed by several major flash manufacturers normally requires several hundred microamperes of programming current. The low programming current is highly favorable for SOC applications, since many of them are targeted for portable use and therefore require low power consumption. The erase is achieved through poly-to-poly tunneling under the aid of asperity. The channel region is not actively involved
Fig. 2. Flash cell operation and bias condition.
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Fig. 3. Cross-section SEM of 0.25 mm flash cell.
in erase operation. Such a wide physical separation between programming region and erase region reduces the challenge in scaling down the cell size in the channel direction. Fig. 3 is a cross section SEM photo of the flash cell. It is in effect a 1.5-transistor cell, which offers the advantage of low design complexity and low area overhead for flash control circuit. This advantage is particularly attractive for SOC applications because it leads to small flash block size, easy interface between flash block and the rest of the chip, and low power consumption in the control circuit. Similar to other types of flash cell, continuing scaling down the cell size is a challenge. To circumvent the challenge, advanced etching modules were developed to realize a highly compact cell structure. As a result, a highly competitive cell size of 0.38 mm 2 is achieved with 0.18 mm lithography, which is only about 1 / 3 of the cell size for 0.25 mm generation. The programming and erase characteristics of such a compact flash cell are shown in Figs. 4 and 5, respectively. It can be seen that high-speed programming and erase can be accomplished with such a compact cell. The disturb characteristics are shown in Figs. 6 and 7. 6T SRAM cells have been built on the standard logic process of recent generations. It is also included in all three generations of our SOC technology. There are technical challenges in offering both SRAM and flash on the same chip. Frequently, SRAM and flash occupy different sweet spots in the process space. Obtaining a common process window for both SRAM and flash requires careful characterization and analysis. On the other hand, synergy between these two types of memory can occasionally be found. For instance, certain process features used to reduce the cell size in one type of memory can also be leveraged in the other type of memory.
4. Mixed-signal and RF components The availability of mixed-signal and RF components is important for many SOC applications. The feasibility to put logic control blocks, signal processing blocks, base-band blocks and RF blocks,
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Fig. 4. 0.18 mm cell programming characteristics.
Fig. 5. 0.18 mm cell erase characteristics.
SRAM blocks, and flash memory blocks on the same chip can revolutionize the system design and open the door to many new applications. Bluetooth is one such example. The most important on-chip mixed-signal and RF components include precision capacitor, high-value resistor, and inductor. In our SOC technology, precision capacitor is implemented in the form of metal-to-metal (MIM) capacitor. The high-value resistor is implemented using lightly doped poly strips. Inductor is implemented using thick metal layers. Table 3 lists key attributes of MIM capacitor and inductor for 0.18 mm generation. As mentioned before, all these mixed-signal and RF components are modularized in the process architecture, so that they can be optionally added onto the standard baseline process according to the needs of each individual product. For RF applications, a high degree of signal isolation among neighboring nodes is important. To achieve good isolation, a deep N-well has been added into the process as an optional feature. Fig. 8
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Fig. 6. 0.18 mm cell word-line disturb characteristics.
Fig. 7. 0.18 mm cell bit-line disturb characteristics.
Table 3 0.18 mm mix-signal and RF components Capacitor type
Film thickness
Capacitance (fF / mm 2 )
VCC1 (ppm / V)
TCC (ppm / C)
Mismatch (%)
BV (V)
MiM
˚ 380 A
2 1.0
, 60
, 60
, 0.2
. 13
Inductor
Thickness (mm)
Rs (mohm / sq)
Space (mm)
L (nH)
Q @ 1 GHz
L(M6)
2.0
15
1.5
10
7
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Fig. 8. Isolation improvement by using a deep N-well.
shows the improvement of OD to OD isolation with the use of a deep N-well. It can be seen that the use of a deep N-well improves the isolation by about 20 dB. Care must be taken in adding such a deep N-well because the large thermal cycle required can potentially alter the characteristics of advanced low-voltage core logic MOSFETs and flash cell.
5. Design library Due to the diversity of SOC component and functional block, a new technology provider–user relationship has emerged in SOC applications. It has often become difficult for any given SOC technology user to master all types of device components and functional blocks available in the SOC technology. SOC technology user’s partial reliance on the design library established and siliconproven by the technology provider has become an inevitable trend. To this end, we have developed a comprehensive set of design libraries for the SOC technology. This includes a wide variety of silicon proven flash memory IP blocks, SRAM IP blocks, core logic cell library, and mixed-signal cell library. Table 4 summarizes the flash memory IP blocks with various array size and configuration for three different generations of technology. There are a large number of selections in each generation. Table 5 lists key product performance of a typical 0.25 mm 4M-bit flash IP block. Several highly competitive features are worthwhile noting. These include fast data access time of 50 ns, fast byte programming of 20 ms, ultra fast erase time of 20 ms, versatile small erase sector size of 2 kbytes, and low standby current of 10 mA. In addition to the standard library, needs often arose for special purpose designs such as ultra low power or ultra high speed. Similar to flash library, the SRAM library also includes IP blocks with different array configurations for each generation of technology. Examples include a 0.25 mm 32K 3 32 single port synchronous SRAM block with 3.9 ns data access time. Mixed-signal library includes A / D converter, D/A converter, and PLL suitable for graphic, video, and communication applications. Examples include an 8-bit D/A converter operating at 250 MHz on 0.25 mm technology.
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Table 4 Flash IP library No. of different flash IP sizes and configurations
Examples of IP configurations
Nominal Vcc
0.25 mm
24
16K38, 32K38, 128K38, 256K38, 32K 16K316, 32K316, 128K316, 256K316, etc.
2.5 V
0.35 mm
16
32K38, 64K38, 128K38, 256K38, 4K316, 8K316, 16K316, 32K316, etc.
3.3 V
0.5 mm
13
4K38, 8K38, 12K38, 32K38, 16K316, 24K316, 32K316, 64K316, etc.
5V
6. Technical support for SOC technology It is important to point out that to make an SOC technology successful, the fabrication process, component set, and design library are not enough by themselves. They need to be bolstered by a comprehensive set of technical support in order to maximize their value. The support needs to encompass the whole spectrum of IC fabrication activities, ranging from the up-front customized product design support, process tailoring for each individual product to achieve low-cost and efficient wafer fabrication, all the way to special testing and packaging services needed by and customized for each individual product. Efficient testing for SOC products, which often include a wide variety of highly diverse functional blocks, is a major challenge. Including in library design a comprehensive set
Table 5 Flash IP product characteristics Technology Configuration Cell size (mm 2 ) Block size (mm 2 ) Sector size (Bytes) Supply voltage (V) Access time (ns) Write time / word (ms) Erase time / sector (ms) Mass erase time (ms) Read current (mA) Standby current (mA)
0.5 mm 32K38 3.12 2.2 128 5 (3.3 functional) ,30 30 4 4 ,20 ,10
0.35 mm 256K38 1.89 5.32 2K 3.3 (2.5 functional) ,50 20 10 20 ,10 ,10
0.25 mm 512K38 1.06 5.57 2K 2.5 (1.8 functional) ,50 20 20 20 ,7 .10
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of versatile and built-in testing capability for the embedded memory blocks can greatly alleviate the challenge. 7. Summary This paper examines in detail the key aspects of SOC technology, using as an example the three generations of flash-based SOC technology we have developed. The essential components of SOC technology were discussed. The success factors for a successful SOC technology in each technology component were highlighted. References [1] SST Patent, US 5,067,108, Single transistor non-volatile electrically alterable semiconductor memory device with a re-crystallized floating gate.
A flash-based SOC technology using a split-gate cell Di-Son Kuo*, Chung Wang, Sam Chu, M.S. Liang, C.S. Tsai, H.J. Tao, Y.C. Huang, J.P. Wu, Y.T. Chen, Y.D. Chih, C.H. Hsieh, H.C. Sung, J.K. Yeh, C.J. Lin, S.C. Wong, S.H. Lin, C.T. Hsieh, W.T. Chu, H.P. Chen, C.Y. Hsu, D.S. Shyu, S.P. Peng, T.J. Fong, K.Y. Lee Taiwan Semiconductor Manufacturing Corporation, Hsinchu, Taiwan, ROC
1. Introduction The continuing advances of IC technology has reached a stage that allows room for a broad diversity of components, each in a significantly large number, to be integrated on the same chip. Such a high integration level opens the door to the realization of ‘system on a chip’ (SOC), a concept that had been a dream of the IC industry for many years. To provide the industry with the application opportunities offered by this technology advance, we have developed three generations (0.5 mm, 0.35 mm, and 0.25 mm) of flash-based SOC technology as part of our foundry service. The 0.18 mm generation is currently under development. In this paper, we present a discussion on the key components of an SOC technology, using our own experience as an example.
2. Process architecture This paragraph explains the principle in constructing the process architecture for SOC technologies. There are three key considerations in the principle. Table 1 is a snap shot of the technology profile for the most recent three generations. All three generations were built upon the foundation of highperformance logic process baselines. In addition, from the entry of gate oxide thickness, it can be seen that a wide variety of MOSFET, including low-voltage core devices, medium-voltage I / O devices, and high voltage devices, are included. The purpose of providing a diversity of devices is to allow the technology users a maximal degree of flexibility in integrating various types of functional blocks on the same chip, and / or mix-and-matching different types of device in each block. Table 2 lists the key device parameters in each generation. Both the design rule and key electrical performance of the low voltage device for the core logic are fully compatible to the high-performance baseline logic process. * Corresponding author. E-mail address: [email protected] (D.-S. Kuo). 0167-9317 / 01 / $ – see front matter PII: S0167-9317( 01 )00623-2
2001 Published by Elsevier Science B.V.
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Table 1 Basic technology profile of flash-based SOC processes
Technology Flash cell size Cell type SRAM cell size Cell type Gate oxide Isolation Gate / source / drain Precision capacitor for mixed-signal
0.35 mm
0.25 mm
0.18 mm
2P4M 1.89 mm 2 Split-gate 15.24 mm 2 6T 70 / 220 LOCOS Silicide PIP
2P5M 1.06 mm 2 Split-gate 7.56 mm 2 6T 47 / 70 / 200 STI Salicide MIM
3P6M 0.38 mm 2 Split-gate 4.65 mm 2 6T 32 / 70 / 170 STI Salicide MIM
The purpose of such an arrangement has a dual purpose. First of all, it ensures that the technology users can enjoy the maximal speed and density offered by the high-performance baseline logic process. Furthermore, it makes things easy for the users to extend into SOC applications their previously proven products or design blocks originally intended only for pure logic applications. The third key consideration in setting up the process architecture is to allow easy integration of high-performance logic blocks (e.g. DSP core), high density SRAM blocks, and high density flash blocks onto the same chip. The process architecture is also to allow easy addition of optional process modules, such as precision capacitor and thick-metal inductor, which are essential for mixed-signal circuit blocks and RF circuit blocks. The trend of including mixed-signal blocks and RF blocks in SOC products has become more and more prevalent in recent years. Section 4 will discuss the capacitor and the inductor in more detail. Fig. 1 is a summary cross section view of our 0.25 mm generation technology. It illustrates the wide diversity of device types and the optional availability of mixed-signal and RF component.
Table 2 Key device electrical performance
Vcc Low voltage NMOS Vt Low voltage NMOS Idsat Low voltage PMOS Vt Low voltage PMOS Idsat High voltage NMOS BV High voltage PMOS BV Cell programming time Cell erase time Cell current
0.35 mm
0.25 mm
0.18 mm
3.3 0.58 550 2 0.75 250 . 12 . 12 10 ms 10 ms . 50
2.5 / 3.3 0.55 610 2 0.55 270 . 12 . 12 10 ms 10 ms . 40
1.8 / 3.3 0.42 600 2 0.5 265 . 12 . 12 10 ms 10 ms . 20
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Fig. 1. Cross section view of TSMC 0.25 mm flash process.
3. The flash cell and the SRAM cell In recent years, flash memory has proven to be a highly valuable component of SOC products. Flash memory has been equally successful in both stand-alone applications and SOC applications. In all generations of our SOC technology, a split-gate flash cell pioneered by SST Inc. [1] has been used. The cross section view, operational principle, and operation biases of the cell are shown in Fig. 2. The programming is done through source-side hot-electron injection. The injection efficiency is two orders of magnitude higher than the more conventional drain-side injection. As a result, very low programming current ( , 5 mA per cell) is needed. In contrast, drain-side injection employed by several major flash manufacturers normally requires several hundred microamperes of programming current. The low programming current is highly favorable for SOC applications, since many of them are targeted for portable use and therefore require low power consumption. The erase is achieved through poly-to-poly tunneling under the aid of asperity. The channel region is not actively involved
Fig. 2. Flash cell operation and bias condition.
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Fig. 3. Cross-section SEM of 0.25 mm flash cell.
in erase operation. Such a wide physical separation between programming region and erase region reduces the challenge in scaling down the cell size in the channel direction. Fig. 3 is a cross section SEM photo of the flash cell. It is in effect a 1.5-transistor cell, which offers the advantage of low design complexity and low area overhead for flash control circuit. This advantage is particularly attractive for SOC applications because it leads to small flash block size, easy interface between flash block and the rest of the chip, and low power consumption in the control circuit. Similar to other types of flash cell, continuing scaling down the cell size is a challenge. To circumvent the challenge, advanced etching modules were developed to realize a highly compact cell structure. As a result, a highly competitive cell size of 0.38 mm 2 is achieved with 0.18 mm lithography, which is only about 1 / 3 of the cell size for 0.25 mm generation. The programming and erase characteristics of such a compact flash cell are shown in Figs. 4 and 5, respectively. It can be seen that high-speed programming and erase can be accomplished with such a compact cell. The disturb characteristics are shown in Figs. 6 and 7. 6T SRAM cells have been built on the standard logic process of recent generations. It is also included in all three generations of our SOC technology. There are technical challenges in offering both SRAM and flash on the same chip. Frequently, SRAM and flash occupy different sweet spots in the process space. Obtaining a common process window for both SRAM and flash requires careful characterization and analysis. On the other hand, synergy between these two types of memory can occasionally be found. For instance, certain process features used to reduce the cell size in one type of memory can also be leveraged in the other type of memory.
4. Mixed-signal and RF components The availability of mixed-signal and RF components is important for many SOC applications. The feasibility to put logic control blocks, signal processing blocks, base-band blocks and RF blocks,
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Fig. 4. 0.18 mm cell programming characteristics.
Fig. 5. 0.18 mm cell erase characteristics.
SRAM blocks, and flash memory blocks on the same chip can revolutionize the system design and open the door to many new applications. Bluetooth is one such example. The most important on-chip mixed-signal and RF components include precision capacitor, high-value resistor, and inductor. In our SOC technology, precision capacitor is implemented in the form of metal-to-metal (MIM) capacitor. The high-value resistor is implemented using lightly doped poly strips. Inductor is implemented using thick metal layers. Table 3 lists key attributes of MIM capacitor and inductor for 0.18 mm generation. As mentioned before, all these mixed-signal and RF components are modularized in the process architecture, so that they can be optionally added onto the standard baseline process according to the needs of each individual product. For RF applications, a high degree of signal isolation among neighboring nodes is important. To achieve good isolation, a deep N-well has been added into the process as an optional feature. Fig. 8
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Fig. 6. 0.18 mm cell word-line disturb characteristics.
Fig. 7. 0.18 mm cell bit-line disturb characteristics.
Table 3 0.18 mm mix-signal and RF components Capacitor type
Film thickness
Capacitance (fF / mm 2 )
VCC1 (ppm / V)
TCC (ppm / C)
Mismatch (%)
BV (V)
MiM
˚ 380 A
2 1.0
, 60
, 60
, 0.2
. 13
Inductor
Thickness (mm)
Rs (mohm / sq)
Space (mm)
L (nH)
Q @ 1 GHz
L(M6)
2.0
15
1.5
10
7
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Fig. 8. Isolation improvement by using a deep N-well.
shows the improvement of OD to OD isolation with the use of a deep N-well. It can be seen that the use of a deep N-well improves the isolation by about 20 dB. Care must be taken in adding such a deep N-well because the large thermal cycle required can potentially alter the characteristics of advanced low-voltage core logic MOSFETs and flash cell.
5. Design library Due to the diversity of SOC component and functional block, a new technology provider–user relationship has emerged in SOC applications. It has often become difficult for any given SOC technology user to master all types of device components and functional blocks available in the SOC technology. SOC technology user’s partial reliance on the design library established and siliconproven by the technology provider has become an inevitable trend. To this end, we have developed a comprehensive set of design libraries for the SOC technology. This includes a wide variety of silicon proven flash memory IP blocks, SRAM IP blocks, core logic cell library, and mixed-signal cell library. Table 4 summarizes the flash memory IP blocks with various array size and configuration for three different generations of technology. There are a large number of selections in each generation. Table 5 lists key product performance of a typical 0.25 mm 4M-bit flash IP block. Several highly competitive features are worthwhile noting. These include fast data access time of 50 ns, fast byte programming of 20 ms, ultra fast erase time of 20 ms, versatile small erase sector size of 2 kbytes, and low standby current of 10 mA. In addition to the standard library, needs often arose for special purpose designs such as ultra low power or ultra high speed. Similar to flash library, the SRAM library also includes IP blocks with different array configurations for each generation of technology. Examples include a 0.25 mm 32K 3 32 single port synchronous SRAM block with 3.9 ns data access time. Mixed-signal library includes A / D converter, D/A converter, and PLL suitable for graphic, video, and communication applications. Examples include an 8-bit D/A converter operating at 250 MHz on 0.25 mm technology.
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Table 4 Flash IP library No. of different flash IP sizes and configurations
Examples of IP configurations
Nominal Vcc
0.25 mm
24
16K38, 32K38, 128K38, 256K38, 32K 16K316, 32K316, 128K316, 256K316, etc.
2.5 V
0.35 mm
16
32K38, 64K38, 128K38, 256K38, 4K316, 8K316, 16K316, 32K316, etc.
3.3 V
0.5 mm
13
4K38, 8K38, 12K38, 32K38, 16K316, 24K316, 32K316, 64K316, etc.
5V
6. Technical support for SOC technology It is important to point out that to make an SOC technology successful, the fabrication process, component set, and design library are not enough by themselves. They need to be bolstered by a comprehensive set of technical support in order to maximize their value. The support needs to encompass the whole spectrum of IC fabrication activities, ranging from the up-front customized product design support, process tailoring for each individual product to achieve low-cost and efficient wafer fabrication, all the way to special testing and packaging services needed by and customized for each individual product. Efficient testing for SOC products, which often include a wide variety of highly diverse functional blocks, is a major challenge. Including in library design a comprehensive set
Table 5 Flash IP product characteristics Technology Configuration Cell size (mm 2 ) Block size (mm 2 ) Sector size (Bytes) Supply voltage (V) Access time (ns) Write time / word (ms) Erase time / sector (ms) Mass erase time (ms) Read current (mA) Standby current (mA)
0.5 mm 32K38 3.12 2.2 128 5 (3.3 functional) ,30 30 4 4 ,20 ,10
0.35 mm 256K38 1.89 5.32 2K 3.3 (2.5 functional) ,50 20 10 20 ,10 ,10
0.25 mm 512K38 1.06 5.57 2K 2.5 (1.8 functional) ,50 20 20 20 ,7 .10
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of versatile and built-in testing capability for the embedded memory blocks can greatly alleviate the challenge. 7. Summary This paper examines in detail the key aspects of SOC technology, using as an example the three generations of flash-based SOC technology we have developed. The essential components of SOC technology were discussed. The success factors for a successful SOC technology in each technology component were highlighted. References [1] SST Patent, US 5,067,108, Single transistor non-volatile electrically alterable semiconductor memory device with a re-crystallized floating gate.