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A flexible grid interface for a PV power system
Solar Energy 144 (2017) 540–547
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A flexible grid interface for a PV power system Jinn-Chang Wu a,⇑, Hurng-Liahng Jou b, Jie-Hao Tsai a a b
Department of Microelectronics Engineering, National Kaohsiung Marine University, Kaohsiung 811, Taiwan, ROC Department of Electrical Engineering, National Kaohsiung University of Applied Sciences, Kaohsiung 807, Taiwan, ROC
a r t i c l e
i n f o
Article history: Received 3 October 2016 Received in revised form 13 January 2017 Accepted 26 January 2017 Available online 7 February 2017 Keywords: PV power system Multi-level inverter DC-DC converter
a b s t r a c t A PV power system with a flexible grid interface is studied in this paper. The flexible grid interface comprises two power conversion stages, a two-mode buck-boost converter (TMBBC) and a variable-level inverter (VLI). The operation of VLI is flexible according to the output DC voltage of the PV array, and it generates an AC voltage with three levels, five levels or seven levels and outputs a sinusoidal current to the grid. Partial power from the PV array is directly converted to AC power via only one power conversion such that the power efficiency for the PV power system is improved. Besides, the operating voltage range for the PV array can be extended because of the high boost gain of TMMBC. A hardware prototype is implemented to demonstrate the performance of the proposed flexible grid interface. Ó 2017 Elsevier Ltd. All rights reserved.
1. Introduction The major energy source for electrical power generation has been fossil fuels. However, the use of fossil fuels results in extreme climate change and air pollution. The development of renewable power systems has become important (Nayar et al., 2011). PV energy is inexhaustible. PV cells convert photovoltaic energy to DC electrical energy. Several PV cells are integrated into a PV module, and PV array is composed of several PV modules. The output electrical energy of a PV array is dependent on the irradiance and temperature (Das et al., 2015; Upadhyay et al., 2017; Gupta et al., 2016). Technological progress and mass production mean that the cost of PV modules is continuously dropping and the requirement for PV generation is still growing. The growth of PV generation is expected to alleviate the problems of global warming. Different operating voltage for the PV array generates different level of output power. A PV array has a unique maximum power point (MPP) for a specific irradiance and temperature (Upadhyay et al., 2017; Gupta et al., 2016). A power conversion interface is needed between the PV array and the load or the grid to extract the power of PV array and convert it to AC power and to perform the maximum power tracking (Upadhyay et al., 2017; Gupta et al., 2016; Chen et al., 2013). In general, small-scale PV power systems consist of fewer PV modules and the grid interface requires two power conversion stages: a DC-DC converter and a DC-AC inverter, connected in cascaded (Spertino and Graditi, 2014; Shen et al., 2012; Ahmad et al., ⇑ Corresponding author. E-mail address: [email protected] (J.-C. Wu). http://dx.doi.org/10.1016/j.solener.2017.01.062 0038-092X/Ó 2017 Elsevier Ltd. All rights reserved.
2013; Lauria and Coppola, 2014; Boukezata et al., 2016). The DCDC converter boosts the output voltage of PV array to the dc bus voltage of the DC-AC inverter. Bridge-type inverters are a popular means for converting DC power to AC power. A half-bridge inverter comprises only two power semiconductor switches and generates a two-level AC voltage. Four power semiconductor switches are imposed in the full-bridge inverter to convert a dc voltage to a two-level or three-level AC voltage. Usually, all of the output power from the PV array that is supplied to the load or the grid must be processed by both the DC-DC converter and the DC-AC inverter. Advances in semiconductor technology mean that passive elements are being replaced by power semiconductor devices in power conversion circuit. Several new topologies have been developed. An interleaved topology integrates several power converters in parallel and interleaves the switching of these power converters to allow frequency multiplication so a passive filter for an interleaved topology is smaller (Patel and Panda, 2014; Tamyurek and Kirimer, 2015; Capella et al., 2015). A multi-level (ML) topology generates more levels of output voltage and reduces the dominant switching harmonic. The passive filter that is required is also smaller (Iero et al., 2014; Bharatiraja et al., 2010; Gayathri Devi et al., 2014; Trabelsi et al., 2013; Sanjeevan et al., 2016; Chinnaiyan et al., 2013; Valan Rajkumar and Manoharan, 2013; Kumar et al., 2016). Since power semiconductor switches are operated by hard switching, there is a switching power loss. The switching power loss for a power semiconductor switch is dependent on the switching in the voltage, the current and the speed and the frequency. The power efficiency for a ML topology is improved by reducing the
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switching in the voltage during the switching process. Therefore, a ML topology is gradually used for small-scale DC-AC inverters. A diode-clamped ML inverter (DCMLI) utilities several diodes to maintain the output voltage at one of voltage levels of the dc bus (Iero et al., 2014; Bharatiraja et al., 2010; Gayathri Devi et al., 2014). A flying-capacitor ML inverter (FCMLI) uses several capacitors in the current path to provide different levels of output voltage (Trabelsi et al., 2013; Sanjeevan et al., 2016). However, DCMLI and FCMLI require regulation of the voltages in the capacitors because an asymmetric voltage results in the dc components appearing in the output voltage and current. A cascade ML inverter (CMLI) comprises several HBCs that are connected in series to generate an output voltage that combines the output voltages of the HBCs (Chinnaiyan et al., 2013; Valan Rajkumar and Manoharan, 2013; Kumar et al., 2016). However, several voltage sources are required for the operation of a cascade multi-level inverter. The integration of a H-bridge converter (HBC) and a three-port power converter (TPPC) to produce a five-level inverter and a seven-level inverter has been proposed by the authors (Shen et al., 2013; Wu et al., 2014). These respectively use symmetric input voltages and the input voltages with multiple relationships. However, a DC-DC converter is required to generate these dc voltages and all of the output power must be processed by two power conversion stages: a DC-DC converter and a DC-AC inverter. In this paper, a HBC and a TPPC are integrated to produce a variable-level inverter (VLI). This VLI is applied in a PV power system. The VLI generates a voltage with three levels, five levels, seven symmetric levels or seven asymmetric levels. A two-mode buck-boost converter (TMBBC) is developed to extend the voltage range for the PV array and to improve the power efficiency. Consequently, the operation of proposed grid interface is flexible according to the voltage of PV array. To verify the performance of the proposed PV power system, a hardware prototype is developed and tested.
2. Power circuit topology Fig. 1 shows the power circuit topology for the proposed PV power system. The flexible grid interface comprises a TMBBC and a VLI. The VLI is composed of a HBC and a TPPC. The TPPC has two input ports and an output port. The first input port is directly connected to the PV array and its voltage is controlled to trace the MPP for the PV array. The input of the TMBBC is also provided from
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the PV array, and the output of this TMBBC provides a voltage to the second input port. These two input ports are directly connected in series. The TMBBC controls the voltage at the second input port and ensures that the sum of the voltages at the two input ports is greater than the amplitude of the grid voltage. The HBC is switched synchronously to the grid voltage to commutate the output voltage of the TPPC during the negative cycle of the grid voltage. Only the TPPC is operated in high-frequency switching. The TMBBC integrates two-mode inductors to allow a greater voltage gain, which extends the voltage range for the PV array and increases the power efficiency. Although the power circuit of VLI in the proposed grid interface is the same as that of inverter (Shen et al., 2013; Wu et al., 2014), the arrangement of VLI and TPPC for the proposed PV power system is novel. The DC-DC converter and VLI are connected in cascade and all of the output power must be processed by two power conversion stages in the previous PV power system (Shen et al., 2013; Wu et al., 2014). In addition, the relationship between the voltages of two input ports for the TPPC is fixed such that the amount of levels for the output voltage is fixed. For the proposed PV power system, shown in Fig. 1, the PV array directly supplies power to the first input port of TPPC such that partial power from the PV array can only be converted by only one power conversion stage. Besides, the amount of levels for the output voltage can be varied according to the output voltage of PV array.
3. Operation of VLI The VLI is composed of a HBC and a TPPC. The HBC is switched synchronously to the grid voltage, to generate an output voltage of alternate polarity, and the TPPC is switched in pulse-width modulation (PWM) to generate a dc pulse voltage that has variable levels and to control the output current of the VLI. Since the first input port of the TPPC is directly connected to the PV array, its voltage (VC2) is equal to the output voltage of PV array. The TMBBC generates the voltage (VC1) of the second input port for the TPPC such that the summation of the voltages at the two input ports is greater than the amplitude of the grid voltage. Fig. 2 shows the switching modes for the TPPC, and there are four modes (mode I, II, III and IV). The respective voltages at the output port for modes I, II, III and IV are VC1, VC2, VC1 + VC2 and 0. Consequently, the HBC outputs a voltage that has levels, VC1, VC2, (VC1 + VC2), 0, VC1, VC2 and VC1 + -
Fig. 1. Power circuit of the proposed PV power system.
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Fig. 2. Switching modes of the TPPC, for (a) mode I, (b) mode II, (c) mode III and (d) mode IV.
VC2. If VC1 is not equal to VC2, the output voltage from the VLI has seven levels. The VLI outputs a five-level voltage if VC1 is equal to VC2. If VC2 is greater than the setting voltage, which is greater than the amplitude of the grid voltage, VC1 is equal to zero and the VLI outputs a three-level voltage. The setting voltage is 180 V for a grid voltage of 110 V. The output power from a PV array varies depending on its output voltage, and there is a unique MPP for a specific environmental condition. To harvest PV power effectively, the output voltage of PV array must be regulated to trace the MPP, so VC2 varies within a wide range. According to the output voltage of PV array, the operation of the TPPC has four cases: VC1 < VC2, VC1 = VC2, VC1 > VC2 and VC2 > 180 V. The HBC is connected between the TPPC and the grid and is switched synchronously to the grid voltage to commutate the output voltage from the TPPC during the negative cycle of grid voltage. Therefore, in terms of the TPPC, the HBC is regarded as an absolute circuit, and the TPPC is regarded as a buck converter with a variable output voltage (absolute grid voltage). Therefore, the output voltage from the TPPC cannot be controlled. The control object for the TPPC is the output current. The four operating cases for the TPPC are as follows: 3.1. Case 1: VC1 < VC2 In this case, the output voltage of PV array is higher than half of the setting voltage. The operation of the TPPC is divided into three periods for this case because the magnitude of utility voltage is time-variant (sinusoidal) waveform. The power semiconductor switches, S1 and S2, in the TPPC must generate two voltage levels around the magnitude of grid voltage to increase and decrease the output current and follow the current reference during each period. When the magnitude of the grid voltage is smaller than VC1, the TPPC operates between switching modes I and IV, so S1 is operated in PWM and S2 is always turned off. Therefore, the TPPC generates two voltage levels: VC1 and 0. The TPPC is operated between switching modes I and II when the magnitude of grid voltage is between VC1 and VC2. Both S1 and S2 are switched in complementary PWM to generate VC2 or VC1. If the magnitude of the grid voltage is greater than VC2, the TPPC is operated between switching modes II and III, so S1 is operated in PWM and S2 is always turned on. The TPPC generates two voltage levels: (VC2 + VC1) and VC1. Therefore, the TPPC generates a voltage that has four levels, according to the magnitude of the grid voltage, and the VLI outputs a seven-level voltage.
ates a voltage that has four levels, according to the magnitude of the grid voltage, and the VLI also outputs a seven-level voltage. 3.3. Case 3: VC1 = VC2 The TPPC is operated in case 3 when the output voltage of PV array is just equal to half of the setting voltage. In this case, the operation of the TPPC is divided into two periods. When the magnitude of the grid voltage is less than VC2, S1 and S2 can have two switching operations. The first is the integration of switching modes I and IV and the other is the integration of switching modes II and IV. To achieve greater power efficiency, switching modes II and IV are preferred because the power is directly supplied from the PV array (not the TMBBC). Therefore, S2 is operated in PWM and S1 is always turned off. This generates two voltage levels, VC2 and 0, during this period. If the magnitude of grid voltage is greater than VC2, S1 and S2 are also switched in two different ways. The first is the integration of switching modes I and III and the second is the integration of switching modes II and III. Switching modes II and III are preferred because the PV array (not the TMBBC) still supplies power in these two switching modes such that the power efficiency is greater. Therefore, S1 is operated in PWM and S2 is always turned on. This generates two voltage levels, 2VC2 and VC2, during this period. Therefore, the TPPC generates a voltage that has three levels, according to the magnitude of the grid voltage, and the VLI outputs a five-level voltage. 3.4. Case 4: VC2 > 180 V In this case, the output voltage of PV array is greater than the setting voltage. The TMBBC is disabled and VC1 = 0 V. For this condition, S2 is operated in PWM and S1 is always turned off and the TPPC is operated between switching modes II and IV. The TPPC generates two voltage levels: VC2 and 0. Accordingly, the VLI outputs a three-level voltage. The operations of S1 and S2 are integrated in Table 1. PWM is used to control the TPPC where a modulation signal vm is comTable 1 Operation of S1 and S2.
VC1 > VC2
S1
S2
|vu| < VC2 VC1 > |vu| > VC2
Off PWM
PWM
|vu| > VC1
On
PWM PWM
3.2. Case 2: VC1 > VC2
VC1 = VC2
|vu| < VC2 |vu| > VC2
Off On
PWM PWM
In this case, the output voltage of PV array is less than half of the setting voltage. The operation of the TPPC for this condition is similar to that for the case 1. The difference is that the turned-on and turned-off operations for S1 and S2 are reversed. The TPPC gener-
VC1 < VC2
|vu| < VC1 VC2 > |vu| > VC1
PWM
Off PWM
|vu| > VC2 VC2 > 180 V
PWM PWM Off
On PWM
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pared with a triangle signal. The duty for the PWM control is represented as:
continuous-conduction mode (CCM), the transfer function for TMBBC is represented as (Hart, 2004):
dt ¼ vm =Vtri
VC1 Dd ¼ VC2 1 Dd
ð1Þ
where Vtri is the peak value of the triangle signal. The average output voltage for the TPPC is derived as:
vot ¼ dt DV þ Vx ¼ kTPPC vm þ Vx
ð2Þ
where DV is the difference between the two voltage levels and Vx is the lower voltage level during each operational period. The TPPC can be regarded as an amplifier with the gain KTPPC and is represented as:
kTPPC ¼ DV=Vtri
ð3Þ
The current-mode control in the TPPC controls the output current. Fig. 3 shows a simplified model of the TPPC, where kc and Gc are the transfer functions for the current detector and the current controller and L is the inductance of the filter inductor. In terms of the TPPC, the grid voltage and the output current for the VLI are represented by their absolute value in Fig. 3. The absolute output current (|IL|) is derived as:
jIL j ¼
kTPPC Gc =L 1=L jI j ðjVu j Vx Þ s þ kc kTPPC Gc =L L s þ kc kTPPC Gc =L
ð4Þ
where jIL j is the absolute current reference. Since the output current is expected to be sinusoidal, jIL j is an absolute sinusoidal signal. The second term in (4) is the disturbance of the current-mode control, and it can be attenuated by a feed-forward control, which is Gf, shown in Fig. 3. Since the feed-forward control provides the major part of the modulation signal, the current controller adopts a proportional control to fine-tune the modulation signal. 4. Operation of TMBBC Since the negative terminal of VC1 is joined to the positive terminal of VC2, a buck-boost converter is used to build VC1 from VC2. Ideally, the gain for the buck-boost converter is infinite when the duty ratio for the power semiconductor switch approaches unity. However, the gain for a buck-boost converter is limited because there are power losses in the inductor and power semiconductor devices. The greater duty ratio for the power semiconductor switch will conduct serious degradation in power efficiency. The TMBBC, which is shown in Fig. 1, is developed in the PV power system. As can be seen, a controllable inductor set replaces the inductor of the buck-boost power converter. The controllable inductor set is composed of a power semiconductor switch S8, three diodes, D4, D5 and D6, and two inductors. The operation of a TMBBC has two modes. When VC2 is greater than VC1, S8 is turned off and the two inductors are operated in parallel. The operation of TMBBC is similar to that for a conventional buck-boost power converter. In
Fig. 3. Simplified model of the TPPC.
ð5Þ
where Dd is the duty of S7. Since VC2 is greater than VC1, Dd is smaller than 0.5. When VC2 is smaller than VC1, S8 is still turned on. When S7 is turned on, D4 and D5 conduct and the path, S8 and D6, is disabled because D6 has a reverse bias. Consequently, the two inductors are charged in parallel. If the two inductors are identical, the current in each inductor is the same and can be represented as:
diLa VC2 ¼ dt La
ð6Þ
The change in the inductor current during the period when S7 is on is derived as:
ðDiLa Þon ¼
VC2 Dd T La
ð7Þ
When S7 is turned off, D4 and D5 are turned off and the path, S8 and D6, is enabled. Consequently, the two inductors are discharged in series through the path, S8 and D6. The current in the inductor is represented as:
diLa VC1 ¼ dt 2La
ð8Þ
The change in the inductor current during the period when S7 is off is derived as:
ðDiLa Þoff ¼
VC1 ð1 Dd ÞT 2La
ð9Þ
In the steady state, (DiLa)on is equal to (DiLa)off and the transfer function for the TMBBC is derived as
VC1 2Dd ¼ VC2 1 Dd
ð10Þ
The transfer function for the TMBBC is twice that of conventional buck-boost power converter, so the operating voltage for the PV array can be extended. 5. Disscussion A small-scale PV power system consists of fewer PV modules and the output voltage of PV array is low. Conventionally, two power conversion stages, a DC-DC converter and a DC-AC inverter, are used in the grid interface for a small-scale PV power system. The power from the PV array to the grid should be converted by two power conversion stages. The power efficiency (g) for a conventional grid interface can be represented as:
g ¼ gdc—dc gdc—ac
ð11Þ
where gdc–dc and gdc–ac are the power efficiencies for the DC-DC converter and DC-AC inverter, respectively. A ML topology can be used in the DC-AC inverter to reduce the switching loss and the dominant switching harmonic (Iero et al., 2014; Bharatiraja et al., 2010; Gayathri Devi et al., 2014; Trabelsi et al., 2013; Sanjeevan et al., 2016; Chinnaiyan et al., 2013; Valan Rajkumar and Manoharan, 2013; Kumar et al., 2016; Shen et al., 2013; Wu et al., 2014). The power efficiency gdc–ac is improved. However, the power from the PV array to the grid is still processed by two power conversion stages. In addition, the amount of levels for the output voltage of conventional ML inverter is fixed. In the proposed grid interface, operation of the VLI is flexible and the amount of levels for the output voltage may be three, five or seven according to the output voltage of PV array. In addition, partial power from the PV array is
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directly converted to AC power via only the VLI. The power efficiency for the proposed grid interface can be represented as:
g ¼ kgdc—ac þ ð1 kÞgdc—dc gdc—ac
ð12Þ
where k is the power ratio converted by only the VLI, and it is dependent on the output voltage of PV array. k is increased when the output voltage of PV array increases. As compared to (11), the power efficiency for the proposed grid interface is improved. 6. Control diagram The control objects for the VLI are the output current and the voltage of the PV array. An outer voltage control loop adjusts the voltage of the PV array to trace the MPP for the PV array and an inner control loop is applied to generate a high-quality AC current that is sinusoidal and in phase with the grid voltage. Fig. 4(a) shows the control diagram for the VLI. The perturbation and observation (P&O) method is employed for tracing MPP (Mellit et al., 2011). The voltage of the PV array is disturbed and the change in the output power is observed, to decide the next perturbation for the PV array. The output power for the PV power system replaces the output power for the PV array as the observed parameter for the proposed PV power system, which obviates the need for a current detector in the PV array. As seen in Fig. 4(a), the outer voltage control loop is employed to control the voltage, VC2, to follow the output from the maximum power point tracking (MPPT) controller. The output of PI controller is the calculated amplitude for the output current. The grid voltage is sent to a signal generator, to generate an absolute sinusoidal signal with unity amplitude. Both the outputs from the PI controller and the signal generator are sent to a multiplier, to calculate the
current reference. The inner current control loop is employed to control the absolute output current to follow the current reference. Finally, the modulation signal is obtained by summing the outputs from the current controller and the feed-forward. The PWM circuit compares the modulation signal with a triangle signal to produce the PWM signal. The control signals for S1 and S2, shown in Table 1, must take account of the magnitude of the grid voltage, VC1 and VC2. Therefore, the PWM signal, the magnitude of the grid voltage, VC1 and VC2 are sent to the switching signal generator to produce the switching signals for S1 and S2. The grid voltage is also sent to a comparator, to produce the switching signals for S3, S4, S5 and S6. Since the amplitude of the grid voltage is regarded as a constant value over a short period, the output power for the PV power system can be decided by the amplitude of its output current. In the steady state, the amplitude of the output current approaches the result of the PI controller. Therefore, the result of the PI controller can be used to observe the change in the output power for the PV power system in the MPPT control. Since the sum of VC1 and VC2 must be equal to the setting voltage, the control object for the TMBBC is VC1. Fig. 4(b) shows the control block for the TMBBC. The output from the MPPT controller is the voltage reference for VC2. This is subtracted from the setting voltage to obtain the voltage reference for VC1. The voltage reference for VC1 is compared to the detected value of VC1 and then delivered to a PI controller. To increase the stability of the TMBBC, the current control is integrated. The output from the PI controller is compared to the detected inductor current and then sent to the amplifier. The output from the amplifier is the modulation signal, and the PWM circuit compares the modulation signal with a triangle signal to produce the switching signal for S7. The output for the MPPT controller and half of the setting voltage are sent to the comparator to provide the switching signal for S8.
Fig. 4. Control block of the proposed PV power system, for (a) VLI and (b) TMBBC.
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7. Experimental results A prototype was established to evaluate the functions of the proposed PV power system. The controller, shown in Fig. 4, is implemented by a digital signal processor TMS320F28035. Fig. 5 shows the photograph for the prototype. The power rating of prototype is 700 W. MOSFETs are used for S1, S2 of TPPC and S7, S8 of TMBBC because of high-frequency switching. S3–S6 of HBC are switched synchronously to the grid voltage such that IGBTs are used. Considering low reverse-recovery loss, SiC diodes are used for D1, D2 of TPPC and D3 of TMPPC. The voltage of the singlephase grid was 110 V and 60 Hz. Table 2 summarizes the parameters for the developed prototype. The performance of the VLI was evaluated. A DC power source temporarily substitutes for the PV array to counteract the effects of weather during the experiment. Fig. 6 shows the experimental results for the VLI for a DC input voltage of 120V. The output voltage from the VLI is a seven-level voltage that is synchronous with the grid voltage. The output current is sinusoidal and in phase with the grid voltage. Fig. 7 shows the experimental results for the VLI for a DC input voltage of 90 V. It is seen that the output voltage from the VLI has five levels. The output current is also sinusoidal and in phase with the grid voltage. Fig. 8 shows the experimental results for the VLI for a DC input voltage of 180 V. It is seen that the output voltage from the VLI is a three-level voltage and the
Fig. 6. Experimental results of VLI under the DC 120 V input voltage: (a) grid voltage, (b) output voltage of the VLI and (c) output current of the VLI.
Fig. 7. Experimental results of VLI under the DC 90 V input voltage: (a) grid voltage, (b) output voltage of the VLI and (c) output current of the VLI.
Fig. 5. Photograph of the prototype, for (a) power circuit and (b) control circuit.
Table 2 Parameters of prototype. VLI Capacitor C1 Output filter S1,S2
2000lF L:1.2 mH, C:3lF
D1,D2
MOSFET: IRFP260N CVFD20065
TMBBC Inductors L1 and L2
1 mH
S7,S8 D4-D6
MOSFET: IRFP260N DSEI60-06A
Capacitor C2 PWM frequency S3–S6
4000lF 20 kHz
PWM frequency D3
20 kHz
IGBT: FGH60N60
CVFD20065
Fig. 8. Experimental results of VLI under the DC 180 V input voltage: (a) grid voltage, (b) output voltage of the VLI and (c) output current of the VLI.
output current is also sinusoidal and in phase with the grid voltage. Fig. 9 shows the experimental results for the VLI when the DC input voltage is varied from 90 V to 60 V. The output voltage from the VLI gradually changes from a five-level voltage to an unsymmetric seven-level voltage and finally becomes a symmetric seven-level voltage.
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Fig. 9. Experimental results of VLI under the varied DC input voltage: (a) input voltage, (b) output voltage of the VLI and (c) output current of the VLI.
The current for the total inductor path is decreased and its magnitude is the same as that for a single inductor when S7 is turned off. The maximum power efficiencies are 97.6%, 97.3 and 95.5% for the proposed PV power system when the DC input voltages are 120 V, 90 V and 60 V, respectively. Fig. 11 shows the experimental results for maximum power point tracking for the proposed PV power system. The PV array, which is composed of three PV modules, was applied to the input of the PV power system. The open-circuit voltage and short-circuit current for the PV modules were 38.08 V and 8.65 A, respectively. As is seen in Fig. 11(a), the output power from the PV array is recorded while scanning its output voltage and the maximum power is 0.68 kW. Fig. 11(b) shows the MPPT process for the proposed PV power system. As can be seen, the output power is increased while the proposed grid interface is operated and the output power remains constant while the MPP is tracked. The tracked maximum power is equal to that shown in Fig. 11(a). The experimental results, shown in Figs. 6–9, verify that the proposed VLI can convert DC power to AC power and generate a voltage that has different voltage levels, depending on the input voltage. It is more flexible as compared to the conventional ML inverter whose output voltage has fixed levels. This also has the salient feature that the partial power from the PV array is directly converted to AC power via only the VLI in the proposed grid interface. From Fig. 10, it verifies that two inductors are energized in parallel and de-energized in series when the TMBBC is operated to boost voltage. Hence, the boost gain of TMMBC can be double as compared to the conventional buck-boost power converter such that the minimum operation voltage for the PV array can be extended. As seen in Fig. 11, it verifies that the proposed grid interface can effectively perform the MPPT function in the application of PV power system. 8. Conclusion
Fig. 10. Experimental results of the TMBBC: (a) current of single inductor, (b) current of total inductor path and (c) control signal of S7.
Fig. 10 shows the experimental results for the TMBBC. As is seen in Fig. 10, the current for the total inductor path is increased and its magnitude is twice that for a single inductor when S7 is turned on.
The output voltage of PV array varies over a wide range, depending on the material, the configuration and the environmental conditions. The proposed grid interface is composed of a VLI and a TMBBC. The output voltage of the proposed VLI may be three levels, five levels or seven levels according to the output voltage of PV array. In addition, partial power from the PV array is directly converted to AC power via only the VLI such that the power efficiency can be improved. The TMBBC can also be flexibly operated in two modes according to the output voltage of PV array. The boost gain is increased and the power efficiency is improved for
Fig. 11. Experimental results of maximum power point tracking, for (a) power scan and (b) MPPT process.
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the TMBBC as compared to the conventional buck-boost converter such that the operating voltage range for the PV array can be extended. The experimental results verify that the proposed PV power system can generate an AC voltage with different levels and output a sinusoidal current injecting into the grid according to the output voltage of PV array. In addition, the maximum power efficiencies is still more than 95% for the proposed PV power system even when the DC input voltage is decreased to 60 V. Acknowledgment This work was supported by ABLEREX Electronics Co. Ltd. for its financial support. References Ahmad, K.N.E.K., Rahim, N.A., Selvaraj, J., Rivai, A., Chaniago, K., 2013. An effective passive islanding detection method for PV single-phase grid-connected inverter. Sol. Energy 97, 155–167. Bharatiraja, C., Jeevananthan, S., Latha, R., 2010. Direct power control of grid connected PV systems with three level NPC inverter. Sol. Energy 84, 1175–1186. Boukezata, B., Gaubert, J.P., Chaoui, A., Hachemi, M., 2016. Predictive current control in multifunctional grid connected inverter interfaced by PV system. Sol. Energy 139, 130–141. Capella, G.J., Pou, J., Ceballos, S., Konstantinou, G., Zaragoza, J., Agelidis, V.G., 2015. Enhanced phase-shifted PWM carrier disposition for interleaved voltage-source inverters. IEEE Trans. Power Electron. 30, 1121–1125. Chen, S., Li, P., Brady, D., Lehman, B., 2013. Determining the optimum gridconnected photovoltaic inverter size. Sol. Energy 87, 96–116. Chinnaiyan, V.K., Jerome, J., Karpagam, J., 2013. An experimental investigation on a multilevel inverter for solar energy applications. Int. J. Electr. Power Energy Syst. 47, 157–167. Das, N., Wongsodihardjo, H., Islam, S., 2015. Modeling of multi-junction photovoltaic cell using MATLAB/Simulink to improve the conversion efficiency. Renew. Energy 74, 917–924. Gayathri Devi, K.S., Arun, S., Sreeja, C., 2014. Comparative study on different five level inverter topologies. Int. J. Electr. Power Energy Syst. 63, 363–372. Gupta, A., Chauhan, Y.K., Pachauri, R.K., 2016. A comparative investigation of maximum power point tracking methods for solar PV system. Sol. Energy 136, 236–253.
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Hart, D.W., 2004. Introduction to Power Electronics. Prentice Hall. Iero, D., Carbone, R., Carotenuto, R., Felini, C., Merenda, M., Pangallo, G., Corte, F.G.D., 2014. SPICE modelling of a complete photovoltaic system including modules, energy storage elements and a multilevel inverter. Sol. Energy 107, 338–350. Kumar, N., Saha, T.K., Dey, J., 2016. Modeling, control and analysis of cascaded inverter based grid-connected photovoltaic system. Int. J. Electr. Power Energy Syst. 76, 165–173. Lauria, D., Coppola, M., 2014. Design and control of an advanced PV inverter. Sol. Energy 110, 533–542. Mellit, A., Rezzouk, H., Messai, A., Medjahed, B., 2011. FPGA-based real time implementation of MPPT-controller for photovoltaic systems. Renew. Energy 36, 1652–1661. Nayar, C.V., Islam, S.M., Dehbonei, H., Tan, K., Sharma, H., Power Electronics for Renewable Energy Sources, 2011. Power Electronics Handbook (Third Edition), pp. 723–766. Patel, R., Panda, A.K., 2014. Real time implementation of PI and fuzzy logic controller based 3-phase 4-wire interleaved buck active power filter for mitigation of harmonics with id–iq control strategy. Int. J. Electr. Power Energy Syst. 59, 66–78. Sanjeevan, A.R., Kaarthik, R.S., Gopakumar, K., Rajeevan, P.P., Leon, J.I., Franquelo, L. G., 2016. Reduced common-mode voltage operation of a new seven-level hybrid multilevel inverter topology with a single DC voltage source. IET Power Electron. 9, 519–528. Shen, J.M., Jou, H.L., Wu, J.C., 2012. Novel transformer-less grid-connected power converter with negative grounding for photovoltaic generation system. IEEE Trans. Power Electron. 27, 1818–1829. Shen, J.M., Jou, H.L., Wu, J.C., Wu, K.D., 2013. Five-level inverter for renewable power generation system. IEEE Trans. Energy Convers. 28, 257–266. Spertino, F., Graditi, G., 2014. Power conditioning units in grid-connected photovoltaic systems: a comparison with different technologies and wide range of power ratings. Sol. Energy 108, 219–229. Tamyurek, B., Kirimer, B., 2015. An interleaved high-power flyback inverter for photovoltaic applications. IEEE Trans. Power Electron. 30, 3228–3241. Trabelsi, M., Ghazi, K.A., Al-Emadi, N., Ben-Brahim, L., 2013. A weighted real-time predictive controller for a grid connected flying capacitors inverter. Int. J. Electr. Power Energy Syst. 49, 322–332. Upadhyay, P., Pulipaka, S., Sharma, M., Kumar, R., 2017. A proposed maximum power point operating strategy for photovoltaic applications using monthly irradiance estimates. Sol. Energy 141, 266–277. Valan Rajkumar, M., Manoharan, P.S., 2013. FPGA based multilevel cascaded inverters with SVPWM algorithm for photovoltaic system. Sol. Energy 87, 229– 245. Wu, J.C., Wu, K.D., Jou, H.L., Chang, S.K., 2014. A small-scale grid-connected photovoltaic power system. IET Power Electron. 7, 2717–2725.
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A flexible grid interface for a PV power system Jinn-Chang Wu a,⇑, Hurng-Liahng Jou b, Jie-Hao Tsai a a b
Department of Microelectronics Engineering, National Kaohsiung Marine University, Kaohsiung 811, Taiwan, ROC Department of Electrical Engineering, National Kaohsiung University of Applied Sciences, Kaohsiung 807, Taiwan, ROC
a r t i c l e
i n f o
Article history: Received 3 October 2016 Received in revised form 13 January 2017 Accepted 26 January 2017 Available online 7 February 2017 Keywords: PV power system Multi-level inverter DC-DC converter
a b s t r a c t A PV power system with a flexible grid interface is studied in this paper. The flexible grid interface comprises two power conversion stages, a two-mode buck-boost converter (TMBBC) and a variable-level inverter (VLI). The operation of VLI is flexible according to the output DC voltage of the PV array, and it generates an AC voltage with three levels, five levels or seven levels and outputs a sinusoidal current to the grid. Partial power from the PV array is directly converted to AC power via only one power conversion such that the power efficiency for the PV power system is improved. Besides, the operating voltage range for the PV array can be extended because of the high boost gain of TMMBC. A hardware prototype is implemented to demonstrate the performance of the proposed flexible grid interface. Ó 2017 Elsevier Ltd. All rights reserved.
1. Introduction The major energy source for electrical power generation has been fossil fuels. However, the use of fossil fuels results in extreme climate change and air pollution. The development of renewable power systems has become important (Nayar et al., 2011). PV energy is inexhaustible. PV cells convert photovoltaic energy to DC electrical energy. Several PV cells are integrated into a PV module, and PV array is composed of several PV modules. The output electrical energy of a PV array is dependent on the irradiance and temperature (Das et al., 2015; Upadhyay et al., 2017; Gupta et al., 2016). Technological progress and mass production mean that the cost of PV modules is continuously dropping and the requirement for PV generation is still growing. The growth of PV generation is expected to alleviate the problems of global warming. Different operating voltage for the PV array generates different level of output power. A PV array has a unique maximum power point (MPP) for a specific irradiance and temperature (Upadhyay et al., 2017; Gupta et al., 2016). A power conversion interface is needed between the PV array and the load or the grid to extract the power of PV array and convert it to AC power and to perform the maximum power tracking (Upadhyay et al., 2017; Gupta et al., 2016; Chen et al., 2013). In general, small-scale PV power systems consist of fewer PV modules and the grid interface requires two power conversion stages: a DC-DC converter and a DC-AC inverter, connected in cascaded (Spertino and Graditi, 2014; Shen et al., 2012; Ahmad et al., ⇑ Corresponding author. E-mail address: [email protected] (J.-C. Wu). http://dx.doi.org/10.1016/j.solener.2017.01.062 0038-092X/Ó 2017 Elsevier Ltd. All rights reserved.
2013; Lauria and Coppola, 2014; Boukezata et al., 2016). The DCDC converter boosts the output voltage of PV array to the dc bus voltage of the DC-AC inverter. Bridge-type inverters are a popular means for converting DC power to AC power. A half-bridge inverter comprises only two power semiconductor switches and generates a two-level AC voltage. Four power semiconductor switches are imposed in the full-bridge inverter to convert a dc voltage to a two-level or three-level AC voltage. Usually, all of the output power from the PV array that is supplied to the load or the grid must be processed by both the DC-DC converter and the DC-AC inverter. Advances in semiconductor technology mean that passive elements are being replaced by power semiconductor devices in power conversion circuit. Several new topologies have been developed. An interleaved topology integrates several power converters in parallel and interleaves the switching of these power converters to allow frequency multiplication so a passive filter for an interleaved topology is smaller (Patel and Panda, 2014; Tamyurek and Kirimer, 2015; Capella et al., 2015). A multi-level (ML) topology generates more levels of output voltage and reduces the dominant switching harmonic. The passive filter that is required is also smaller (Iero et al., 2014; Bharatiraja et al., 2010; Gayathri Devi et al., 2014; Trabelsi et al., 2013; Sanjeevan et al., 2016; Chinnaiyan et al., 2013; Valan Rajkumar and Manoharan, 2013; Kumar et al., 2016). Since power semiconductor switches are operated by hard switching, there is a switching power loss. The switching power loss for a power semiconductor switch is dependent on the switching in the voltage, the current and the speed and the frequency. The power efficiency for a ML topology is improved by reducing the
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switching in the voltage during the switching process. Therefore, a ML topology is gradually used for small-scale DC-AC inverters. A diode-clamped ML inverter (DCMLI) utilities several diodes to maintain the output voltage at one of voltage levels of the dc bus (Iero et al., 2014; Bharatiraja et al., 2010; Gayathri Devi et al., 2014). A flying-capacitor ML inverter (FCMLI) uses several capacitors in the current path to provide different levels of output voltage (Trabelsi et al., 2013; Sanjeevan et al., 2016). However, DCMLI and FCMLI require regulation of the voltages in the capacitors because an asymmetric voltage results in the dc components appearing in the output voltage and current. A cascade ML inverter (CMLI) comprises several HBCs that are connected in series to generate an output voltage that combines the output voltages of the HBCs (Chinnaiyan et al., 2013; Valan Rajkumar and Manoharan, 2013; Kumar et al., 2016). However, several voltage sources are required for the operation of a cascade multi-level inverter. The integration of a H-bridge converter (HBC) and a three-port power converter (TPPC) to produce a five-level inverter and a seven-level inverter has been proposed by the authors (Shen et al., 2013; Wu et al., 2014). These respectively use symmetric input voltages and the input voltages with multiple relationships. However, a DC-DC converter is required to generate these dc voltages and all of the output power must be processed by two power conversion stages: a DC-DC converter and a DC-AC inverter. In this paper, a HBC and a TPPC are integrated to produce a variable-level inverter (VLI). This VLI is applied in a PV power system. The VLI generates a voltage with three levels, five levels, seven symmetric levels or seven asymmetric levels. A two-mode buck-boost converter (TMBBC) is developed to extend the voltage range for the PV array and to improve the power efficiency. Consequently, the operation of proposed grid interface is flexible according to the voltage of PV array. To verify the performance of the proposed PV power system, a hardware prototype is developed and tested.
2. Power circuit topology Fig. 1 shows the power circuit topology for the proposed PV power system. The flexible grid interface comprises a TMBBC and a VLI. The VLI is composed of a HBC and a TPPC. The TPPC has two input ports and an output port. The first input port is directly connected to the PV array and its voltage is controlled to trace the MPP for the PV array. The input of the TMBBC is also provided from
541
the PV array, and the output of this TMBBC provides a voltage to the second input port. These two input ports are directly connected in series. The TMBBC controls the voltage at the second input port and ensures that the sum of the voltages at the two input ports is greater than the amplitude of the grid voltage. The HBC is switched synchronously to the grid voltage to commutate the output voltage of the TPPC during the negative cycle of the grid voltage. Only the TPPC is operated in high-frequency switching. The TMBBC integrates two-mode inductors to allow a greater voltage gain, which extends the voltage range for the PV array and increases the power efficiency. Although the power circuit of VLI in the proposed grid interface is the same as that of inverter (Shen et al., 2013; Wu et al., 2014), the arrangement of VLI and TPPC for the proposed PV power system is novel. The DC-DC converter and VLI are connected in cascade and all of the output power must be processed by two power conversion stages in the previous PV power system (Shen et al., 2013; Wu et al., 2014). In addition, the relationship between the voltages of two input ports for the TPPC is fixed such that the amount of levels for the output voltage is fixed. For the proposed PV power system, shown in Fig. 1, the PV array directly supplies power to the first input port of TPPC such that partial power from the PV array can only be converted by only one power conversion stage. Besides, the amount of levels for the output voltage can be varied according to the output voltage of PV array.
3. Operation of VLI The VLI is composed of a HBC and a TPPC. The HBC is switched synchronously to the grid voltage, to generate an output voltage of alternate polarity, and the TPPC is switched in pulse-width modulation (PWM) to generate a dc pulse voltage that has variable levels and to control the output current of the VLI. Since the first input port of the TPPC is directly connected to the PV array, its voltage (VC2) is equal to the output voltage of PV array. The TMBBC generates the voltage (VC1) of the second input port for the TPPC such that the summation of the voltages at the two input ports is greater than the amplitude of the grid voltage. Fig. 2 shows the switching modes for the TPPC, and there are four modes (mode I, II, III and IV). The respective voltages at the output port for modes I, II, III and IV are VC1, VC2, VC1 + VC2 and 0. Consequently, the HBC outputs a voltage that has levels, VC1, VC2, (VC1 + VC2), 0, VC1, VC2 and VC1 + -
Fig. 1. Power circuit of the proposed PV power system.
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Fig. 2. Switching modes of the TPPC, for (a) mode I, (b) mode II, (c) mode III and (d) mode IV.
VC2. If VC1 is not equal to VC2, the output voltage from the VLI has seven levels. The VLI outputs a five-level voltage if VC1 is equal to VC2. If VC2 is greater than the setting voltage, which is greater than the amplitude of the grid voltage, VC1 is equal to zero and the VLI outputs a three-level voltage. The setting voltage is 180 V for a grid voltage of 110 V. The output power from a PV array varies depending on its output voltage, and there is a unique MPP for a specific environmental condition. To harvest PV power effectively, the output voltage of PV array must be regulated to trace the MPP, so VC2 varies within a wide range. According to the output voltage of PV array, the operation of the TPPC has four cases: VC1 < VC2, VC1 = VC2, VC1 > VC2 and VC2 > 180 V. The HBC is connected between the TPPC and the grid and is switched synchronously to the grid voltage to commutate the output voltage from the TPPC during the negative cycle of grid voltage. Therefore, in terms of the TPPC, the HBC is regarded as an absolute circuit, and the TPPC is regarded as a buck converter with a variable output voltage (absolute grid voltage). Therefore, the output voltage from the TPPC cannot be controlled. The control object for the TPPC is the output current. The four operating cases for the TPPC are as follows: 3.1. Case 1: VC1 < VC2 In this case, the output voltage of PV array is higher than half of the setting voltage. The operation of the TPPC is divided into three periods for this case because the magnitude of utility voltage is time-variant (sinusoidal) waveform. The power semiconductor switches, S1 and S2, in the TPPC must generate two voltage levels around the magnitude of grid voltage to increase and decrease the output current and follow the current reference during each period. When the magnitude of the grid voltage is smaller than VC1, the TPPC operates between switching modes I and IV, so S1 is operated in PWM and S2 is always turned off. Therefore, the TPPC generates two voltage levels: VC1 and 0. The TPPC is operated between switching modes I and II when the magnitude of grid voltage is between VC1 and VC2. Both S1 and S2 are switched in complementary PWM to generate VC2 or VC1. If the magnitude of the grid voltage is greater than VC2, the TPPC is operated between switching modes II and III, so S1 is operated in PWM and S2 is always turned on. The TPPC generates two voltage levels: (VC2 + VC1) and VC1. Therefore, the TPPC generates a voltage that has four levels, according to the magnitude of the grid voltage, and the VLI outputs a seven-level voltage.
ates a voltage that has four levels, according to the magnitude of the grid voltage, and the VLI also outputs a seven-level voltage. 3.3. Case 3: VC1 = VC2 The TPPC is operated in case 3 when the output voltage of PV array is just equal to half of the setting voltage. In this case, the operation of the TPPC is divided into two periods. When the magnitude of the grid voltage is less than VC2, S1 and S2 can have two switching operations. The first is the integration of switching modes I and IV and the other is the integration of switching modes II and IV. To achieve greater power efficiency, switching modes II and IV are preferred because the power is directly supplied from the PV array (not the TMBBC). Therefore, S2 is operated in PWM and S1 is always turned off. This generates two voltage levels, VC2 and 0, during this period. If the magnitude of grid voltage is greater than VC2, S1 and S2 are also switched in two different ways. The first is the integration of switching modes I and III and the second is the integration of switching modes II and III. Switching modes II and III are preferred because the PV array (not the TMBBC) still supplies power in these two switching modes such that the power efficiency is greater. Therefore, S1 is operated in PWM and S2 is always turned on. This generates two voltage levels, 2VC2 and VC2, during this period. Therefore, the TPPC generates a voltage that has three levels, according to the magnitude of the grid voltage, and the VLI outputs a five-level voltage. 3.4. Case 4: VC2 > 180 V In this case, the output voltage of PV array is greater than the setting voltage. The TMBBC is disabled and VC1 = 0 V. For this condition, S2 is operated in PWM and S1 is always turned off and the TPPC is operated between switching modes II and IV. The TPPC generates two voltage levels: VC2 and 0. Accordingly, the VLI outputs a three-level voltage. The operations of S1 and S2 are integrated in Table 1. PWM is used to control the TPPC where a modulation signal vm is comTable 1 Operation of S1 and S2.
VC1 > VC2
S1
S2
|vu| < VC2 VC1 > |vu| > VC2
Off PWM
PWM
|vu| > VC1
On
PWM PWM
3.2. Case 2: VC1 > VC2
VC1 = VC2
|vu| < VC2 |vu| > VC2
Off On
PWM PWM
In this case, the output voltage of PV array is less than half of the setting voltage. The operation of the TPPC for this condition is similar to that for the case 1. The difference is that the turned-on and turned-off operations for S1 and S2 are reversed. The TPPC gener-
VC1 < VC2
|vu| < VC1 VC2 > |vu| > VC1
PWM
Off PWM
|vu| > VC2 VC2 > 180 V
PWM PWM Off
On PWM
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pared with a triangle signal. The duty for the PWM control is represented as:
continuous-conduction mode (CCM), the transfer function for TMBBC is represented as (Hart, 2004):
dt ¼ vm =Vtri
VC1 Dd ¼ VC2 1 Dd
ð1Þ
where Vtri is the peak value of the triangle signal. The average output voltage for the TPPC is derived as:
vot ¼ dt DV þ Vx ¼ kTPPC vm þ Vx
ð2Þ
where DV is the difference between the two voltage levels and Vx is the lower voltage level during each operational period. The TPPC can be regarded as an amplifier with the gain KTPPC and is represented as:
kTPPC ¼ DV=Vtri
ð3Þ
The current-mode control in the TPPC controls the output current. Fig. 3 shows a simplified model of the TPPC, where kc and Gc are the transfer functions for the current detector and the current controller and L is the inductance of the filter inductor. In terms of the TPPC, the grid voltage and the output current for the VLI are represented by their absolute value in Fig. 3. The absolute output current (|IL|) is derived as:
jIL j ¼
kTPPC Gc =L 1=L jI j ðjVu j Vx Þ s þ kc kTPPC Gc =L L s þ kc kTPPC Gc =L
ð4Þ
where jIL j is the absolute current reference. Since the output current is expected to be sinusoidal, jIL j is an absolute sinusoidal signal. The second term in (4) is the disturbance of the current-mode control, and it can be attenuated by a feed-forward control, which is Gf, shown in Fig. 3. Since the feed-forward control provides the major part of the modulation signal, the current controller adopts a proportional control to fine-tune the modulation signal. 4. Operation of TMBBC Since the negative terminal of VC1 is joined to the positive terminal of VC2, a buck-boost converter is used to build VC1 from VC2. Ideally, the gain for the buck-boost converter is infinite when the duty ratio for the power semiconductor switch approaches unity. However, the gain for a buck-boost converter is limited because there are power losses in the inductor and power semiconductor devices. The greater duty ratio for the power semiconductor switch will conduct serious degradation in power efficiency. The TMBBC, which is shown in Fig. 1, is developed in the PV power system. As can be seen, a controllable inductor set replaces the inductor of the buck-boost power converter. The controllable inductor set is composed of a power semiconductor switch S8, three diodes, D4, D5 and D6, and two inductors. The operation of a TMBBC has two modes. When VC2 is greater than VC1, S8 is turned off and the two inductors are operated in parallel. The operation of TMBBC is similar to that for a conventional buck-boost power converter. In
Fig. 3. Simplified model of the TPPC.
ð5Þ
where Dd is the duty of S7. Since VC2 is greater than VC1, Dd is smaller than 0.5. When VC2 is smaller than VC1, S8 is still turned on. When S7 is turned on, D4 and D5 conduct and the path, S8 and D6, is disabled because D6 has a reverse bias. Consequently, the two inductors are charged in parallel. If the two inductors are identical, the current in each inductor is the same and can be represented as:
diLa VC2 ¼ dt La
ð6Þ
The change in the inductor current during the period when S7 is on is derived as:
ðDiLa Þon ¼
VC2 Dd T La
ð7Þ
When S7 is turned off, D4 and D5 are turned off and the path, S8 and D6, is enabled. Consequently, the two inductors are discharged in series through the path, S8 and D6. The current in the inductor is represented as:
diLa VC1 ¼ dt 2La
ð8Þ
The change in the inductor current during the period when S7 is off is derived as:
ðDiLa Þoff ¼
VC1 ð1 Dd ÞT 2La
ð9Þ
In the steady state, (DiLa)on is equal to (DiLa)off and the transfer function for the TMBBC is derived as
VC1 2Dd ¼ VC2 1 Dd
ð10Þ
The transfer function for the TMBBC is twice that of conventional buck-boost power converter, so the operating voltage for the PV array can be extended. 5. Disscussion A small-scale PV power system consists of fewer PV modules and the output voltage of PV array is low. Conventionally, two power conversion stages, a DC-DC converter and a DC-AC inverter, are used in the grid interface for a small-scale PV power system. The power from the PV array to the grid should be converted by two power conversion stages. The power efficiency (g) for a conventional grid interface can be represented as:
g ¼ gdc—dc gdc—ac
ð11Þ
where gdc–dc and gdc–ac are the power efficiencies for the DC-DC converter and DC-AC inverter, respectively. A ML topology can be used in the DC-AC inverter to reduce the switching loss and the dominant switching harmonic (Iero et al., 2014; Bharatiraja et al., 2010; Gayathri Devi et al., 2014; Trabelsi et al., 2013; Sanjeevan et al., 2016; Chinnaiyan et al., 2013; Valan Rajkumar and Manoharan, 2013; Kumar et al., 2016; Shen et al., 2013; Wu et al., 2014). The power efficiency gdc–ac is improved. However, the power from the PV array to the grid is still processed by two power conversion stages. In addition, the amount of levels for the output voltage of conventional ML inverter is fixed. In the proposed grid interface, operation of the VLI is flexible and the amount of levels for the output voltage may be three, five or seven according to the output voltage of PV array. In addition, partial power from the PV array is
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directly converted to AC power via only the VLI. The power efficiency for the proposed grid interface can be represented as:
g ¼ kgdc—ac þ ð1 kÞgdc—dc gdc—ac
ð12Þ
where k is the power ratio converted by only the VLI, and it is dependent on the output voltage of PV array. k is increased when the output voltage of PV array increases. As compared to (11), the power efficiency for the proposed grid interface is improved. 6. Control diagram The control objects for the VLI are the output current and the voltage of the PV array. An outer voltage control loop adjusts the voltage of the PV array to trace the MPP for the PV array and an inner control loop is applied to generate a high-quality AC current that is sinusoidal and in phase with the grid voltage. Fig. 4(a) shows the control diagram for the VLI. The perturbation and observation (P&O) method is employed for tracing MPP (Mellit et al., 2011). The voltage of the PV array is disturbed and the change in the output power is observed, to decide the next perturbation for the PV array. The output power for the PV power system replaces the output power for the PV array as the observed parameter for the proposed PV power system, which obviates the need for a current detector in the PV array. As seen in Fig. 4(a), the outer voltage control loop is employed to control the voltage, VC2, to follow the output from the maximum power point tracking (MPPT) controller. The output of PI controller is the calculated amplitude for the output current. The grid voltage is sent to a signal generator, to generate an absolute sinusoidal signal with unity amplitude. Both the outputs from the PI controller and the signal generator are sent to a multiplier, to calculate the
current reference. The inner current control loop is employed to control the absolute output current to follow the current reference. Finally, the modulation signal is obtained by summing the outputs from the current controller and the feed-forward. The PWM circuit compares the modulation signal with a triangle signal to produce the PWM signal. The control signals for S1 and S2, shown in Table 1, must take account of the magnitude of the grid voltage, VC1 and VC2. Therefore, the PWM signal, the magnitude of the grid voltage, VC1 and VC2 are sent to the switching signal generator to produce the switching signals for S1 and S2. The grid voltage is also sent to a comparator, to produce the switching signals for S3, S4, S5 and S6. Since the amplitude of the grid voltage is regarded as a constant value over a short period, the output power for the PV power system can be decided by the amplitude of its output current. In the steady state, the amplitude of the output current approaches the result of the PI controller. Therefore, the result of the PI controller can be used to observe the change in the output power for the PV power system in the MPPT control. Since the sum of VC1 and VC2 must be equal to the setting voltage, the control object for the TMBBC is VC1. Fig. 4(b) shows the control block for the TMBBC. The output from the MPPT controller is the voltage reference for VC2. This is subtracted from the setting voltage to obtain the voltage reference for VC1. The voltage reference for VC1 is compared to the detected value of VC1 and then delivered to a PI controller. To increase the stability of the TMBBC, the current control is integrated. The output from the PI controller is compared to the detected inductor current and then sent to the amplifier. The output from the amplifier is the modulation signal, and the PWM circuit compares the modulation signal with a triangle signal to produce the switching signal for S7. The output for the MPPT controller and half of the setting voltage are sent to the comparator to provide the switching signal for S8.
Fig. 4. Control block of the proposed PV power system, for (a) VLI and (b) TMBBC.
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7. Experimental results A prototype was established to evaluate the functions of the proposed PV power system. The controller, shown in Fig. 4, is implemented by a digital signal processor TMS320F28035. Fig. 5 shows the photograph for the prototype. The power rating of prototype is 700 W. MOSFETs are used for S1, S2 of TPPC and S7, S8 of TMBBC because of high-frequency switching. S3–S6 of HBC are switched synchronously to the grid voltage such that IGBTs are used. Considering low reverse-recovery loss, SiC diodes are used for D1, D2 of TPPC and D3 of TMPPC. The voltage of the singlephase grid was 110 V and 60 Hz. Table 2 summarizes the parameters for the developed prototype. The performance of the VLI was evaluated. A DC power source temporarily substitutes for the PV array to counteract the effects of weather during the experiment. Fig. 6 shows the experimental results for the VLI for a DC input voltage of 120V. The output voltage from the VLI is a seven-level voltage that is synchronous with the grid voltage. The output current is sinusoidal and in phase with the grid voltage. Fig. 7 shows the experimental results for the VLI for a DC input voltage of 90 V. It is seen that the output voltage from the VLI has five levels. The output current is also sinusoidal and in phase with the grid voltage. Fig. 8 shows the experimental results for the VLI for a DC input voltage of 180 V. It is seen that the output voltage from the VLI is a three-level voltage and the
Fig. 6. Experimental results of VLI under the DC 120 V input voltage: (a) grid voltage, (b) output voltage of the VLI and (c) output current of the VLI.
Fig. 7. Experimental results of VLI under the DC 90 V input voltage: (a) grid voltage, (b) output voltage of the VLI and (c) output current of the VLI.
Fig. 5. Photograph of the prototype, for (a) power circuit and (b) control circuit.
Table 2 Parameters of prototype. VLI Capacitor C1 Output filter S1,S2
2000lF L:1.2 mH, C:3lF
D1,D2
MOSFET: IRFP260N CVFD20065
TMBBC Inductors L1 and L2
1 mH
S7,S8 D4-D6
MOSFET: IRFP260N DSEI60-06A
Capacitor C2 PWM frequency S3–S6
4000lF 20 kHz
PWM frequency D3
20 kHz
IGBT: FGH60N60
CVFD20065
Fig. 8. Experimental results of VLI under the DC 180 V input voltage: (a) grid voltage, (b) output voltage of the VLI and (c) output current of the VLI.
output current is also sinusoidal and in phase with the grid voltage. Fig. 9 shows the experimental results for the VLI when the DC input voltage is varied from 90 V to 60 V. The output voltage from the VLI gradually changes from a five-level voltage to an unsymmetric seven-level voltage and finally becomes a symmetric seven-level voltage.
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Fig. 9. Experimental results of VLI under the varied DC input voltage: (a) input voltage, (b) output voltage of the VLI and (c) output current of the VLI.
The current for the total inductor path is decreased and its magnitude is the same as that for a single inductor when S7 is turned off. The maximum power efficiencies are 97.6%, 97.3 and 95.5% for the proposed PV power system when the DC input voltages are 120 V, 90 V and 60 V, respectively. Fig. 11 shows the experimental results for maximum power point tracking for the proposed PV power system. The PV array, which is composed of three PV modules, was applied to the input of the PV power system. The open-circuit voltage and short-circuit current for the PV modules were 38.08 V and 8.65 A, respectively. As is seen in Fig. 11(a), the output power from the PV array is recorded while scanning its output voltage and the maximum power is 0.68 kW. Fig. 11(b) shows the MPPT process for the proposed PV power system. As can be seen, the output power is increased while the proposed grid interface is operated and the output power remains constant while the MPP is tracked. The tracked maximum power is equal to that shown in Fig. 11(a). The experimental results, shown in Figs. 6–9, verify that the proposed VLI can convert DC power to AC power and generate a voltage that has different voltage levels, depending on the input voltage. It is more flexible as compared to the conventional ML inverter whose output voltage has fixed levels. This also has the salient feature that the partial power from the PV array is directly converted to AC power via only the VLI in the proposed grid interface. From Fig. 10, it verifies that two inductors are energized in parallel and de-energized in series when the TMBBC is operated to boost voltage. Hence, the boost gain of TMMBC can be double as compared to the conventional buck-boost power converter such that the minimum operation voltage for the PV array can be extended. As seen in Fig. 11, it verifies that the proposed grid interface can effectively perform the MPPT function in the application of PV power system. 8. Conclusion
Fig. 10. Experimental results of the TMBBC: (a) current of single inductor, (b) current of total inductor path and (c) control signal of S7.
Fig. 10 shows the experimental results for the TMBBC. As is seen in Fig. 10, the current for the total inductor path is increased and its magnitude is twice that for a single inductor when S7 is turned on.
The output voltage of PV array varies over a wide range, depending on the material, the configuration and the environmental conditions. The proposed grid interface is composed of a VLI and a TMBBC. The output voltage of the proposed VLI may be three levels, five levels or seven levels according to the output voltage of PV array. In addition, partial power from the PV array is directly converted to AC power via only the VLI such that the power efficiency can be improved. The TMBBC can also be flexibly operated in two modes according to the output voltage of PV array. The boost gain is increased and the power efficiency is improved for
Fig. 11. Experimental results of maximum power point tracking, for (a) power scan and (b) MPPT process.
J.-C. Wu et al. / Solar Energy 144 (2017) 540–547
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