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A flexible system-on-chip (SoC) for biomedical signal acquisition and processing
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Sensors and Actuators A 142 (2008) 361–368
A flexible system-on-chip (SoC) for biomedical signal acquisition and processing N. Van Helleputte a,∗ , J.M. Tomasik b , W. Galjan b , A. Mora-Sanchez b , D. Schroeder b , W.H. Krautschneider b , R. Puers a b
a KU Leuven – ESAT-MICAS, Kasteelpark Arenberg 10, B-3001 Heverlee, Belgium Hamburg University of Technology, 38, Eissendorfer Straße, D-21073 Hamburg, Germany
Received 29 September 2006; received in revised form 4 April 2007; accepted 10 April 2007 Available online 19 April 2007
Abstract In this paper, a system-on-chip (SoC) that combines multiple biomedical signal acquisition (ECG, EEG, EP, and respiration-related signals) with on-chip digital signal processing is presented. The embedded flexibility of the SoC facilitates its use in a multitude of applications. Time-sharing of the operational transconductance amplifier within the analog-to-digital converters is employed in order to lower the power consumption and to save area. Built-in self-test (BIST) and autocalibration capabilities are included to enhance its reliability. The low noise analog front-end (AFE) is fully programmable to achieve the best power-noise trade-off for the application at hand. A prototype has been manufactured in 0.35 m 3.3 V CMOS technology. © 2007 Elsevier B.V. All rights reserved. Keywords: SoC; Built-in self-test and autocalibration; Biomedical potentials measurement
1. Introduction The next two decades will see significant changes in the health needs of the world’s population because of increased life expectancy, rising health care, and increasing associated costs [1]. One approach to cope with these problems is to reduce the high hospitalization costs through “homecare”. This constitutes a shift of in-hospital care to the home for certain tasks (e.g. monitoring). For homecare to be feasible, the need arises for highly sophisticated, mobile medical equipment [2–4]. In order to keep size, cost, and power consumption reasonable, a high level of system integration is desirable. Several approaches towards integrated analog front-ends (AFE) (responsible for signal acquisition) in CMOS technology have been accomplished [5,6]. Other research efforts have extended the integrated analog front-end with on-chip analog-to-digital converters that allows for easy post-processing and/or data-storage [7,8]. As an added advantage, this approach reduces the signal path, resulting in
∗
Corresponding author. Tel.: +3216328618; fax: +3216321975. E-mail address: [email protected] (N. Van Helleputte).
0924-4247/$ – see front matter © 2007 Elsevier B.V. All rights reserved. doi:10.1016/j.sna.2007.04.026
less interference/noise coupling into the system. Finally, adding real-time signal processing as in [4,9,10] yields a system well suited for homecare. In this paper a reliable, multipurpose single-chip solution, providing all of the above-mentioned functionality in a compact form, is presented. The system-on-chip (SoC) concept allows for improved performances in terms of cost, area, speed, and power consumption compared to discrete or partly integrated solutions [4,9]. The proposed flexible analog front-end is able to measure ECG, EEG, EP, and respiration-related signals. Realtime on-chip digital processing eliminates the need for additional computer resources. The built-in self-test (BIST) and autocalibration reduces manufacturing costs due to an increased yield and reduced testing overhead. Furthermore, it enhances the reliability and ease-of-use, which is especially important for homecare. With such a generic fully programmable IC, the cost-efficient development of biomedical devices for different applications in the field of homecare and emergency comes within reach. The system architecture is described in Section 2. Section 3 details the design of each of the functional blocks. A prototype IC, manufactured in a standard 0.35 m CMOS
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Fig. 1. System architecture.
technology, is presented along with measurement results in Section 4. 2. System description Fig. 1 shows a functional block diagram of the proposed SoCarchitecture. The programmable AFE is capable of acquiring and amplifying biomedical signals like ECG, EEG, and EP. A respiration measurement system, reusing part of the AFE, is also included. The AFE contains circuitry for calibrating key specifications like CMRR and gain mismatch between channels. A programmable signal generator capable of outputting sine waves with different amplitude and frequency is used to apply known stimuli. Combined with the digital signal processing capabilities of an on-chip DSP, this allows the inclusion of BIST and autocalibration. The AFE is followed by Analog-to-DigitalConverters (ADCs). In order to reduce power consumption, time-sharing of operational transconductance amplifiers inside the ADCs is employed. Three UART’s and 16 multipurpose I/O-pins are included to provide flexible communication with a readout device or a wireless data transmission module (e.g. bluetooth or zigbee). The Timing and Control Unit (TCU) generates the clocking signals for the different digital subblocks and powerdown signals for the different analog subblocks. With the TCU it is possible to specifically tailor the power-performance trade-off for each application. 3. Block description 3.1. AFE The AFE [11] has several identical channels with a programmable amplification factor (20, 80 or 320) and cut-off
frequency (3 or 15 kHz). A single channel consists of a preamplifier, a postamplifier, a low-pass filter, and an ADC as shown in Fig. 2. The opamps used can trade noise for power. As such, the AFE can be used for the acquisition of ECG, EEG, and EP signals. Low power consumption is required in applications like long-term wearable ECG monitors (less then 5 mW per channel) whereas EEG/EP-measurements have a more profound noise requirement (see Table 3). 3.2. Calibration circuitry To provide accurate biomedical signal acquisition, a CMRR of at least 65 dB and gain errors between channels of less than 1% are required. Inevitable mismatch on the gain setting resistors will have a detrimental influence on the specifications. To counter these effects, two very precise tuneable resistors are included in the gain-setting resistor chains (see Fig. 2). One is used for calibrating the gain, the other is used for calibrating the CMRR. Each tuneable resistor is digitally controlled by four bits and consists of four similar cascaded stages. Fig. 3 shows the schematic of a single stage. Table 1 clarifies the working principle. When the switch is open, a total resistance Rtot equal to R0 (e.g. 15 in the first stage) is present between its terminals, whereas when the switch is closed Rtot equals the parallel resistance of R0 and R2 (e.g. 13.8 in the first stage). The values are chosen so that the difference between R0 (switch open) and the parallel of R0 and R2 (switch closed) is only 1.2 in the first stage. The step sizes of the cascaded stages are binary weighted (1.2, 2.4, 4.8, and 9.6 ) so that 16 different resistances with a resolution of 1.2 can be generated in a linear fashion. The switches are implemented using MOS passgates. Large transistor sizes were chosen in order to minimize the channel resistance. Due to process variations, there is a rather significant uncertainty
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Fig. 2. Schematic view of a single channel.
on the exact value. Furthermore, the actual switch resistance is slightly dependent on the Vgs and Vds . The resistors were chosen so that a fairly large uncertainty on the switch resistance will result in only a slight variation on the total resistance of the stage (see Table 1). Fig. 4 shows the parallel resistance of R0 and R2 as a function of R2 . As can be seen in the plot, by choosing a value of R2 significantly larger then R0 , the total parallel resistance is fairly independent on variations of R2 . The resulting resistance is now mainly dependent on mismatch on the ratio of R0 and R1 , which is easier to control and has a less profound effect.
Table 1 Resistor values in first stage Switch
Open
Closed
R0 R2 Rtot Difference
15 175 ± 10 15
15 175 ± 10 ∼13.8
1.2 ± .06
3.3. ADCs The resolution of the ADC is required to be 16 bits for EEG and EP signals, whereas for ECG signals, 12 bits are sufficient. Since biomedical signals have their bandwidth in the low frequency range, and because of the required resolution, ADCs
Fig. 3. A single stage of the tuneable resistor.
Fig. 4. Parallel resistance as a function of R2 .
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are the proper choice. The implemented converter consists of a 2nd-order discrete-time 1-bit -modulator followed by a digital decimation filter. The modulator has been realized as a time-sharing single-opamp architecture [12], which reduces the power consumption compared to traditional approaches and helps to minimize the on-chip area. In its actual implementation a configurable fully-differential 2-stage class A/AB OTA and a regenerative latched comparator were employed. The digital filter is based on the polyphase decomposition of a 3rd-order comb filter with decimation factor of 256, featuring a very lowpower consumption which can be neglected compared to that of the modulator [13]. The ADCs output data rate can be adjusted from 1 to 50 kHz with 14 or more bits of accuracy, dissipating between 240 W and 3 mW. 3.4. Respiration The respiration monitoring system is fully integrated on chip with the exception of an external capacitor for low-pass filtering. The measurement principle is based on bioelectric impedance [14] measurement on the patients’ thorax and allows the measurement of respiration concurrently with an ECG-measurement using two ECG-electrodes. The circuit is also used to detect open-leads by measuring the absolute impedance between leads. If this impedance exceeds a certain threshold, the leads are assumed to be open. Fig. 5 shows the structure of the system. The on-chip oscillator generates two differential 40 kHz sine-signals, which are applied to the body-electrodes through additional impedances forming a voltage divider. The applied carrier-signal is modulated by a change of body impedance due to breathing of the patient. After the preamplifiers, both the ECG-signal and the modulated carrier are present. Because the carrier is located at 40 kHz, which is removed by the low-pass filter at the end of the analog channel, respiration measurement does not disturb ECG measurement. After the preamplifiers, the
differential carrier is converted to a single-ended signal. The very-low-frequency (<1 Hz) respiration signal modulated on the carrier signal can be considered as a slow varying DC-signal. To extract this DC-signal an active full-wave rectifier is used followed by a Sallen-Key low pass filter. The resulting signal VDC contains the respiration signal with an additional DC-offset due to rectification of the 40 kHz sine wave. This offset is given by VDCoffset = VPeak × 2/, where VPeak represents the peak voltage of the carrier signal. The obtained respiration signal is too small (in the microvolt range) to be directly A/D converted. Therefore, an adjustable postamplifier is used to amplify this signal. The gain can be set digitally to 25, 50, 100 or 125. To prevent saturation of the postamplifier, the DC-offset has to be reduced. A static solution to eliminate the DC-offset could not be used as any change of the sine-wave amplitude (due to a change in body and/or cable impedance, e.g. as a result of movement, sweating, etc.) would result in a change of this DC-level. We used a digital DC-offset control to prevent saturation, Fig. 6 shows the circuit. The first stage of the postamp consists of a non-inverting amplifier (A) with an additional amplifier (B) controlling the reference ground of the first stage. The reference ground can be changed by digitally controlling the gain of amplifier B. The second stage consists also of a non-inverting amplifier (C), here the overall gain is set digitally. Two comparators connected to the output of the postamp generate a (digital) signal indicating if the output signal is in saturation (e.g. too high or too low). If this occurs, the reference ground of the postamps’ first stage is changed to reduce this DC-offset accordingly. The amplified respiration signal is finally AD converted and the digitized signal can be read out by the on-chip DSP. 3.5. DSP and TCU A 16-bit high-performance fixed-point DSP and 17 Kb of memory are embedded in the SoC, enabling a wide range of on-
Fig. 5. Respiration measurement circuit.
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Fig. 6. Offset control circuit.
chip digital signal processing capabilities. This includes basic filtering like a 50 Hz notch filter and 0.1 Hz high pass filter for ECG signals, but also more advanced functionality. In an ECG application for instance, this could include ECG feature extraction, heart rate variability assessment, or signal compression for long term monitors. The DSP also governs other blocks through the TCU. The TCU contains read/write registers for the operational parameters (e.g. AFE’s gain and cut-off frequency, selective power down of unneeded parts) and read-only registers to store the digitized analog output. The TCU also generates the clock signals for the -ADCs. 3.6. Signal generator A signal generator capable of generating precise sine waves, based on the principle of digital resonators is used [15]. This has several benefits such as easy integration (mainly digital and no DAC needed), stability, and programmability. By changing the clock frequency and the initial values of delay elements in the digital resonator, the amplitude and frequency of the resulting output can be set. Peak-to-peak amplitudes ranging from 25 mV to 1.5 V and frequencies ranging from 50 to 40 kHz can be obtained. The lowest output amplitude is needed to measure the highest gain factor whereas the high output amplitude is needed for common mode gain measurement. Low frequency signals are required to do characterization in the bands of interest. The 40 kHz is needed for the respiration measurement. The output of the digital block is a single-bit digital signal. The sigma-delta modulation within the loop shapes the noise to higher frequencies. This digital signal is fed to a low pass filter, the output of which is the desired analog signal.
3.7. BIST & autocalibration Each time the IC is powered on, a test and calibration routine is run. The on-chip signal generator is used to generate known stimuli, which are applied to the AFE. The output is measured and the DSP can calculate key features like gain, CMRR, output noise and crosstalk. The BIST routine compares them to the specifications. For the autocalibration routine, the test signal is first applied to in2 and in1 is shorted to ref (see Fig. 2). Since in1 and ref are at the same potential, no current is flowing through the lower resistors. The output is only determined by the upper resistors. The upper tuneable resistor can be used to accurately set the gain factor to the desired value. Once that is done, in1 is shorted to in2 so that the testsignal is applied to the circuit as a common mode signal. The lower tuneable resistor can now be used to precisely match the bottom resistors to the upper one in order to maximize the CMRR. 4. Prototype A first prototype of the SoC with three channels was manufactured in a 0.35 m 3.3 V CMOS technology from Austria-Microsystems. Fig. 7 shows the photograph of the die. The die size is 6800 × 5500 m. 4.1. Power consumption and noise performance The power consumption of the different blocks is listed in Table 2. For the AFE two power consumptions are listed, one for a biasing current of 2 A for the amplifiers and one for a biasing current of 20 A. Table 3 lists the total input referred noise voltage for the two biasing currents in different frequency
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Fig. 8. Respiration measured on a real patient.
Fig. 7. Chip photograph. Fig. 9. DC-offset control. Table 2 Power consumption Digital
DSP TCU 3×UART
4.2. Respiration Dynamic power consumption (mW/MHz) Idle
Full load
0.62 ∼0 ∼0
1.77 0.19 1.47
Analog
Power consumption (mW)
ADC @1 KHz ADC @50 KHz AFE (Ibias = 1 A) AFE (Ibias = 20 A)
0.24 mW 3 mW 4 mW/channel 10 mW/channel
bands. A biasing current of 2 A is appropriate for ECG applications. For EEG/EMG and EP measurements a higher biasing current is needed in order to satisfy the noise requirement. For ECG a low sampling rate, consuming minimal power, can be used due to low frequency content, for EMG/EP a higher sampling rate, and thus power consumption, is needed. The digital parts can run at different clock frequencies as well depending on the required processing power and signal bandwidth. Therefore, the dynamic power consumption is expressed as mW/MHz. There is a total static power consumption of 0.6 mW. The other digital blocks can be switched off when they are not used.
The respiration circuit was tested with an artificial body impedance (Zbody ) of 300 and a cable impedance of 1 k. Respiration was simulated by varying Zbody . A change of 1 in Zbody resulted in a 12.5 mV change in output voltage. Breathing typically causes an impedance change in the range of 0.1–5 . Fig. 8 shows the output of the configurable postamplifier as measured on a patient (male, 70 kg, 30 yrs). The DC-offset control was tested with a slowly increasing carrier signal amplitude reflecting changes in the impedances of the thorax and contact between thorax and electrode. For example, the change can be caused by sweating of the patient. Fig. 9 shows the output of the configurable postamplifier (with gain 100 in this case). The amplitude of the 40 kHz test signal (without a respiration signal) is slowly increased which in turn increases the dc-offset at the input of the postamp. Every 4 mV change of DC-offset at the postamp’s input, the control-circuit changes the gain of
Table 3 Total input referred noise voltage Band (application)
Ib = 2 A (Vpp )
Ib = 20 A (Vpp )
Spec (Vpp )
.05–250 Hz (ECG) .5–70 Hz (EEG) .1–3 KHz (EP) .01–5 KHz (EMG)
1.47 0.89 3.55 4.32
0.96 0.61 1.78 2.08
<2.5 <0.75 <2.2 <3
Fig. 10. Spectrum of digital oscillator set to output at 4.95 kHz.
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Fig. 11. Measured gain and CMRR values for different values of the tuneable resistors. Gain of preamplifier was set to 20 (upper plots) and 80 (lower plots).
amplifier B in Fig. 6 and setting therefore a new DC-offset level (in Fig. 9 the postamp’s output DC-level drops to lower level at that point, preventing a saturation of the postamp). The ripple on the test signal is an artefact from the measurement set-up. 4.3. Signal generator The output spectrum of the digital oscillator is shown in Fig. 10. The noise shaping due to the sigma-delta modulation is clearly visible in the upper plot covering a large frequency span. The lower plot shows a close-up of the spectrum around the fundamental tone located at 4.95 kHz. The second harmonic is more than 60 dB below the signal. Similar results were measured for different output frequencies. Furthermore, no significant drift in amplitude or frequency over time could be noticed making these sine waves very suited to do calibration and BIST. 4.4. Autocalibration The on-chip oscillator was used to generate a sine wave with a frequency of 230 Hz. This signal was first applied to the AFE as a differential signal as explained in the previous section. The RMS value over 50 periods of the fundamental tone was calculated with the DSP. This value was then divided by the RMS value of the applied signal to obtain the gain factor. This was repeated for all 16 different values of the upper tuneable resistor (the one used for calibrating gain – see Fig. 2). The resulting measured
gain factors are displayed in the left plots of Fig. 11. In both cases (preamplifier set to gain 20 and gain 80) it was possible to find a gain factor within 0.5% of the desired value. The same procedure was repeated but this time the signal was applied as commonmode and the lower (CMRR) tuneable resistor was used while the upper one was fixed with the optimal value. The results are shown in the right plots of Fig. 11. Again it was possible to obtain the required specifications in both cases. Similar results were measured with different dies. 5. Conclusions and future work A flexible SoC for biomedical signal acquisition and on-chip processing is presented. The SoC employs a programmable AFE, BIST, autocalibration, -ADCs, respiration measurement circuitry and on-chip DSP. Furthermore, various power-saving techniques are employed. The result is a multipurpose, reliable and yet low-cost single-chip solution. A prototype was manufactured with three channels. This IC will be used in a proof-of-concept application. It will be a 24/7 battery-powered long-term ECG-monitoring device. The DSP running at 1 MHz, the TCU at 256 KHz, an ADC sample frequency of 500 Hz and a biasing current of 2 A for the AFE would result in a total current consumption of less than 5 mA. An additional 5 mA is needed for data storage. Two standard AA batteries with a capacity of 2000 mAh are sufficient to power the device for one week 24/7. The final board size will be about 10 × 5 cm, which can be further reduced by using a much smaller BGA package instead of the current PGA package.
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Acknowledgements This project is funded by the European Commission, DG RTD, Contract No. COOP-CT-2004-508291-M3C. References [1] Health at a Glance: OECD Indicators 2005. ISBN 92-64-01262-1. [2] I. Korhonen, J. P¨arkka, M. van Gils, Health monitoring in the home of the future, IEEE Eng. Med. Biol. Mag. (May/June 2003). [3] U. Edstrom, J. Skonevik, T. Backlund, J.S. Karlsson, A flexible measurement system for physiological signals in mobile health care, Engineering in Medicine and Biology Society 27th Annual International Conference, 2005. Pages: 2161–2162. [4] E. Jovanov, P. Gelabert, R. Adhami, P. Smith, Real time portable heart monitoring using low power DSP, in: International Conference on Signal Processing Applications and Technology, Dallas, Texas, October 2000. [5] R. Martins, S. Selberherr, F.A. Vaz, A CMOS IC for portable EEG acquisition systems, IEEE Trans. Instrum. Meas. 47 (no. 5) (Oct. 1998). [6] K.A. Ng, P.K. Chan, A CMOS analog front-end IC for portable EEG/ECG monitoring applications, IEEE Trans. Circ. Syst. 52 (no. 11) (Nov. 2005) 2335–2347. [7] T. Desel, T. Reichel, S. Rudischhauser, H. Hauer, A CMOS nine channel ECG measurement IC, Proc. 2nd IEEE Int. Conf. ASIC (Oct. 1996) 115–118. [8] B. Fuchs, S. Vogel, D. Schroeder, Universal application-specific integrated circuit for bioelectric data acquisition, Medical Engineering and Physics, no. 24, pp. 695–701. Elsevier Science Ltd., 2002. [9] S. L. Toral, J.M. Quero, M.E. Perez, L.G. Franquelo, A microprocessor based system for ECG telemedicine and telecare, IEEE Inter. Symp. on Circ. Syst., Syndey, Australia, May 2001, vol. 4, pp. 526–529. [10] B.R. Hayes-Gill, A.C. Cardoso, N. Meinke, J.A. Crowe, B. Francon, A. Harrison, A generic ASIC and DSP based ambulatory electrophysiological recorder, Data Logging of Physiological Signals, IEE Colloquium on, Vol., Iss., 23 Nov 1995. Pages: 9/1–9/3. [11] C. Bronskowski, D. Schroeder, A programmable analog front end for the acquisition of biomedical signals, in: ProRISC2004 Workshop, Veldhoven, 2004, pp. 474–477. [12] Alexander Mora-Sanchez, Dietmar Schroeder, Wolfgang H. Krautschneider, Sigma-delta modulators of 2nd- and 3rd-order with a single operational transconductance amplifier for low-power analogue-to-digital conversion, in: ProRisc2005 Workshop, 2005, pp. 259–262. [13] A. Mora-Sanchez, D. Schroeder, Low-power decimation filter in a 0. 35 m CMOS technology for a multi-channel biomedical data acquisition chip, in: XI Iberchip Workshop, Salvador do Bahia, Brasil, 2005, pp. 199–202. [14] J.D. Bronzino, et al., The Biomedical Engineering Handbook, CRC Press, 2000. [15] A. Lu, G. Roberts, A high-quality analog oscillator using oversampling D/A conversion techniques, IEEE Trans. Circ. Syst. 41 (no. 7) (July 1994) 437–444.
Biographies Nick Van Helleputte was born in Leuven, Belgium, in 1981. In 2004, he received the degree of M.S. in Electrical Engineering from the Katholieke Universiteit Leuven, Belgium. The subject of his MS thesis was on the design of an integrated analog front-end for foetal ECG monitoring. From 2004 up to now he is a research assistant at the MICAS laboratories of the Katholieke Universiteit Leuven. His current research activities include circuit design for biomedical applications and low-power analog radio design.
Jakob M. Tomasik was born in Gliwice, Poland, in 1975. In 2004, he received the diploma degree in computer science and engineering from the Hamburg University of Technology, Germany. From 2004 up to now he is a research assistant at the Institute of Nanoelectronics of the Hamburg University of Technology. Wjatscheslaw Galjan was born in Omsk, Russia, in 1976. In 2004, he received the diploma degree in Electrical Engineering from the Hamburg University of Technology, Germany. From 2004 up to now he is a research assistant at the Institute of Nanoelectronics of the Hamburg University of Technology. Alexander Mora-Sanchez was born in San Jose, Costa Rica, in 1975. He received both his Bachelor’s and Licentiate degrees in Electrical Engineering from the University of Costa Rica in 1997 and 1999, respectively. In 2002, he received the Master’s degree in Microelectronics and Microsystems from the Technical University of Hamburg-Harburg (TUHH), Hamburg, Germany. From 2002 up to now he is a research assistant with the Institute of Nanoelectronics of the TUHH, where he conducted research in the area of low-power mixed-signal ASICs/SoCs for biomedical applications. His research interest is in low-power digital design, low-power small-area sigma-delta A/D-modulators and SC-circuit design. He will finish his Ph.D. studies in 2006. Dietmar Schroeder received the Dipl.-Ing. and Dr.-Ing. degrees in Electrical Engineering from the Technical University of Braunschweig, Germany, in 1978 and 1984, respectively. From 1983 to 1985, he was an advisor for Electrical Engineering at the Computer Center, Technical University of Hamburg-Harburg, Germany. Since 1985, he has been Chief Engineer at the Department of Microelectronics. In 1994, he attained the academic degree of habilitation from TU Hamburg-Harburg, and is now lecturer for Semiconductor Electronics at this university. He has authored or co-authored 60 papers and one book. His research interests include low-power analog/digital converters, efficient signal processing based on information theory, mixed-signal integrated circuits for sensor interfaces, integrated circuits for medical technology, and modeling of charge transport in semiconductor devices. Wolfgang H. Krautschneider studied Electronics Engineering at Berlin University of Technology, Germany. After completion of his MS and Ph.D. degrees, he managed an industrial and academic joint project for automotive electronics. Then, he held an assignment as visiting scientist at the Central Research Laboratories of IBM in Yorktown Heights, USA. After this, he worked in the field of Megabit memory chips, first at the Siemens Corporate Research Center in Munich, Germany, and then in a joint DRAM development project of IBM and Siemens AG at the IBM site in Essex Junction, VT, USA. Next station of his professional life was the design of devices and circuits for Gigabit memories at the Corporate Research Laboratories of Siemens AG in Munich, Germany. In 1997, he received the Siemens Innovation Award for his invention of a new type of memory cell. In the same year, he completed his habilitation about “Solid-State Electronics” at the Berlin University of Technology. In 1999, he was appointed a full professor at Hamburg University of Technology, where he heads the institute of nanoelectronics. From 2002 to 2004, he served as Deputy Dean of the Faculty for Electrical Engineering of Hamburg University of Technology, and since 2004 as Dean of this faculty. He has authored and co-authored more than 75 scientific papers and is the inventor and co-inventor of more than 35 issued patents in the field of electronic circuits, memory cells and advanced semiconductor devices. Robert (Bob) Puers was born in Antwerpen, Belgium, 1953, and grew up in the Ghent. He received his B.S. degree in Electrical Engineering in Ghent in 1974, and his M.S. degree at the Katholieke Universiteit Leuven in 1977, where he obtained his Ph.D. in 1986. From 1980 he was employed as a Research Assistant at the Laboratory ESAT at K. U. Leuven. In 1986, he became Director (NFWO) of the clean room facilities for silicon and hybrid circuit technology at the ESAT-MICAS laboratories of the same university. His research interests are in silicon sensors, MEMS and packaging techniques, for biomedical implantable total systems as well as for industrial devices. Robert Puers is professor at the Katholieke Universiteit Leuven, Belgium, since 1991.
Sensors and Actuators A 142 (2008) 361–368
A flexible system-on-chip (SoC) for biomedical signal acquisition and processing N. Van Helleputte a,∗ , J.M. Tomasik b , W. Galjan b , A. Mora-Sanchez b , D. Schroeder b , W.H. Krautschneider b , R. Puers a b
a KU Leuven – ESAT-MICAS, Kasteelpark Arenberg 10, B-3001 Heverlee, Belgium Hamburg University of Technology, 38, Eissendorfer Straße, D-21073 Hamburg, Germany
Received 29 September 2006; received in revised form 4 April 2007; accepted 10 April 2007 Available online 19 April 2007
Abstract In this paper, a system-on-chip (SoC) that combines multiple biomedical signal acquisition (ECG, EEG, EP, and respiration-related signals) with on-chip digital signal processing is presented. The embedded flexibility of the SoC facilitates its use in a multitude of applications. Time-sharing of the operational transconductance amplifier within the analog-to-digital converters is employed in order to lower the power consumption and to save area. Built-in self-test (BIST) and autocalibration capabilities are included to enhance its reliability. The low noise analog front-end (AFE) is fully programmable to achieve the best power-noise trade-off for the application at hand. A prototype has been manufactured in 0.35 m 3.3 V CMOS technology. © 2007 Elsevier B.V. All rights reserved. Keywords: SoC; Built-in self-test and autocalibration; Biomedical potentials measurement
1. Introduction The next two decades will see significant changes in the health needs of the world’s population because of increased life expectancy, rising health care, and increasing associated costs [1]. One approach to cope with these problems is to reduce the high hospitalization costs through “homecare”. This constitutes a shift of in-hospital care to the home for certain tasks (e.g. monitoring). For homecare to be feasible, the need arises for highly sophisticated, mobile medical equipment [2–4]. In order to keep size, cost, and power consumption reasonable, a high level of system integration is desirable. Several approaches towards integrated analog front-ends (AFE) (responsible for signal acquisition) in CMOS technology have been accomplished [5,6]. Other research efforts have extended the integrated analog front-end with on-chip analog-to-digital converters that allows for easy post-processing and/or data-storage [7,8]. As an added advantage, this approach reduces the signal path, resulting in
∗
Corresponding author. Tel.: +3216328618; fax: +3216321975. E-mail address: [email protected] (N. Van Helleputte).
0924-4247/$ – see front matter © 2007 Elsevier B.V. All rights reserved. doi:10.1016/j.sna.2007.04.026
less interference/noise coupling into the system. Finally, adding real-time signal processing as in [4,9,10] yields a system well suited for homecare. In this paper a reliable, multipurpose single-chip solution, providing all of the above-mentioned functionality in a compact form, is presented. The system-on-chip (SoC) concept allows for improved performances in terms of cost, area, speed, and power consumption compared to discrete or partly integrated solutions [4,9]. The proposed flexible analog front-end is able to measure ECG, EEG, EP, and respiration-related signals. Realtime on-chip digital processing eliminates the need for additional computer resources. The built-in self-test (BIST) and autocalibration reduces manufacturing costs due to an increased yield and reduced testing overhead. Furthermore, it enhances the reliability and ease-of-use, which is especially important for homecare. With such a generic fully programmable IC, the cost-efficient development of biomedical devices for different applications in the field of homecare and emergency comes within reach. The system architecture is described in Section 2. Section 3 details the design of each of the functional blocks. A prototype IC, manufactured in a standard 0.35 m CMOS
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Fig. 1. System architecture.
technology, is presented along with measurement results in Section 4. 2. System description Fig. 1 shows a functional block diagram of the proposed SoCarchitecture. The programmable AFE is capable of acquiring and amplifying biomedical signals like ECG, EEG, and EP. A respiration measurement system, reusing part of the AFE, is also included. The AFE contains circuitry for calibrating key specifications like CMRR and gain mismatch between channels. A programmable signal generator capable of outputting sine waves with different amplitude and frequency is used to apply known stimuli. Combined with the digital signal processing capabilities of an on-chip DSP, this allows the inclusion of BIST and autocalibration. The AFE is followed by Analog-to-DigitalConverters (ADCs). In order to reduce power consumption, time-sharing of operational transconductance amplifiers inside the ADCs is employed. Three UART’s and 16 multipurpose I/O-pins are included to provide flexible communication with a readout device or a wireless data transmission module (e.g. bluetooth or zigbee). The Timing and Control Unit (TCU) generates the clocking signals for the different digital subblocks and powerdown signals for the different analog subblocks. With the TCU it is possible to specifically tailor the power-performance trade-off for each application. 3. Block description 3.1. AFE The AFE [11] has several identical channels with a programmable amplification factor (20, 80 or 320) and cut-off
frequency (3 or 15 kHz). A single channel consists of a preamplifier, a postamplifier, a low-pass filter, and an ADC as shown in Fig. 2. The opamps used can trade noise for power. As such, the AFE can be used for the acquisition of ECG, EEG, and EP signals. Low power consumption is required in applications like long-term wearable ECG monitors (less then 5 mW per channel) whereas EEG/EP-measurements have a more profound noise requirement (see Table 3). 3.2. Calibration circuitry To provide accurate biomedical signal acquisition, a CMRR of at least 65 dB and gain errors between channels of less than 1% are required. Inevitable mismatch on the gain setting resistors will have a detrimental influence on the specifications. To counter these effects, two very precise tuneable resistors are included in the gain-setting resistor chains (see Fig. 2). One is used for calibrating the gain, the other is used for calibrating the CMRR. Each tuneable resistor is digitally controlled by four bits and consists of four similar cascaded stages. Fig. 3 shows the schematic of a single stage. Table 1 clarifies the working principle. When the switch is open, a total resistance Rtot equal to R0 (e.g. 15 in the first stage) is present between its terminals, whereas when the switch is closed Rtot equals the parallel resistance of R0 and R2 (e.g. 13.8 in the first stage). The values are chosen so that the difference between R0 (switch open) and the parallel of R0 and R2 (switch closed) is only 1.2 in the first stage. The step sizes of the cascaded stages are binary weighted (1.2, 2.4, 4.8, and 9.6 ) so that 16 different resistances with a resolution of 1.2 can be generated in a linear fashion. The switches are implemented using MOS passgates. Large transistor sizes were chosen in order to minimize the channel resistance. Due to process variations, there is a rather significant uncertainty
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Fig. 2. Schematic view of a single channel.
on the exact value. Furthermore, the actual switch resistance is slightly dependent on the Vgs and Vds . The resistors were chosen so that a fairly large uncertainty on the switch resistance will result in only a slight variation on the total resistance of the stage (see Table 1). Fig. 4 shows the parallel resistance of R0 and R2 as a function of R2 . As can be seen in the plot, by choosing a value of R2 significantly larger then R0 , the total parallel resistance is fairly independent on variations of R2 . The resulting resistance is now mainly dependent on mismatch on the ratio of R0 and R1 , which is easier to control and has a less profound effect.
Table 1 Resistor values in first stage Switch
Open
Closed
R0 R2 Rtot Difference
15 175 ± 10 15
15 175 ± 10 ∼13.8
1.2 ± .06
3.3. ADCs The resolution of the ADC is required to be 16 bits for EEG and EP signals, whereas for ECG signals, 12 bits are sufficient. Since biomedical signals have their bandwidth in the low frequency range, and because of the required resolution, ADCs
Fig. 3. A single stage of the tuneable resistor.
Fig. 4. Parallel resistance as a function of R2 .
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are the proper choice. The implemented converter consists of a 2nd-order discrete-time 1-bit -modulator followed by a digital decimation filter. The modulator has been realized as a time-sharing single-opamp architecture [12], which reduces the power consumption compared to traditional approaches and helps to minimize the on-chip area. In its actual implementation a configurable fully-differential 2-stage class A/AB OTA and a regenerative latched comparator were employed. The digital filter is based on the polyphase decomposition of a 3rd-order comb filter with decimation factor of 256, featuring a very lowpower consumption which can be neglected compared to that of the modulator [13]. The ADCs output data rate can be adjusted from 1 to 50 kHz with 14 or more bits of accuracy, dissipating between 240 W and 3 mW. 3.4. Respiration The respiration monitoring system is fully integrated on chip with the exception of an external capacitor for low-pass filtering. The measurement principle is based on bioelectric impedance [14] measurement on the patients’ thorax and allows the measurement of respiration concurrently with an ECG-measurement using two ECG-electrodes. The circuit is also used to detect open-leads by measuring the absolute impedance between leads. If this impedance exceeds a certain threshold, the leads are assumed to be open. Fig. 5 shows the structure of the system. The on-chip oscillator generates two differential 40 kHz sine-signals, which are applied to the body-electrodes through additional impedances forming a voltage divider. The applied carrier-signal is modulated by a change of body impedance due to breathing of the patient. After the preamplifiers, both the ECG-signal and the modulated carrier are present. Because the carrier is located at 40 kHz, which is removed by the low-pass filter at the end of the analog channel, respiration measurement does not disturb ECG measurement. After the preamplifiers, the
differential carrier is converted to a single-ended signal. The very-low-frequency (<1 Hz) respiration signal modulated on the carrier signal can be considered as a slow varying DC-signal. To extract this DC-signal an active full-wave rectifier is used followed by a Sallen-Key low pass filter. The resulting signal VDC contains the respiration signal with an additional DC-offset due to rectification of the 40 kHz sine wave. This offset is given by VDCoffset = VPeak × 2/, where VPeak represents the peak voltage of the carrier signal. The obtained respiration signal is too small (in the microvolt range) to be directly A/D converted. Therefore, an adjustable postamplifier is used to amplify this signal. The gain can be set digitally to 25, 50, 100 or 125. To prevent saturation of the postamplifier, the DC-offset has to be reduced. A static solution to eliminate the DC-offset could not be used as any change of the sine-wave amplitude (due to a change in body and/or cable impedance, e.g. as a result of movement, sweating, etc.) would result in a change of this DC-level. We used a digital DC-offset control to prevent saturation, Fig. 6 shows the circuit. The first stage of the postamp consists of a non-inverting amplifier (A) with an additional amplifier (B) controlling the reference ground of the first stage. The reference ground can be changed by digitally controlling the gain of amplifier B. The second stage consists also of a non-inverting amplifier (C), here the overall gain is set digitally. Two comparators connected to the output of the postamp generate a (digital) signal indicating if the output signal is in saturation (e.g. too high or too low). If this occurs, the reference ground of the postamps’ first stage is changed to reduce this DC-offset accordingly. The amplified respiration signal is finally AD converted and the digitized signal can be read out by the on-chip DSP. 3.5. DSP and TCU A 16-bit high-performance fixed-point DSP and 17 Kb of memory are embedded in the SoC, enabling a wide range of on-
Fig. 5. Respiration measurement circuit.
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Fig. 6. Offset control circuit.
chip digital signal processing capabilities. This includes basic filtering like a 50 Hz notch filter and 0.1 Hz high pass filter for ECG signals, but also more advanced functionality. In an ECG application for instance, this could include ECG feature extraction, heart rate variability assessment, or signal compression for long term monitors. The DSP also governs other blocks through the TCU. The TCU contains read/write registers for the operational parameters (e.g. AFE’s gain and cut-off frequency, selective power down of unneeded parts) and read-only registers to store the digitized analog output. The TCU also generates the clock signals for the -ADCs. 3.6. Signal generator A signal generator capable of generating precise sine waves, based on the principle of digital resonators is used [15]. This has several benefits such as easy integration (mainly digital and no DAC needed), stability, and programmability. By changing the clock frequency and the initial values of delay elements in the digital resonator, the amplitude and frequency of the resulting output can be set. Peak-to-peak amplitudes ranging from 25 mV to 1.5 V and frequencies ranging from 50 to 40 kHz can be obtained. The lowest output amplitude is needed to measure the highest gain factor whereas the high output amplitude is needed for common mode gain measurement. Low frequency signals are required to do characterization in the bands of interest. The 40 kHz is needed for the respiration measurement. The output of the digital block is a single-bit digital signal. The sigma-delta modulation within the loop shapes the noise to higher frequencies. This digital signal is fed to a low pass filter, the output of which is the desired analog signal.
3.7. BIST & autocalibration Each time the IC is powered on, a test and calibration routine is run. The on-chip signal generator is used to generate known stimuli, which are applied to the AFE. The output is measured and the DSP can calculate key features like gain, CMRR, output noise and crosstalk. The BIST routine compares them to the specifications. For the autocalibration routine, the test signal is first applied to in2 and in1 is shorted to ref (see Fig. 2). Since in1 and ref are at the same potential, no current is flowing through the lower resistors. The output is only determined by the upper resistors. The upper tuneable resistor can be used to accurately set the gain factor to the desired value. Once that is done, in1 is shorted to in2 so that the testsignal is applied to the circuit as a common mode signal. The lower tuneable resistor can now be used to precisely match the bottom resistors to the upper one in order to maximize the CMRR. 4. Prototype A first prototype of the SoC with three channels was manufactured in a 0.35 m 3.3 V CMOS technology from Austria-Microsystems. Fig. 7 shows the photograph of the die. The die size is 6800 × 5500 m. 4.1. Power consumption and noise performance The power consumption of the different blocks is listed in Table 2. For the AFE two power consumptions are listed, one for a biasing current of 2 A for the amplifiers and one for a biasing current of 20 A. Table 3 lists the total input referred noise voltage for the two biasing currents in different frequency
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Fig. 8. Respiration measured on a real patient.
Fig. 7. Chip photograph. Fig. 9. DC-offset control. Table 2 Power consumption Digital
DSP TCU 3×UART
4.2. Respiration Dynamic power consumption (mW/MHz) Idle
Full load
0.62 ∼0 ∼0
1.77 0.19 1.47
Analog
Power consumption (mW)
ADC @1 KHz ADC @50 KHz AFE (Ibias = 1 A) AFE (Ibias = 20 A)
0.24 mW 3 mW 4 mW/channel 10 mW/channel
bands. A biasing current of 2 A is appropriate for ECG applications. For EEG/EMG and EP measurements a higher biasing current is needed in order to satisfy the noise requirement. For ECG a low sampling rate, consuming minimal power, can be used due to low frequency content, for EMG/EP a higher sampling rate, and thus power consumption, is needed. The digital parts can run at different clock frequencies as well depending on the required processing power and signal bandwidth. Therefore, the dynamic power consumption is expressed as mW/MHz. There is a total static power consumption of 0.6 mW. The other digital blocks can be switched off when they are not used.
The respiration circuit was tested with an artificial body impedance (Zbody ) of 300 and a cable impedance of 1 k. Respiration was simulated by varying Zbody . A change of 1 in Zbody resulted in a 12.5 mV change in output voltage. Breathing typically causes an impedance change in the range of 0.1–5 . Fig. 8 shows the output of the configurable postamplifier as measured on a patient (male, 70 kg, 30 yrs). The DC-offset control was tested with a slowly increasing carrier signal amplitude reflecting changes in the impedances of the thorax and contact between thorax and electrode. For example, the change can be caused by sweating of the patient. Fig. 9 shows the output of the configurable postamplifier (with gain 100 in this case). The amplitude of the 40 kHz test signal (without a respiration signal) is slowly increased which in turn increases the dc-offset at the input of the postamp. Every 4 mV change of DC-offset at the postamp’s input, the control-circuit changes the gain of
Table 3 Total input referred noise voltage Band (application)
Ib = 2 A (Vpp )
Ib = 20 A (Vpp )
Spec (Vpp )
.05–250 Hz (ECG) .5–70 Hz (EEG) .1–3 KHz (EP) .01–5 KHz (EMG)
1.47 0.89 3.55 4.32
0.96 0.61 1.78 2.08
<2.5 <0.75 <2.2 <3
Fig. 10. Spectrum of digital oscillator set to output at 4.95 kHz.
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Fig. 11. Measured gain and CMRR values for different values of the tuneable resistors. Gain of preamplifier was set to 20 (upper plots) and 80 (lower plots).
amplifier B in Fig. 6 and setting therefore a new DC-offset level (in Fig. 9 the postamp’s output DC-level drops to lower level at that point, preventing a saturation of the postamp). The ripple on the test signal is an artefact from the measurement set-up. 4.3. Signal generator The output spectrum of the digital oscillator is shown in Fig. 10. The noise shaping due to the sigma-delta modulation is clearly visible in the upper plot covering a large frequency span. The lower plot shows a close-up of the spectrum around the fundamental tone located at 4.95 kHz. The second harmonic is more than 60 dB below the signal. Similar results were measured for different output frequencies. Furthermore, no significant drift in amplitude or frequency over time could be noticed making these sine waves very suited to do calibration and BIST. 4.4. Autocalibration The on-chip oscillator was used to generate a sine wave with a frequency of 230 Hz. This signal was first applied to the AFE as a differential signal as explained in the previous section. The RMS value over 50 periods of the fundamental tone was calculated with the DSP. This value was then divided by the RMS value of the applied signal to obtain the gain factor. This was repeated for all 16 different values of the upper tuneable resistor (the one used for calibrating gain – see Fig. 2). The resulting measured
gain factors are displayed in the left plots of Fig. 11. In both cases (preamplifier set to gain 20 and gain 80) it was possible to find a gain factor within 0.5% of the desired value. The same procedure was repeated but this time the signal was applied as commonmode and the lower (CMRR) tuneable resistor was used while the upper one was fixed with the optimal value. The results are shown in the right plots of Fig. 11. Again it was possible to obtain the required specifications in both cases. Similar results were measured with different dies. 5. Conclusions and future work A flexible SoC for biomedical signal acquisition and on-chip processing is presented. The SoC employs a programmable AFE, BIST, autocalibration, -ADCs, respiration measurement circuitry and on-chip DSP. Furthermore, various power-saving techniques are employed. The result is a multipurpose, reliable and yet low-cost single-chip solution. A prototype was manufactured with three channels. This IC will be used in a proof-of-concept application. It will be a 24/7 battery-powered long-term ECG-monitoring device. The DSP running at 1 MHz, the TCU at 256 KHz, an ADC sample frequency of 500 Hz and a biasing current of 2 A for the AFE would result in a total current consumption of less than 5 mA. An additional 5 mA is needed for data storage. Two standard AA batteries with a capacity of 2000 mAh are sufficient to power the device for one week 24/7. The final board size will be about 10 × 5 cm, which can be further reduced by using a much smaller BGA package instead of the current PGA package.
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Acknowledgements This project is funded by the European Commission, DG RTD, Contract No. COOP-CT-2004-508291-M3C. References [1] Health at a Glance: OECD Indicators 2005. ISBN 92-64-01262-1. [2] I. Korhonen, J. P¨arkka, M. van Gils, Health monitoring in the home of the future, IEEE Eng. Med. Biol. Mag. (May/June 2003). [3] U. Edstrom, J. Skonevik, T. Backlund, J.S. Karlsson, A flexible measurement system for physiological signals in mobile health care, Engineering in Medicine and Biology Society 27th Annual International Conference, 2005. Pages: 2161–2162. [4] E. Jovanov, P. Gelabert, R. Adhami, P. Smith, Real time portable heart monitoring using low power DSP, in: International Conference on Signal Processing Applications and Technology, Dallas, Texas, October 2000. [5] R. Martins, S. Selberherr, F.A. Vaz, A CMOS IC for portable EEG acquisition systems, IEEE Trans. Instrum. Meas. 47 (no. 5) (Oct. 1998). [6] K.A. Ng, P.K. Chan, A CMOS analog front-end IC for portable EEG/ECG monitoring applications, IEEE Trans. Circ. Syst. 52 (no. 11) (Nov. 2005) 2335–2347. [7] T. Desel, T. Reichel, S. Rudischhauser, H. Hauer, A CMOS nine channel ECG measurement IC, Proc. 2nd IEEE Int. Conf. ASIC (Oct. 1996) 115–118. [8] B. Fuchs, S. Vogel, D. Schroeder, Universal application-specific integrated circuit for bioelectric data acquisition, Medical Engineering and Physics, no. 24, pp. 695–701. Elsevier Science Ltd., 2002. [9] S. L. Toral, J.M. Quero, M.E. Perez, L.G. Franquelo, A microprocessor based system for ECG telemedicine and telecare, IEEE Inter. Symp. on Circ. Syst., Syndey, Australia, May 2001, vol. 4, pp. 526–529. [10] B.R. Hayes-Gill, A.C. Cardoso, N. Meinke, J.A. Crowe, B. Francon, A. Harrison, A generic ASIC and DSP based ambulatory electrophysiological recorder, Data Logging of Physiological Signals, IEE Colloquium on, Vol., Iss., 23 Nov 1995. Pages: 9/1–9/3. [11] C. Bronskowski, D. Schroeder, A programmable analog front end for the acquisition of biomedical signals, in: ProRISC2004 Workshop, Veldhoven, 2004, pp. 474–477. [12] Alexander Mora-Sanchez, Dietmar Schroeder, Wolfgang H. Krautschneider, Sigma-delta modulators of 2nd- and 3rd-order with a single operational transconductance amplifier for low-power analogue-to-digital conversion, in: ProRisc2005 Workshop, 2005, pp. 259–262. [13] A. Mora-Sanchez, D. Schroeder, Low-power decimation filter in a 0. 35 m CMOS technology for a multi-channel biomedical data acquisition chip, in: XI Iberchip Workshop, Salvador do Bahia, Brasil, 2005, pp. 199–202. [14] J.D. Bronzino, et al., The Biomedical Engineering Handbook, CRC Press, 2000. [15] A. Lu, G. Roberts, A high-quality analog oscillator using oversampling D/A conversion techniques, IEEE Trans. Circ. Syst. 41 (no. 7) (July 1994) 437–444.
Biographies Nick Van Helleputte was born in Leuven, Belgium, in 1981. In 2004, he received the degree of M.S. in Electrical Engineering from the Katholieke Universiteit Leuven, Belgium. The subject of his MS thesis was on the design of an integrated analog front-end for foetal ECG monitoring. From 2004 up to now he is a research assistant at the MICAS laboratories of the Katholieke Universiteit Leuven. His current research activities include circuit design for biomedical applications and low-power analog radio design.
Jakob M. Tomasik was born in Gliwice, Poland, in 1975. In 2004, he received the diploma degree in computer science and engineering from the Hamburg University of Technology, Germany. From 2004 up to now he is a research assistant at the Institute of Nanoelectronics of the Hamburg University of Technology. Wjatscheslaw Galjan was born in Omsk, Russia, in 1976. In 2004, he received the diploma degree in Electrical Engineering from the Hamburg University of Technology, Germany. From 2004 up to now he is a research assistant at the Institute of Nanoelectronics of the Hamburg University of Technology. Alexander Mora-Sanchez was born in San Jose, Costa Rica, in 1975. He received both his Bachelor’s and Licentiate degrees in Electrical Engineering from the University of Costa Rica in 1997 and 1999, respectively. In 2002, he received the Master’s degree in Microelectronics and Microsystems from the Technical University of Hamburg-Harburg (TUHH), Hamburg, Germany. From 2002 up to now he is a research assistant with the Institute of Nanoelectronics of the TUHH, where he conducted research in the area of low-power mixed-signal ASICs/SoCs for biomedical applications. His research interest is in low-power digital design, low-power small-area sigma-delta A/D-modulators and SC-circuit design. He will finish his Ph.D. studies in 2006. Dietmar Schroeder received the Dipl.-Ing. and Dr.-Ing. degrees in Electrical Engineering from the Technical University of Braunschweig, Germany, in 1978 and 1984, respectively. From 1983 to 1985, he was an advisor for Electrical Engineering at the Computer Center, Technical University of Hamburg-Harburg, Germany. Since 1985, he has been Chief Engineer at the Department of Microelectronics. In 1994, he attained the academic degree of habilitation from TU Hamburg-Harburg, and is now lecturer for Semiconductor Electronics at this university. He has authored or co-authored 60 papers and one book. His research interests include low-power analog/digital converters, efficient signal processing based on information theory, mixed-signal integrated circuits for sensor interfaces, integrated circuits for medical technology, and modeling of charge transport in semiconductor devices. Wolfgang H. Krautschneider studied Electronics Engineering at Berlin University of Technology, Germany. After completion of his MS and Ph.D. degrees, he managed an industrial and academic joint project for automotive electronics. Then, he held an assignment as visiting scientist at the Central Research Laboratories of IBM in Yorktown Heights, USA. After this, he worked in the field of Megabit memory chips, first at the Siemens Corporate Research Center in Munich, Germany, and then in a joint DRAM development project of IBM and Siemens AG at the IBM site in Essex Junction, VT, USA. Next station of his professional life was the design of devices and circuits for Gigabit memories at the Corporate Research Laboratories of Siemens AG in Munich, Germany. In 1997, he received the Siemens Innovation Award for his invention of a new type of memory cell. In the same year, he completed his habilitation about “Solid-State Electronics” at the Berlin University of Technology. In 1999, he was appointed a full professor at Hamburg University of Technology, where he heads the institute of nanoelectronics. From 2002 to 2004, he served as Deputy Dean of the Faculty for Electrical Engineering of Hamburg University of Technology, and since 2004 as Dean of this faculty. He has authored and co-authored more than 75 scientific papers and is the inventor and co-inventor of more than 35 issued patents in the field of electronic circuits, memory cells and advanced semiconductor devices. Robert (Bob) Puers was born in Antwerpen, Belgium, 1953, and grew up in the Ghent. He received his B.S. degree in Electrical Engineering in Ghent in 1974, and his M.S. degree at the Katholieke Universiteit Leuven in 1977, where he obtained his Ph.D. in 1986. From 1980 he was employed as a Research Assistant at the Laboratory ESAT at K. U. Leuven. In 1986, he became Director (NFWO) of the clean room facilities for silicon and hybrid circuit technology at the ESAT-MICAS laboratories of the same university. His research interests are in silicon sensors, MEMS and packaging techniques, for biomedical implantable total systems as well as for industrial devices. Robert Puers is professor at the Katholieke Universiteit Leuven, Belgium, since 1991.