A fringing-capacitance model for deep-submicron MOSFET with high-k gate dielectric

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Microelectronics Reliability 48 (2008) 693–697 www.elsevier.com/locate/microrel

A fringing-capacitance model for deep-submicron MOSFET with high-k gate dielectric F. Ji a,b, J.P. Xu a,*, P.T. Lai c,*, J.G. Guan d a

Department of Electronic Science and Technology, Huazhong University of Science and Technology, Wuhan 430074, People’s Republic of China b Wuhan Institute of Technology, Wuhan 430074, People’s Republic of China c Department of Electrical and Electronic Engineering, The University of Hong Kong, Pokfulam Road, Hong Kong d State Key Laboratory of Advanced Technology for Materials Synthesis and Process, Wuhan University of Technology, Wuhan 430070, People’s Republic of China Received 23 June 2007; received in revised form 1 December 2007 Available online 10 March 2008

Abstract An analytical model of fringing capacitances for deep-submicron MOSFET with high-k gate dielectric, including gate dielectric fringing-capacitance and gate electrode fringing-capacitance, is obtained by the conformal-mapping transformation method. It is demonstrated that the fringing-capacitance effect is enhanced as the thickness of gate electrode or the dielectric constant of either gate dielectric or sidewall spacer increases. Moreover, the influence of fringing-capacitance on threshold voltage is demonstrated. Ó 2008 Elsevier Ltd. All rights reserved.

1. Introduction Increased gate leakage is one major limiting factor on aggressive scaling of gate dielectric for deep-submicron CMOS technology [1]. Search has been on for a suitable high-permittivity (high-k) gate dielectric, which can replace SiO2 [2]. However, this gives rise to significant fringingcapacitance, consisting of gate dielectric fringing-capacitance between gate electrode bottom and source/drain surface and gate electrode fringing-capacitance between gate electrode edge and source/drain surface. Both affect the electrical characteristics and degrade the short-channel performance of MOSFET because they increase the fringing field from the gate to the source/drain regions [3,4]. Recently, conformal-mapping transformation was employed to model the fringing parasitic capacitance [5– 7] and the fringing-capacitance was derived through the conformal-mapping of potential space [5]. In this work, the fringing capacitances are directly derived by the confor*

Corresponding authors. E-mail addresses: [email protected] (J.P. Xu), [email protected] (P.T. Lai). 0026-2714/$ - see front matter Ó 2008 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2008.01.007

mal-mapping method. The fringing-induced barrier lowing (FIBL) is demonstrated through the effect of charges induced by the fringing capacitances. Calculation results show that the fringing capacitances increase with the k value of gate dielectric or thickness of gate electrode, and thus exert larger influence on the performance of deep-submicron MOSFET. For example, the fringing capacitances can impact the threshold voltage of the device. In this connection, a threshold voltage model including the fringingcapacitance effect is derived and the influence of sidewall spacer on threshold voltage is discussed.

2. Models of fringing-capacitance and surface potential The fringing capacitances of a high-k gate dielectric MOSFET are shown in Fig. 1, where Cof is gate dielectric fringing-capacitance; Cgf is gate electrode fringing-capacitance; Cox is gate dielectric capacitance between the gate and channel; Tox and Tg are physical thickness of the gate dielectric and gate electrode, respectively; L and La are channel length and distance between source/drain electrode and gate dielectric (i.e., length of sidewall spacer), respectively;

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F. Ji et al. / Microelectronics Reliability 48 (2008) 693–697

Cgf electrode

Cof O La S y

where k1 is dielectric constant of the sidewall spacer. Substituting the points a(0, 0), b(La, 0), c(0, Tox) and d(0, Tox + Tg) 0 0 in the x  y coordinate system into Eq. (2), the corresponding points in the n  g coordinate system can be       T þT expressed as: a(0,0), b cosh1 oxT ox g ; 0 ; c 0; p2 and     T þT d cosh1 oxT ox g ; p2 . Substituting these points into Eq.

Cgf

Tg

Cof

Tox x L

electrode

La D

(4), the gate electrode fringing-capacitance can be obtained:

t

Fig. 1. Schematic diagram of fringing capacitances for high-k gate dielectric MOSFET.

t is width of overlap region between source/drain and gate electrode; O is the origin of the (x, y) coordinate system. In this section, the two fringing capacitances are derived in part A and part B, respectively. 2.1. Gate electrode fringing-capacitance The gate electrode fringing-capacitance with field lines is schematically shown in Fig. 2a, from which it is difficult to directly get an expression for the gate electrode fringingcapacitance. Therefore, the method of conformal-mapping transformation is employed to map the original structure to an equivalent parallel-plate system. The mapping functions are given as follows: n þ jg ¼ F ðX 0 þ jY 0 Þ

ð1Þ

and  0 x ¼ D cos g sinh n y 0 ¼ T ox sin g cosh n

ð2Þ

with D¼

h

La

sinh cosh1



T ox þT g T ox

i

ð3Þ

The structure after mapping is shown in Fig. 2b, and its capacitance can be easily written as C gf ¼ k 1

ndb  nca gcd  gab

ð4Þ

Fig. 2. Field lines of gate fringing (a) before conformal-mapping and (b) after conformal-mapping (the shaded region is the gate electrode, sitting on the gate dielectric).

C gf ¼ k 1

  2bW T ox þ T g cosh1 p T ox

ð5Þ

where W is channel width of MOSFET; b is a form factor added to give better agreement with numerical simulation. 2.2. Gate dielectric fringing-capacitance The gate dielectric fringing-capacitance Cof in Fig. 1 is divided into two parts by the interface between the gate dielectric and spacer: one in the gate dielectric (C1) and another in the spacer (C2), connected in series as shown in Fig. 3. Thus, the total gate dielectric fringing-capacitance can be written as C of ¼

C1C2 C1 þ C2

ð6Þ

Similarly, conformal-mapping is used to derive the expres0 sions of C1 and C2. For C1, the potential between y and 0 0 0 0 0 y + dy is V(y ) in the X  Y coordinate system, as shown in Fig. 4a. For simplification, the field lines between the left/right edges of the gate dielectric and surface of source/drain are considered to be circular, as shown in Fig. 4a. As a result, the structure can be mapped to an equivalent parallel-plate system in Fig. 4b by transforming 0 0 the X  Y coordinate system to the P  U coordinate system, with mapping functions: P þ jU ¼ F ðX 0 þ jY 0 Þ

ð7Þ

and 

x0 ¼ ep cosðuÞ y 0 ¼ ep sinðuÞ

ð8Þ

Fig. 3. Decomposition of gate dielectric fringing-capacitance into C1 and C2 (the shaded region is the gate electrode, sitting on the gate dielectric).

F. Ji et al. / Microelectronics Reliability 48 (2008) 693–697

a

695

0.7

0.6

Tg = 65 nm k1 = 3.9 W = 1μm β = 0.72

Fig. 4. Electric field lines of C1 (a) before conformal-mapping, and (b) after conformal-mapping.

Cgf (10

-16

Farads)

This model Simulated

In the P  U coordinate system, the capacitance per unit length can be easily obtained: P jf  P ig U ij  U gf

ð9Þ 0

0.4 2

b

6

8

10

0.24

This model Simulated

0

0.20

k1 = 3.9 EOT = 2 nm W = 1 μm γ = 0.27

0.16

0

0

0

Substituting the points i(0, y ) and j(0, y + dy ) into Eq. (8) gives P jf  P ig ¼ lnðy 0 þ dy 0 Þ  ln y 0

Cof (10

-16

Substituting the points g(y , 0) and i(0, y ) into Eq. (8), Uij and Ugf can be found:  U ij ¼ p2 ð10Þ U gf ¼ 0

4

Tox (nm)

Farads)

C 1 ðpÞ ¼ k 1

0.5

0.12

ð11Þ 0.08

Putting Eqs. (10) and (11) into Eq. (9), C1 can be derived as 2k 1 1 0 dC 1 ðy Þ ¼ dy p y0 0

0

ð12Þ

2k ox 1 dy 0 p T ox  y 0

40

60

80

Gate dielectric constant (kox)

Fig. 5. Comparison between the model and numerical simulation. (a) and (b) are the dependences of gate electrode fringing-capacitance (Cgf) and gate dielectric fringing-capacitance (Cof) on Tox and kox, respectively.

Similarly, C2 can be derived as dC 2 ðy 0 Þ ¼

20

ð13Þ

where kox is dielectric constant of gate dielectric. Substituting Eqs. (12) and (13) into Eq. (6), the gate dielectric fringing-capacitance can be found: Z T ox dC 1 ðy 0 ÞdC 2 ðy 0 Þ ð14Þ C of ¼ dC 1 ðy 0 Þ þ dC 2 ðy 0 Þ 0 Since the field lines are assumed to be circular, the integral in (14) is multiplied by a form factor c to give more accurate Cof. Thus, integrating results in   2cWk ox k 1 k ox ln C of ¼ ð15Þ pðk ox  k 1 Þ k1 3. Results and discussion Results calculated by the proposed model and numerical device simulator (MEDICI) are compared in Fig. 5, and good agreements are obtained, indicating the correctness of the model. As shown in Fig. 5a, Cgf decreases with

increasing Tox due to increased distance between the two plates of Cgf (i.e. distance between a and c in Fig. 2a). Dependence of gate dielectric fringing-capacitance on gate dielectric constant is shown in Fig. 5b. For a given equivalent oxide thickness (EOT), the larger the kox, the larger is the physical thickness of gate dielectric, which induces more field lines from the bottom of gate electrode to the surface of source/drain via the gate dielectric fringing [3], resulting in an increase of gate dielectric fringingcapacitance. Fig. 6a shows the variation of the gate electrode fringing-capacitance with gate thickness. For a given EOT and kox, the gate electrode fringing-capacitance increases with Tg. This is because the thicker the gate electrode, the more are the field lines emitted from its right/left edges. Thus, more field lines terminate at the surface of the source/drain regions, leading to an increase of the gate electrode fringing-capacitance. For a given gate dielectric constant, the gate dielectric fringing-capacitance increases with the dielectric constant of the sidewall spacer. This

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F. Ji et al. / Microelectronics Reliability 48 (2008) 693–697

a k1 = 3.9 k1 = 10 EOT = 2 nm kox = 20

0.8

Cgf (10

-16

Farads)

1.2

0.4

20

40

60

80

100

120

where VG = Vg  Vfb (Vg is gate voltage; Vfb is flat-band voltage). These charges produce an electric field in the channel, and the relevant surface potential is [8] 2 qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2 2 ðx þ La Þ þ W4 þ W2 rof 6 uof ðx; 0Þ ¼ 4ðx þ La Þ ln qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2 8pk si ðx þ La Þ2 þ W4  W2 qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2 ðx þ La Þ2 þ W4 þ W2 x ln qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2 2 ðx þ La Þ þ W4  W2 rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi qffiffiffiffiffiffiffiffiffiffiffiffiffiffi qffiffiffiffiffiffiffiffiffiffiffiffiffiffi3 2 2 x2 þ W4 þ La þ x2 þ L2a þ 2La x2 þ W4 7 7 qffiffiffiffiffiffiffiffiffiffiffiffiffiffi þW ln 5 2 x2 þ W4 þ x

Tg (nm)

ð17Þ

b

For the same reason, the surface potential induced by Cgf can be found 2 qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2 2 ðx þ La Þ þ W4 þ W2 rgf 6 ugf ðx; 0Þ ¼ 4ðx þ La Þ ln qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2 2 8pk si ðx þ La Þ þ W4  W2 qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2 2 ðx þ La Þ þ W4 þ W2 x ln qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2 2 ðx þ La Þ þ W4  W2 rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi qffiffiffiffiffiffiffiffiffiffiffiffiffiffi qffiffiffiffiffiffiffiffiffiffiffiffiffiffi3 2 2 W2 2 2 x þ 4 þ La þ x þ La þ 2La x2 þ W4 7 7 qffiffiffiffiffiffiffiffiffiffiffiffiffiffi þW ln 5 W2 2 x þ 4 þx

kox = 20 kox = 50 0.6

Cof (10

-16

Farads)

0.8

0.4

0.2

0

20

40

60

k1

ð18Þ

Fig. 6. Influences of (a) gate electrode thickness, and (b) k1 of sidewall spacer on the fringing capacitances Cgf and Cof, respectively.

where rgf = Cgf(VG  Vbi). The electric potential of shortchannel MOSFET without the influence of the fringing fields was derived to be [9]:

means that the field lines from the bottom of the gate electrode can easily go through the interface between the gate dielectric and sidewall spacer. Furthermore, from Fig. 6, smaller k1 can reduce Cgf and Cof. Therefore, low-k1 spacer is helpful for suppressing the fringing capacitances and thus improving the behaviors of small-sized high-k gate dielectric MOSFET. It has been reported that degradation in short-channel performance associated with high-k dielectrics is caused by the fringing fields from the gate to the source/drain regions, because the fringing fields can affect the electric potential in the channel, thereby weakening the gate control [3]. When Vds is small, Vd ffi Vs = Vbi (Vs and Vd are the source and drain voltages; Vbi is built-in potential of the source/substrate and drain/substrate junctions; Vds is the potential difference between drain and source). Thus, the induced charge density at the surface of source or drain region by the fringing field lines of Cof is

us ðx; yÞ ¼ u0 ðyÞ þ ðV bi þ V ds Þ

rof ¼ C of ðV G  V bi Þ=WLa

ð16Þ

sinhðx=lÞ sinhðL=lÞ sinh½ðL  xÞ=l þ V bi sinhðL=lÞ

ð19Þ

where u0(y) the electric potential of long-channel MOSffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ffi pis FET; l ¼ k si y d =C ox is a characteristic length describing the short-channel effect; yd is width of the depletion region in the substrate [9,10]. Considering the influence of the fringing capacitances, the threshold voltage Vth is defined as the gate voltage when the total surface potential at the location of minimum surface potential (x0) us ðx0 Þ þ uof ðx0 Þ þ ugf ðx0 Þ ¼ 2/B

ð20Þ

where /B ¼ kBqT ln NnAi is the Fermi potential of the substrate. When Vds is small, x0  L/2. Therefore, the threshold voltage can be found by Eqs. (19) and (20) V th ¼ V th0 

2ðV bi  2/B þ uof ðx0 Þ þ ugf ðx0 ÞÞ 2 coshðL=2lÞ  2

ð21Þ

F. Ji et al. / Microelectronics Reliability 48 (2008) 693–697

itances on threshold voltage of MOSFET with high-k gate dielectric and different sidewall spacer is described. Low dielectric constant sidewall spacer can alleviate degradation of threshold voltage.

0

k1 = 3.9 k1 = 10 k1 = 20 k1 = 30

Vroll-off (mV)

-40

697

Acknowledgements k = 3.9 k = 10

0.12

C /C

-80

EOT = 2 nm kox = 50 17

-120

NA = 5x10 cm La = L/2

This work is financially supported by the National Natural Science Foundation of China (NSFC, Grant No. 60376019) and Open Foundation of State Key Laboratory of Advanced Technology for Materials Synthesis and Processing (Project No. WUT2006M02).

0.08

0.04

-3 40

80

120

160

200

Channel length (nm)

100

1000

References

Channel length (nm)

Fig. 7. Influence of k1 value of sidewall spacer on the threshold voltage of MOSFET. The insert illustrates effect of k1 value on Cf/Cox ratio.

where Vth0 represents the threshold voltage of long-channel MOSFET. The threshold voltage roll-off (Vroll  off = Vth  Vth0) for different k values of sidewall spacer is shown in Fig. 7. The threshold voltage roll-off increases with k1 in the short-channel region of <100 nm because the fringing-induced barrier lowing (FIBL) effect is enhanced for large k1 values, resulting in an increase of Cf/ Cox ratio (Cf = Cgf + Cof) as shown in the insert of Fig. 7. Therefore, low-k1 sidewall spacer can alleviate the FIBL effect, especially for nano MOSFET. 4. Summary The gate dielectric fringing-capacitance (Cof) and gate electrode fringing-capacitance (Cgf) of deep-submicron MOSFET with high-k gate dielectric are derived using the conformal-mapping transformation method. Device parameters impacting the two capacitances are discussed in detail. Calculation results show that Cof increases with the permittivity of gate dielectric, while Cgf increases/ decreases as thickness of gate electrode/gate dielectric increases. Furthermore, the influence of the fringing capac-

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