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INTEGRATION, the VLSI journal 24 (1997) 147 158
A graph theoretic approach to feed-through pin assignment Y.-P. Chert*, D.F. W o n g Department of Computer Sciences, University of Texas at Austin, Austin, Texas 78712, USA
Abstract
We study in this paper the feed-through pin assignment problem for cell-based design that assigns global nets to feedthrough cells or implicit feed-through ports. On a single row, for a restricted permutation of global nets, we develop a graph theoretic approach for optimally minimizing the density of the channel above (below) the row subject to the bound on the density of the channel below (above) the row. Based on this technique, an approach for iteratively improving multiple row feed-through pin assignment can be developed. We show that our approach is also applicable to the design style in which there is an over-the-cell feed-through layer.
Keywords. Graphy theory: Feed-through pin; Routing; Standard cell
1. Introduction Feed-through pin assignment is a necessary process in standard-cell layout. After the global route for each net is determined by a global router, on each cell row we need to assign feed-through pins to all the nets that cross the row (we denote those nets as feed-through nets). Channel routing can only be performed after feed-through pin assignment is done. Since channel density is an accurate estimation of the number of routing tracks required for each channel, the main objective of feedthrough assignment is to minimize the total density of all channels. In this paper, we will pursue this objective. Recently, there are a few good research works on feed-through pin-assignment problem [I-3]. All these approaches assume the feed-through pins reserved for feed-through nets are at their final positions, In other words, they are fixed and cannot be changed. We propose an approach for improving single-row feed-through pin assignment which has the advantage that the position of feedthrough pins need not be fixed. In this paper, we assume that there are two types of feed-through pins: implicit feed-through pins in ordinary cells and feed-through pins in a type of special cells called feed-through cells. In addition to movable feed-through pins, our approach has the following features. First, all cells on each row can be shifted as long as the row length does not exceed the given maximum length. Second, there can be zero or more feed-through cells (if necessary) between *Correspondence address: Avant! Corporation, 46871 Bayside Parkway, Fremont, CA 94538, + 1 510 413 8995: fax: + 1 510 4137705; e-mail:
[email protected]. 0167-9260/97/$17.00 @ 1997 Elsevier Science B.V. All rights reserved PH S 01 6 7 - 9 2 6 0 ( 9 7 ) 0 0 0 3 0 - 8
USA. Tel.:
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each pair of adjacent ordinary cells. Third, the number of required feed-through pins on one row may be less than the total number of feed-through nets on the same row due to merging of equivalent signals. All of these features will be described in detail. We model the problem of single-row feed-through assignment as a graph problem. We construct a directed acyclic graph, such that each vertex corresponds to a feed-through cell, an implicit feedthrough pin, or an ordinary cell; and each edge corresponds to a segment of the cell row. The edge weights are ordered-pairs which store the density of the sub-channel above and below the segment. We develop an efficient optimal single-row feed-through assignment improvement algorithm under the condition that the feed-through nets are grouped as interchangeable pairs. An approximate approach for improving multiple-row feed-through pin assignment can be derived by iteratively performing the single-row algorithm. The remainder of this paper is organized as follows. In Section 2, the problem formulation is given and a single-row feed-through assignment algorithm is proposed. In Section 3, we propose the algorithm for multiple-row feed-through pin assignment based on the single-row algorithm. In Section 4, we show that the same problem for a different design technology - over-the-cell feedthrough layer can be solved as a special case of our approach. We give the conclusions in Section 5.
2. Single-row algorithm There are ordinary cells and feed-through cells on each cell row. Some ordinary cells contain implicit feed-through pins. Many nets connect terminals on several cell rows. If the route of a net crosses a cell row and this net does not have any terminal near the crossing positions, then we need to assign feed-through pin to this net. A global router approximately determines the positions of feed-through pins and the initial assignment of feed-through pins to feed-through nets. However, the assignment often is not good enough due to the difficulty of the global routing problem and the fact that global routers use heuristic approaches. Therefore, we propose an optimal single-row feed-through pin-assignment algorithm serving as an enhancement to the global routing results. 2.1. Problem formulation
The formulation of the general single-row feed-through pin-assignment problem is as follows. Given the maximum row length L, the fixed-order set of ordinary cells CI, C2,..., Cm on this row R, where cell Ci contains f(~>0) implicit feed-through ports, and the set of feed-through nets N~,N2,... ,Nn that require feed-through pins on this cell row, determine the position of all nets NI,N2 .... ,N,, such that the density of the channel above (or below) the row R is minimized, while the density of the channel below (or above) is smaller than a given constant, usually the original density. The new row length of R should not exceed L. Each N,. is either between two adjacent cells Cj and Cj+1 (we introduce two pseudo-cells Co and Cm+l to represent the left- and right-end of the cell row), or occupies an implicit feed-through port in a cell CJ. The former case implies that a feed-through cell is required between cell Cj and Cj+l. Fig. 1 illustrates the general single-row feed-through pin-assignment problem. A vertical dotted line in an ordinary cell represent an implicit feed-through port. Each vertical segment on the right side represents a net that requires feed-through position on the middle row i. Their ordering is not fixed. In (b), an assignment is shown for the problem in (a). Net 3 uses feed-through cell, while
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net 4 and net 7 use implicit feed-through ports. The positions of the ordinary cells are shifted but their order is preserved. Note that the ordering of net 3 and net 4 is changed. We intend to improve upon the result given by a global router, which approximately determines the positions and ordering of the feed-through nets. When we perform feed-through pin assignment, we can assume that we start with a good initial solution. Therefore, we consider the following feed-through net ordering. Definition 1. Given a sequence of feed-through nets N1, N2 . . . . . N,, it is even interchangeable if each N2i+l(i 1>0) can be swapped with N2i+2. It is odd interchangeable if each N2i(i >~ 1 ) can be swapped with N2i+j. A fully even-swapped (odd-swapped) sequence is the one obtained by swapping all eligible pairs of nets of an even (odd) interchangeable net sequence. A partially even-swapped (odd-swapped) sequence is the one obtained by performing zero or more swaps of an even (odd) interchangeable net sequence. For example, if (Nj, Nz, N3, N4, Ns) is a feed-through net sequence, the fully even-swapped sequence is (N2, NI, N4, N3, Ns), and the fully odd-swapped sequence is IN1, N3, N2, Ns, N4). The sequence (NI, N2, N4, N3, N6) is a partially even-swapped sequence. Note that the original sequence and the fully swapped sequence are special cases of partially swapped sequences. The problem that we can optimally solve is the general single-row problem with one additional constraint: the sequence of feed-through nets N~'s is even (or odd) interchangeable. There may exist identical nets in the feed-through net sequence NI, N2, ..., N,. If some identical nets are adjacent in the sequence after swapping, they may be merged as one. In our previous
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Fig. 2. An even adjacency graph.
Fig. 3. An odd adjacency graph.
example, if N2 and Ns are identical, in the fully odd-swapped sequence, they become adjacent and therefore may be merged. The reduced sequence is (NL,N3,N?,N4}. We start with the construction of the adjacency graph, which is used to determine whether two consecutive feed-through pins on a cell row from left to right can be assigned to a given pair of feed-through nets.
2.2. Adjacency graph Given the even (odd) interchangeable feed-through nets Ni's (1 <~i<~n), we construct the even (odd) adjacen O' graph as follows. For each net N/, we create two vertices labeled Ni and Ni', which corresponds to Ni after being swapped. In addition, there is a source s and sink z. For any two vertices v~ and vj excluding s and z, there exists an edge e oriented from v~ to ~/ if the two corresponding nets are consecutive from left to right in a partially even (odd) swapped sequence. The weight of e is 0 if the two nets are identical, and it is 1 otherwise. Then we connect s to any v~ having zero in-degree, and assign edge weight 1. Similarly, we connect any vertex having zero out-degree to z, and assign edge weight 1. For example, given nets N~,N2,...,NT, where Ni and N3 are identical, and N4, N5 and N7 are identical. The even adjacency graph is shown in Fig. 2, and the odd adjacency graph is shown in Fig. 3. We define the shortest distance between two vertices vj and vj as the sum of the edge weights of the shortest path from vi to vj. The shortest distance between each pair of vertices can he determined by an all-pairs shortest path algorithm [4]. If the shortest distance between v~ and t~j is 0, it implies that the two corresponding nets N~ and Ni and all nets in between are all identical. It may be better to merge two identical nets and assign only one feed-through pin. Fig. 4 shows an example. Clearly, if the shortest distance between vi and O is less than or equal to 1, they can be adjacent in the final feed-through net sequence. Some identical nets are covered by v~ or vi.
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Fig. 4. Net merging. Definition 2. Given a feed-through net sequence which is even-swapped (or odd-swapped), some nets can be absorbed by their identical neighbors and from the sequence. The resulting sequence is called a reduced even-swapped (or odd-swapped) feed-through net sequence. After we construct the adjacency graph and determine the shortest distances of all pairs of vertices, we proceed to construct the configuration graph.
2.3. Configuration graph For simplicity, we assume that each ordinary cell in the cell library has exactly one implicit feedthrough pin, though our algorithm applies to the more general case in which each cell can have zero or more than one implicit feed-through ports. We construct a directed acyclic graph called configuration graph. First, we introduce the vertices. An a-vertex corresponds to a net occupying a feed-through cell. Its notation is ~(n, c, l) which means the feed-through cell is occupied by net n, the nearest ordinary cell to its left is c (if c is assigned " - " , then it means n is at the left end of the cell row), and it is located at column l(O<~l<<,L). A /~-vertex corresponds to an ordinary cell. Its notation is ~(n,c, l), which means the ordinary cell is the cth cell on the cell sequence, the nearest feed-through net before it is n (if there is no feedthrough net before cell c, the first field is filled by " - " ) , and its left edge is aligned with column I. A 7-vertex corresponds to a net occupying an implicit feed-through port. Its notation is 7(n,c,l), which means the net n occupies the implicit feed-through port of cell c (c ~> 1), and the left edge of cell c is aligned with column l. In addition, there exist a source S and a sink Z. Let l(c) denote the length of cell c, and lr be the length of the feed-through cell (There is only one type of feed-through cells in the library.) We assume that the port position is in the center of a feed-through cell. Let D(n,n') be the shortest distance from net n to net n' in the adjacency graph. Let M denote the number of ordinary cells. If e = (u, v) is an edge in the configuration graph, it must satisfy one of the following rules. Note that all l's, l~ 's and /2's are positive integers less than or equal to L, the maximum row length.
1. u=~(nl,c, lj) and v=~(n2,c, 12), where D(nl,n2)<~l and 12 -- lj >~lf. 2. u = ~(n, c, lj ) and v =/~(n, c + 1, 12), where 12 -- I i / > If~2. 3. u=fl(n,c, li) and v=fl(n,c + 1,/2), where 12- lj >~l(cl). 4. u=fi(nl,c, ll) and v=cz(n2, c, 12), where D(nl,n2)<~l and 1 2 - ll >~l(c) + Ir/2. 5. u = fl(nt, c, l) and v = 7(n2, c , / ) , where D ( n l , n2) ~< 1. 6. u = ?'(n I, c, I i ) and v = ~(n2, c, 12), where D(nl, n2) ~< 1, and 12 -- I I > / l ( c ) + lf/2.
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u=7(n,c, ll) and v=[J(n,c + 1,/2), where l e - 11 >~l(q). u = S and v = c~(n,0, 1), where D(s, n) = 1. u = S and v = / ~ ( - , l , / ) . u=~(n,M, l) and v = Z , where D(n,z)= 1, and cell M is the rightmost ordinary cell. u=fl(n,M,l) and v = Z . (The same as Rule 10.) u--7(n,M,l) and v = Z . (The same as Rule 10.)
The above rules are self-explanatory. The first rule says that the shortest distance between nj and n2 in the adjacency graph is at most 1, and they occupy two consecutive feed-through cells (to the right of the cth ordinary cell). The distance between the locations of the two nets is at least lr (Fig. 5). For the configurations specified in rules 2,3,...,7, please refer to Figs. 6-l 1. The rest of the connection rules are not graphically illustrated. We illustrate the construction of configuration graph by a simple example (Figs. 12-14). There is only one ordinary cell C. l(C)=4, and lr = 2. There are two even-interchangeable feed-through nets N~ and Nz which are not identical. The maximum row length is 6. In Fig. 12, the even adjacency graph for nets N1 and N2 is shown. The configuration graph is shown in Fig. 13. The path
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Fig. 12. The even adjacency graph for two feed-through nets.
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Fig. 14. A simple feed-through pin assignment.
S -+ f l ( - , 1,0) --~ y(N1, 1,0) ~ 0~(N2, 1,5) ---+Z corresponds to the feed-through pin assignment shown in Fig. 14. Given a path P from S to Z, we can extract the first attributes of all the vertices on the path except S and Z and form a sequence of nets. There are some sub-sequences of identical nets. For those sub-sequences, we keep only one net and remove the rest. We change each N i' back to Ni. We call the resulting net sequence N(P). L e m m a 1. Given a path P from S to Z in a configuration graph, the extracted net sequence N(P) must be a reduced even-swapped (or odd-swapped) net sequence. Proof. We assume the contrary, which says that N(P) is not a reduced even-swapped (or oddswapped) net sequence. In other words, there exists a pair of consecutive nets whose shortest
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distance in the corresponding adjacency graph is greater than 1. This is not possible, according to the connection rules specifying the values of the shortest distance function D. By contradiction, N(P) is a reduced even-swapped (or odd-swapped) net sequence. [] Definition 3. A legal ./bed-through assignment is an assignment of an even (odd) interchangeable sequence of feed-through nets to feed-through cells or implicit feed-through ports such that 1. The ordering of the feed-through nets on the cell row corresponds to a reduced even-swapped (odd-swapped) net sequence. 2. Each feed-through net is either between two ordinary cells (using a feed-through cell), or occupies an implicit feed-through pin or at the left or right end of the cell row; 3, No more than one feed-through nets occupy a feed-through pin; 4. Each feed-through net n is given a column number c(n) denoting its position, which satisfies that c(n)<~L for all n, and all c(n)'s are strictly increasing; and 5. The ordering of the ordinary cells is fixed. Theorem 1. There is a one-to-one correspondence between the set of all paths j?om S to Z in the configuration graph and the set of all legal feed-through assignments containing all d(ff'erent feed-through nets. Proof. We first show that any path P from S to Z in the configuration graph corresponds to a legal feed-through pin assignment containing all different feed-through nets. The extracted net sequence N(P) satisfies Definition 3(1) because of Lemma 1. We show that N(P) satisfies Definition 3(2). Obviously the e-vertices or 7-vertices in the path indicate where the corresponding nets reside. The net sequence N(P) must also satisfy Definition 3(3). Since according to the construction rules, P cannot contain consecutive y-vertices, which implies that if an implicit feed-through pin is occupied, it must be occupied by exactly one feed-through net. It is also easy to see that no two feed-through nets can occupy the same feed-through cell. If this is not the case, the two corresponding :~-vertices must have the same second and third attributes, which is not allowed by Rule 1. It is apparent that N satisfies Definition 3(4). If a net n comes from an c~-vertex, the third attribute is c(n). If n is from a 7-vertex, c(n) is the third attribute plus the distance from the implicit feed-through pin to the left edge of the containing cell. The values of c(n)'s are strictly increasing because the values of the third attributes of all vertices in P are non-decreasing, and the distance of an implicit feed-through pin to the left end of the containing cell is non-zero. Lastly, to show that Definition 3(5) is satisfied, we extract the second attributes of the fl-vertices in P. The resulting ordinary cell sequences must have the same ordering of the given ordinary cells, since in any two consecutive /J-vertices in P, the second attribute of the second/J-vertex must be one greater than that of the first/I-vertex. Now, we show that for any legal feed-through assignment containing all different feed-through nets, there is a corresponding path from S to Z. We can consider a legal feed-through assignment as a sequence of feed-through cells and ordinary cells, some of whose implicit feed-through pins are occupied by feed-through nets. We scan from left to right. While at the left end, we identify the vertex S. When we reach a feed-through cell, an ordinary cell, or an implicit feed-through pin, we identify a corresponding c~, /~, or ~, vertex, respectively, and determine the values of the three vertex attributes according to its column position, the containing (or preceding) cell, and the preceding feed-through net. Finally, when we reach the right end, we identify the vertex Z. In this way, we
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created a vertex sequence. It is clear that each vertex in this vertex sequence is in the vertex set of the configuration graph. Furthermore, for any pair of vertices in this sequence, there must exist an edge in the edge set of the configuration graph that connects them, since their relation must satisfy one of the 12 connection rules. [] We explain how the weights of the edges are assigned. Each edge determines a sub-channel from 11 to 12- 1 above and below the cell row, where ll is derived from the third attribute of the source vertex, and 12 is derived from the third attribute of the target vertex. The pin positions in the subchannel are fixed, so the maximum density of each sub-channel is a constant. The exceptions are S and Z, whose positions are assumed to be at the left end and right end, respectively. The weight of each edge is an ordered-pair (dl,d2) where dl is the density of the sub-channel above the cell row from column l~ to 12 -- 1, and d2 is the density of the sub-channel below the cell row from column II to 1 2 - 1.
2.4. Min-max path problem The original problem can be solved by finding a path from S to dl (or d2) on any edge along this path is minimized, while the all the edges on the path is no more than a given constant. We path problem. The algorithm to solve the upper channel problem algorithm is similar.
Z such that the maximum density maximum density d2 (or d~) of denote this problem as min-max is as follows. The lower channel
Algorithm 2. Upper channel density minimization Begin 1. D +- the largest upper edge weight on the configuration graph. C +-- the largest allowable lower edge weight, d ~ D
2. d+--d- 1 3. Delete all edges whose upper weights exceed d or lower weights exceed C, and perform depth first search to test if there exists a path from S to Z. If the test succeeds, store this path and go to Step 2. Otherwise, report d + 1 and the corresponding path and exit.
End. Step 3 of Algorithm 2 runs in O([V I + [El) time, where IV] and IE] are the number of vertices and the number of edges of the configuration graph, respectively. Since Step 3 is only executed O(1) time, Algorithm 2 has time complexity O(I V] + [El). We analyze the space requirement of the configuration graph. In the worst case, the number of a-vertices is O(NML), where N is the number of feed-through nets, M is the number of ordinary cells, and L is the maximum row length. This is the number of all possible combinations of the three attributes specified in an a-vertex. Similarly, the number of fl-vertices and 7-vertices are also O(NML). Because of the constraints given by the connection rules on the first two attributes n and c, the out-degree of a vertex is O(L). Therefore, in the worst case, the number of edges is O([VIL), so the required space for the edges is O(NML2). The required time for building the configuration graph is O(N 3 + N2M2L2). First, we need to run the all-pairs shortest path algorithm on the adjacency
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graph (The time complexity is O(N3).) Then we create all vertices of the configuration graph. Based on the connection rules, we determine whether there exists an edge between any pair of vertices. This accounts for the second term N2M2L 2 of the time complexity.
Theorem 2. The problem of single-row feed-through pin assignment of even (odd) interchangeable nets for minimizin9 the density of the channel above (below) the cell row subject to the density bound on the other channel can be solved optimally in O(N3+ N2M2L 2) time and O(NML 2) space. 3. Multiple-row feed-through assignment To approximately solve the multiple-row feed-through pin-assignment problem, we can iteratively apply the single-row algorithm on each of the middle R-2 rows until there is no improvement on the total density. While working on row i, the cells and feed-through nets on row i-1 and i+1 are fixed. We state it in the following algorithm.
Algorithm 3. Multiple-row feed-through pin assignment Begin 1. Total-density-reduction +- 0. 2. Select next non-processed row. 3. Iteratively make the net sequence even interchangeable or odd interchangeable, and iteratively perform single-row upper channel density minimization or lower channel density minimization algorithm, until there is no improvement. Update total-density-reduction. If not all rows are processed, go to Step 2. 4. If total-density-reduction = 0, stop. Otherwise, go to Step 1.
End 4. Over-the-cell feed-through assignment If the given technology allows over-the-cell routing, we can use the over-the-cell layer for routing feed-through nets. In this case, the feed-through cells and implicit feed-through ports are not needed. Our graph-theoretic technique can also be applied. The configuration graph is simpler. In addition to S and Z, the configuration graph needs only one type of vertices - 6(n, 1), which means net n crosses the cell row at column l. The connection rules for each edge e = (u, v) are:
1. u=~(nl,lj) and v=6(n2,12), where D(nl,n2)<.l and ll <.12. 2. u = S, and v = 6(n, l), where D(s, n) = O. 3. u=6(n,l) and v = Z , where D(n,z)=O. After the graph is constructed, Algorithm 2 is again applied. Based on similar analysis, we state the following theorem.
Theorem 3. The problem of single-row over-the-cell feed-through assignment of even (odd) interchangeable nets for minimizin9 the density of the channel above (below) the cell row subject to
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the density bound on the other channel can be solved optimally in O(N 3 + N2L 2) time and O(NL 2) space. As mentioned, it is a special case of the general single-row feed-through assignment problem. We think of the cell row as an empty row without any ordinary cell (M = 0 , so O ( M ) = 1). We also assume the width of a feedthrough cell If is 1, which equals the width of a column. A 6-vertex 6(n, l) is equivalent to an e-vertex e(n, 0, l). The three connection rules are equivalent to the connection rules 1, 8 and 10 in Section 2.3, respectively. Therefore, Theorem 3 is implied by Theorem 2. References [1] G. Meixner, U. Lauther, A new global router based on a flow model and linear assignment, Proc. ICCAD'90, 1990, pp. 4-47. [2] X.E. Hong, J. Huang, C.K. Cheng, E.S. Kuh, FARM: an efficient feed-through pin assignment algorithm, Proc. 29th DAC, 1992, pp. 530-535. [3] T. Okamoto, M. Ishikawa, T. Fujita, A new feed-through assignment algorithm based on a flow model, Proc. ICCAD'93, 1993, pp. 775-778. [4] T.H. Cormen, C.E. Leiserson, R.E. Rivest, Introduction to Algorithms, The MIT Press, Cambridge, MA, 1991. [5] Y. Cai, D.F. Wong, Optimal channel pin assignment, 1EEE Trans. Comput. Aided Des. 10 (l l) (1991) 1413-1424.
Yao-Ping Chen received the B.S. degree in computer science and information engineering from the National Taiwan University in 1988 and the M.S. and Ph.D. degree in computer science from the University of Texas at Austin in 1992 and 1996, respectively. He is currently with Avant! Corporation as a senior software engineer. His research interests include VLSI layout and logic synthesis, and design and analysis of computer algorithms.
D.F. Wong received the B.Sc. degree in mathematics from the University of Toronto (Canada) and the M.S. degree in Mathematics from the University of Illinois at Urbana-Champaign. He obtained the Ph.D. degree in computer science from the University of Illinois at Urbana-Champaign in 1987. Dr. Wong is currently an Associate Professor of Computer Sciences at the University of Texas at Austin. His main research interest is CAD of VLSI. He has published more than 140 technical papers and has graduated 14 Ph.D. students in this area. He is a coauthor of "Simulated Annealing for VLSI Design" (Kluwer Academic Publishers, 1988). Dr. Wong received best paper awards at DAC-86 and ICCD-95 for his work on floorplan design and FPGA routing, respectively. He is the technical program chair of the 1988 ACM International Symposium on Physical Design (ISPD-98). He has also served on the technical program committees of a number of other VLSI CAD conferences (e.g. 1CCAD, ED&TC, ISCAS, FPGA). He is an Editor of IEEE Transactions on Computers.