A high field triode

Solid-State

Electronics

Pergamon

Press 1965. Vol. 8, pp. 349-363.

A HIGH

FIELD

Printed in Great Britain

TRIODE

H. C. NATHANSON Westinghouse (Received

Research 4 May

Laboratories,

Pittsburgh

35, Pennsylvania

1964; in revised form 23 September

1964)

Abstract-Single junction insulated-gate silicon triodes exhibiting very high d.c. voltage gain are described. These planar devices consist of a high resistivity n type substrate into which is diffused a p region of suitably high surface concentration. An aluminum gate electrode, positioned over this junction but insulated by an SiOs layer, provides a means by which intense surface fields can be applied to the underlying semiconductor. At a surface field of about 10s V/cm, the reverse current of the p+n junction markedly softens. At higher values of diode voltage, the reverse current saturates sharply resulting in pentode-like characteristics. A model for the operation of this triode, based on a combination of electrostatically-induced tunneling and substrate pinch-off, is presented. R&sum&-On dCcrit des triodes au silicium 1 une jonction et g dkclenchement isolC demontrant un gain de tension g courant continu t&s 6levC. Ces dispositifs plans comprennent une couche infkrieure g haute resistivitk de type n dans laquelle est diffusee une rCgion p ayant une forte concentration de surface appropriCe. Une electrode de dkclenchement en aluminium sit&e au-dessus de cette jonction mais isolee par une couche d’OsSi permet aux champs de surface intenses d’&re appliquCs au semiconducteur en dessous. A un champ de surface d’environ lOsV/cm le courant inverse de la jonction p+n s’adoucit sensiblement. A de plus grandes tensions de diode, le courant inverse se sature fortement et il en resulte des CaractCristiques similaires g la pentode. Un modele pour l’operation de cette triode basCe sur une combinaison de tunnel induit par Clectrostatique et par reserrement de la couche infCrieure est present& Zusammenfassung-Siliziumtrioden mit einem ubergang und isoliertem Tor, die eine starke Gleichstromspannung-VertsPrkung zeigen, werden beschrieben. Diese Planar-Gergte bestehen aus einem Substrat vom n-Typ mit hohem spezifischen Widerstand, in das eine p-Zone ausreichend hoher Oberfllchenkonzentration eindiffundiert worden ist. Eine Aluminium-Tor-Elektrode steht iiber dem iibergang, ist aber durch eine SiOs-Schicht isoliert und liefert die MBglichkeit, intensive Oberfllchenfelder an den darunterliegenden Halbleiter zu legen. Bei einem Oberfl&henfeld von etwa lOsV/cm wird der Sperrstrom des p+n-uberganges deutlich weicher. Bei hohen Werten der Diodenspannung wird der Sperrstrom gessttigt, so dass die Kennlinien denen einer Pentode gleichen Ein Model1 fiir die Arbeitsweise dieser Diode, das auf einer Kombination eines elektrostatisch induzierten Tunneleffekts und einer Abklemmung des Substrats beruht, wird angegeben. 1. INTRODUCTION

paper describes an insulated-gate silicon triode operating at gate fields in the range 106-107 V/cm. The high doping concentration required in the diffused contact of the device indicates that one of the mechanisms responsible for device operation is tunneling. The voltage-current characteristics of this triode are pentode-like and the device possesses a high voltage gain. Device behavior is well defined and reproducible. In this paper, the experimental behavior of the triode will be described in detail and contrasted with the behavior of the ordinary insulated-gate field effect transistor.(l) A model for device operation will be proposed and the implications of this THIS

I

model compared to experiment. An assessment of the utility of this three-terminal tunneling device at high and intermediate frequencies will be given. Other insulated-gate field effect transistors have attracted wide attention recently.@JJ In these devices, the gate field controls the number of carriers and therefore the conduction between the device source and drain electrodes. The theory of insulated-gate transistors of this type is discussed by IHANTOLAand MoLI,.@) The control of avalanche breakdown at the surface of a pn junction using an insulated-gate electrode has recently been reported.(s,5) The influence of surface fields on avalanche breakdown has been recognised.(s)

349

350

H.

C.

NATHANSON

The control of tunneling, or internal field Metallised contacts to both the p+ and bottom of emission at the surface of a pn junction using a the n region complete the device. Two diffused gate electrode was first proposed by ATTALLA, regions, such as are used in the ordinary insulatedgate transistor, are not needed here. et. aZ.,(7) who demonstrated device feasibility using The active periphery of the device illustrated in a silicon grown pn junction and a polyethyleneFig. 1 is about 12 mils while the gate area is about oxide insulator. The silicon planar version of this 28 milsa. Due to the large area-to-periphery ratio, tunneling device was reported recently.@) this geometry is not optimised for high frequency In order to differentiate the planar tunneling operation. The topological isolation afforded by the triode reported here from the normal insulatedgate transistor, such as reported by HOFSTEIN and enclosed active periphery makes this geometry HEIMAN,@) the former shall be referred to as high attractive, however, for the d.c. measurements to be reported here. In this figure, the voltage between field triode, or HFT, in keeping with the characterthe pf region and the n region of the device is istically high oxide field necessary to initiate operacalled I’D and is taken positive when the p+n tion in the device. junction is reverse biased. A voltage + Yo refers 2. EXPERIMENTAL to a positive gate polarity with respect to the p’ region, which, in operation, is usually grounded. a. Device description and fabrication Since the insulated gate conducts no d.c. current, One possible configuration of the device to be described is as shown in Fig. 1. An annular p+ 10 will refer to the direction of the reverse current in the p+n junction. region is diffused into a high resistivity n type silicon substrate using a boron source and a b. Current-voltage characteristics standard combination of oxide masking and photoSome of the more important terminal features of resist techniques. After diffusion, the masking the high field device are reported in this section. oxide is completely stripped away, and a uniform The current vs. voltage characteristic of the oxide layer, typically 500 A to 5000 A, is regrown over both the p+ and n regions of the device. An triode with zero gate voltage is essentially that of evaporated aluminum gate electrode is placed over the p+n junction lying under the gate. However, this oxide so as to overlap the inside periphery of as a positive voltage is applied to the gate electrode, the p+ region (innermost circle in Fig. 1). the current flowing in the p+n junction increases by orders of magnitude providing certain conditions are met. These are: (1) the doping on the surface D = 14Mils Gate, of the p+ side of the junction must be greater than about 1019 cm-s, (2) the oxide field produced by the gate electrode must be about 10s V/cm or greater, and (3), the gate electrode must overlap not only the high resistivity n region of the triode but at least a few microns of the p+ region as well. A series of observations and experiments leading to the above conclusions follow. The most salient feature of the high field device is the marked role the doping level on the p+ diffused side of the p+lz junction plays in gross device operation. Quite simply, unless the doping on the p+ side is high enough, the triode will not work normally, i.e., the gate field will exert no control over the low voltage device characteristic. Typically, it was found that those devices with in the range p-side surface concentrations 1019-1020 cm-s exhibited high field triode behavior while those in the range of a few times FIG. 1. Circular geometry of a high field triode.

A HIGH

FIELD

101s cm-a and below did not. This is illustrated in Fig. 2 where two sets of devices with the circular geometry of Fig. 1 have been processed under similar conditions. Both device sets had an 1z type substrate resistivity of SQcm, junction depths of 4 TVf 5%, and an oxide thickness of 2500 A f 20%. By a modification of the gaseous ambient during the p+ diffusion, the first set of devices had a surface concentration on the p+ side of the junction of 2 x 101s cm-s, while the second set had a concentration of 9 x lOI cm-3.

-ID

(a)

(b)

m

-"D

/rlllflIlll

Iii i i i E i i i i I FIG. 2. Effect of doping level of the diffused region on gate modulation of VI characteristics of p+n device: (a) Indicated surface concentration = 2 x lOI* cm-3, Oxide fields = 0, 5 x lo6 V cm-l; (b) Indicated surface concentration = 9 x 10lg cm+, Oxide fields = 0, 2.5 x lo6 V cm-l. Horz. = 0.2 V/div. Vert. = 0.01 mA/div.

TRIODE

351

In Fig. 2 the qualitative difference in the voltage-current behavior of the two sets is illustrated. In Fig. 2(a), the characteristics of the device with the lower surface concentration are illustrated for two values of gate field, 0 and 5 x 106 V/cm. It can be seen that the two curves are coincident, no perceptible modulation of the normal diode characteristic being in evidence. In contrast, typical triode characteristics with a highly doped region are illustrated in Fig. 2(b) where gate fields of 0 and 2.5 x 106 V/cm are shown. Note the distinct and somewhat symmetrical modulation of the diode current for an oxide field of 2.5 x 106 V/cm. Although only two values of gate field are shown in Fig. 2(b), smooth modulation of the reverse characteristic of the p+n junction up to a gate field corresponding to oxide breakdown was possible. Since the range of the characteristic illustrated in Fig. 2 is only - 1 5 VD I + 1 V, additional effects of these intense gate fields on the p+n junction characteristics are not seen. In Fig. 3(a), the reverse characteristic of the p+n junction over a greatly increased voltage range is shown. Six curves, corresponding to six different values of surface field, are illustrated. Figure 3(b) shows the circuit used to trace these curves. In the lowest of the curves in Fig. 3(a), the reverse characteristic of a typical device shows that for zero gate field the device exhibits a sharp avalanche breakdown at about 75 V. To the scale of this figure, no perceptible change in this zero gate voltage curve was seen until the oxide field exceeded about 3 x 106 V/cm. At about 4 x 106 V/cm, a slight rounding of the characteristic near the knee is observed. Beyond this value, increased gate field results in a substantial lowering of the breakdown voltage of the junction. An increase from 4.5 to 6 x 10s V/cm results in a decrease of about 25 V in the breakdown voltage of the p+n junction. This decrease is believed to be a direct effect of the gate field on the ionisation rate at the surface of the p+n junction, a Townsend-type phenomenon, and will not be discussed further here. GARRETT and BFWITAIN(~) have treated the effect of surface fields on avalanche breakdown in similar structures. On primary interest is the current modulation nearer to the origin of the characteristic in Fig. 3. It is this modulation, the same as occurred in the highly doped sample of Fig. 2, which is identified

352

H.

C.

NATHANSON

voltage Vo m 5 V in the top curve of Fig. 3, and (3) a low impedance region at higher values I’D corresponding to ultimate avalanche breakdown. Regions (1) and (2) are of interest in this paper. In many of the triodes reported here, the soft VI curve with the monotonically increasing slope near the origin illustrated in some of the lower curves in Fig. 3 is not in evidence. Instead, a clean saturating current component, close to the origin, rises sharply at some critical value of oxide field. The VI characteristics of such a device, a circular geometry p+n HFT, are displayed in Fig. 4. In this 1000 a device, a succession of gate voltages differing by 1 V per step and beginning at Vo = +55 V, are shown. The VI characteristics in this figure are quite flat over a wide range in gate and drain voltages. Defining a device transconductance in the conventional manner (gm E ~S~/aVolv~), it can be seen that although gm in the device m Fig. 4 is low (- 50 pmhos at Vo = +75 V), the saturation of the current characteristic is sufficiently pronounced that a high amplification factor results. Typical mu’s are 200 or more.

654321 $

(4

+ ri;’ +--ID

v

(b)

+I

D Perephery = 12 Mils w ox = 1000 A

I

$ +

V(@

I

P+

&

T

'D

T

FIG. 3. Evolution of VI characteristics of high field device; curves 1 through 6 correspond to an oxide field of 0 through 3, 4, 4.5, 5, 5.5 and 6 x 1OsV cm-l respectively. Horz. = 10 V/div. Vert. = 0.2 mA/div.

with electrostatically-induced tunneling in this paper. The VI characteristic at a given gate field can be divided into three successive regions: (1) a low impedance region near the origin, which may or may not have a monotonically increasing slope, (2) a region where the current has more or less saturated, as, for example, beginning at the

VG = + 55 Volts / 0

+v

AVG= + 1 Volt/Sk;,

D

FIG. 4. VI characteristics of a typical p+n high field triode. Initiation voltage = + 32 V. Horz. = 1 V/div. Vert. = 0.05 mA/div. We define the voltage Vo at which the current 10 saturates as I’SAT. Thus, in Fig. 4, a value of VG of +55 V results in a V~AT of about 2 V. The relationship between V&tT and v/G,as represented in Fig. 4, is worthy of note. It can be seen that a 19 V change in Vo results in a change of about 1.5 V in I/sAT. In the device illustrated then,

AV~AT/AV~ Many

experiments

% l-5119 = 0.08 on

a number

of

different

A

HIGH

FIELD

devices have confirmed the fact that this ratio in the HFT is usually much less than unity. This relationship is of interest when it is recalled that the ratio (AV~AT~AVG) for a regular surfacecontrolled insulated-gate transistor fabricated on a high resistivity substrate is approximately unity.(s) Note that the voltage Vc = 55 V is not the lowest voltage which initiates conduction in the device in Fig. 4. This “initiation” voltage was found to be about 32 V in the HFT illustrated. The characteristic conduction field was therefore 32 V/l000 i% m 3 x 106 V/cm, consistent with the approximate fields necessary to effect conduction in Figs. 2 and 3.

TRIODE

353

The results of this experiment are indicated in Fig. 5. In the triode sets Nos. 7 and lower, where the gate does not overlap the p+ region, no operative devices were obtained. In set 9, in which the gate is about 3 p beyond the p+n junction interface and about 1 p beyond the oxide window used as the original diffusion mask, 80% of the devices are operative. In set 10 and beyond, all devices were operative. Thus, the pf region must be overlapped by the gate before the HFT will work. Although the resolution of this experiment is limited to about 3 f~ due to gate edge irregularities and gate-junction misalignment, the following additional comments can be made: little improvement in triode 3p

Gate

p+

:’ :,_.-.:

1 ;’ ..,.:,; t I

t20

Iil’I//IIIfI

% Operating 50 Cevlces

I

+10

+5

-5

0

8 in microns-20 A

Each Bar Represents IO Devices LEFF’4/.L i Mark 101 x P+ N Triode /

li 16 SET

FIG.

5. Effect

of gate

overlap

In an attempt to ascertain the roles played by the two sides of the p+n junction of the HFT, the following experiment was carried out: Fifteen sets of high field devices, identical except for the position of the gate electrode relative to the p+n junction, were fabricated. A device geometry having a straight rather than circular junction periphery was employed. As one edge of the gate electrode was moved progressively in the direction of the p+ region (see Fig. S), the percentage of operational devices was plotted versus edge position. In this experiment, an “operational” device was one in which a saturation current of 5 PA or greater was in evidence just short of a field corresponding to gate oxide breakdown. Only those devices exhibiting a relatively high output impedance typical of the behavior illustrated in Fig. 4 were considered operative.

of

ion on device

operation.

characteristics was noted beyond set 10, indicating that the length of the active region of the triode on the p+ side is only about 4-6 1.~.Furthermore, set 8 indicates that the gate must extend into the highly doped region of the p type diffused contact if the triode is to work normally. In summary, these results show that a gatecontrolled oxide field of N 3 x 106 V/cm. over the surface of a p+ region doped in excess of 1Olg cm-3 can result in a pentode-like device at voltages VD well below those voltages at which gate-controlled avalanche breakdown has been reported. A model for the high field triode consistent with the above observations will now be presented. 3. THEORETICAL

In this section, a first-order model is proposed to explain such observations as the high initiation

H.

354

C.

NATHANSON

+“I,

+“, FIG. 6. Model

for a high field triode.

field, low transconductance, and low saturation voltage of the HFT. In addition, the role of the surface impurity concentration of the diffused region will become apparent. Effects due to the detailed impedance of the tunneling contact of the device will be neglected resulting in a simple theory which is still in good agreement with experiment. A schematic model for the p+n triode is illustrated in Fig. 6. In Fig. 6-1, the position of the active, or controlling region is indicated. The proposed active mechanism in the device is the conduction of electrons through an n+ channel induced on the surface of the p+ region by the gate field. Electrons enter and leave this channel by means of effective source and drain contacts much as in the ordinary field-effect transistor. However, while two highly doped diffused regions provide source and drain contacts in the ordinary FET, the situation is somewhat different in the high field triode. In this device, electrons tunneling from the valence band of the p+ region into the channel provide the source of channel electrons, while contact of the channel with the high resistivity n type substrate provides the channel drain. The proposed electrical properties of the active region are illustrated in Fig. 6-2, where the inversion layer, represented by a resistive chain, is shunted by a non-linear (tunneling) distributed source contact. Both the channel conductance and the voltage-current characteristic of the distributed contact are functions of both the gate and channel voltage. The electronic current in Fig. 6-2 flows from the grounded p+ region, through the thin

depletion region separating the p+ and n+ regions (by tunneling), along the channel and out to the bulk through any spreading resistance R, which may be present at the end of the channel. In this first-order theory, the effect of the spreading resistance R, and the distributed nature of the tunneling contact are neglected. An assumed source contact is made to the channel by a localised tunneling region an effective distance LEFF cm from the edge of the p&n junction. The resulting electrical representation of the triode is illustrated in Fig. 6-3. Furthermore, by assuming that the impedance of the tunneling region is much less than that of the channel, the source end of the channel is effectively held at ground potential. As a result of these assumptions, it is possible to represent thep+n HFT in the manner illustrated in Fig. 7. Except for the source of channel electrons,

Cross

SeCtIOn

5 n’

’

LEFF-

(0) FIG.

7.

t/p+/n

(a) Schematic representation of HFT insulated-gate triode; (b) band diagram pendicular to surface of HFT.

as a per-

A HIGH

FIELD

the p+n HFT is the equivalent of an nJpJn insulated-gate triode having a channel length of LEFT. In the n/p/n triode, the channel is in good communication with the conduction band of the heavily-doped n type source contact; in the “t/p/n” device represented in Fig. 7, the channel is in good communication with the valence band of the heavily-doped p region. In both cases, a plentiful supply of source electrons is available. In the analysis of the p+n high field triode, the effect of the p+ substrate on the device characteristics below saturation is first investigated. Borrowing liberally from IHANTOLA and MoLL,(~) the field ED associated with an appliedvoltage Va between the n channel and the p+ contact is calculated. The band picture for a non-zero value of V, is shown to the right of Fig. 7. In this figure, the application of a gate voltage Vo with respect to the grounded p+ region has resulted in the formation of an n+ layer on the semiconductor surface. The voltage V, appears as a splitting of & (volts), the quasi-Fermi level for electrons at the surface and &, (volts), the Fermi level in the underlying p+ region. Although the doping of the semiconductor in the p+ region is not constant perpendicular to the surface, a value +,, consistent with the doping CO (cm-s) at the surface of the p+ region will be used. This value is a good approximation since (1) the characteristic lengths associated with most impurity diffusion profiles are in the range lOOO40,OCO A, while (2) the effect of a surface field extends a distance of only a few extrinsic Debye lengths into the surface, which, for material doped high enough to tunnel, is about lo-100 A. Because Co must be the actual surface concentration, effective values of Co obtained from conventional sheet resistance-junction depth measurements may not be applicable due to possible outdiffusion, impurity spiking, etc. at the surface.@) Following BROWN,(~@ we assume that the charge density within the region $p, 5 EI 5 qhnin Fig. 7 is approximately -I$‘~, where EI (volts) is the intrinsic Fermi level in the semiconductor. Integrating Poisson’s equation within this region results in ED, that portion of the gate field which terminates in depleted acceptors rather than mobile electrons : - (dp,--Va) Es=_D

2 KtiI

s

aCod+

(1)

TRIODE

35.5

where

ED = characteristic

depletion region field (V cm-t) Co = impurity concentration at the surface of the p region (cmp3) 4 = electrostatic potential (V) +p, = electrostatic potential associated with doping Co (V)

V, = applied

ESI = dielectric

channel-to-p+ region potential constant of silicon (F cm-i)

From

law,

Gauss’

8 mobile

=

Do.z-DD

(V)

(2)

where Qmobire=mobile charge density at the surface (C cm-2) Doz, Do= oxide, depletion region electric flux density (C cme2) Neglecting the electrostatic voltage drop within the semiconductor surface due to the gate field, from equations (1) and (2)

Qmobile=

kz [ vGir:x’]

-
(3)

where W,, = oxide thickness (cm) of oxide (F cm-l)

l0% = permittivity

In equation (3), the surface concentration of electrons, Qmobtle is given by the electric flux density in the oxide minus a term depending on both the value of the p side surface doping CO, and the channel-to-p region voltage, V,. The effect of this second term is to “pinch-off” the induced electron layer as V, is increased. Since V, is intimately related to the applied device voltage VD, the larger the value of CO, the greater the effect of this “substrate-type” pinch-off on the current characteristics of the HFT. This pinch-off from the device substrate is usually not a factor in conventional insulated-gate field effect transistors which are usually fabricated on very high resistivity substrates. Pinch-off in these devices is usually only a function of the gate-to-drain voltage. Assuming that the channel current is continuous from the tunneling region through to the edge of the n region, it is possible to write an expression for the device current 1, in terms of a summation of

H. C. NATHANSON

356

voltage drops along the channel:ol) VD

os . W dv

IO = +;;

(4)

s

0

=------

cL12%XC:w

WosLEFF

where 0s

VD

VT

= PnQmobile = channel sheet conductivity (mhos) = n to p+ region device voltage in HFT (V) = threshold voltage

W, LEFF = effective channel width, length (cm) in channel (cm2 CLn = electron mobility V-l set-r) . Physically, the threshold voltage VT is that gate voltage necessary to just invert the surface of the p+ region, assuming that there are no surface states present. For large values of CO, VT can be many tens of volts, depending upon the value of the gate insulator thickness, W,,. For the particular investigation in this paper, it is possible to simplify equation (4) considerably since we will be interested only in rather high values of Co for which pinch-off occurs at relatively low values of VD. Under these conditions, it can be shown that the term (lf V~/24~~)s/* is well approximated by a second-order series expansion in T/D/2+p,. Equation (4) becomes

ID=

K

VG~‘VD-~~

where ycO =

VG-VT

B

=

[l +(vT/4+P”)l-1

K

=

~a%rW/WosLEFF

vi

1

(5)

Equation (5) can be used to explain the observed characteristics of the high field device in the region below saturation. Its simple form is a result of assuming that the doping of the p+ region, Ca, was high. However, at low values of CO, VG, + VG and 8 + 1. Under these conditions, equation (5) is still useful since it becomes identical with the ordinary field effect equation reported frequently by SHOCKLEY.(~~) For intermediate values of CO, equation (5) predicts a slightly lower value of ID than the exact expression given in equation (4). Note that the actual gate voltage Vo in equation (5) has been replaced by an effective gate voltage VG~, which takes account of the necessity of first inverting the p+ surface before electrons can be induced. The effect of the negative term Vj/2 has been intensified by the factor g-1, resulting in an earlier pinch-off of the initial device conductance. If a saturation voltage, VSAT, is defined as that drain voltage at which the device current, ID, from equation (5) reaches its maximum or saturation value, then =

VSAT

BVG,,

(6),

and dl/sAT/dvo It

is

assumed

that

= w.

(7)

10

remains constant for IsAT and the transconare given by

VD 5 V,~AT. Therefore ductance, g,, kAT

f

rz

ID VD

=

iVG

VD

Vi 2

VSAT

HISAT g m=-

K.&2.

=

K.WG,

(8)~

(9)

It follows from equations (6) through (9) that the quantities ISAT, gm, VSAT and ~VSAT/~VG are all diminished by the factor 9 from those values obtained had the device been fabricated on an insulating substrate. The factor .% is equal to or less than one, becoming progressively smaller for higher values of Co. In Fig. 8, the quantity 9 is plotted vs. Co for three typical values of Woz. For example, at the point indicated in the figure, a 1000 .& HFT having a p+ diffused contact with a p interface impurity concentration of 4 x 1Ol8 cm-a would exhibit values for saturation current,

A HIGH

FIELD

saturation voltage, etc., diminished by a factor of 20. Since much of the applied gate voltage is required to invert the p+ surface, the combination of high onset field and strong substrate pinch-off severely limits the output current for a given input voltage in this device.

TRIODE

357

the length of the active region of the device, LEFF, due to space-charge widening, it is possible to obtain approximate expressions for the output conductance and amplification factor of the triode. Assuming, quite conservatively, that space-charge widening occurs only on the p+ side of the junction, it can be shown that the resulting gain is Amplification Factor = mu

Note that mu is larger by a factor of about B-1 than the amplification factor obtained for an insulating substrate [(E,,/QJ) * (LEFF/W,,,)].@) This increase in voltage gain is primarily due to the shielding effect of the p+ substrate in electrostatically isolating the drain and channel regions in the device. In summary, this model for the high field triode implies several important limitations. The p+ diffused region, in its duel role as both the effective channel substrate as well as the site where 1020 tunneling can commence, imposes restrictions on co, the current levels in the HFT. Since any element of current tunneling to the surface must pass over FIG. 8. The factor “W” vs. CO, the surface concentration a region doped to essentially p+ degeneracy, the on the highly doped region in the HFT. substrate gating effect is pronounced. The result is that these devices have relatively low transconThe speed of the HFT, defined as the inverse ductance and therefore low speed. In addition, the gate time constant, follows from equation (5): necessity of inverting the highly doped surface of the p+ region results in a high onset voltage. 1 &AT VG, CLn VG, SPEED=-x -=--. Certain experiments relating to these results will LB? t VG I Tinput CGATEVG 2L,;, now be presented.

O.OOl>

cIlT3

(10)

where CGATE = minimum

input

capacitance

(F)

%mWLEFF z wm

-

From equation (lo), the speed of the HFT is lowered by a factor of about 92 from the inverse transit time pnV~/2L2 in a device with an insulating base. Physically, the speed of charging the device input capacitance is limited by the effects of both substrate pinch-off and high onset field. By assuming that a variation in the output voltage Vo of the triode results in a variation in

4. ADDITIONAL

EXF’ERIMENTS

It is known that the high frequency capacitancevoltage behavior of a Metal-Oxide-Semiconductor sandwich becomes relatively flat at the value of voltage corresponding to the inversion of the semiconductor. Simultaneous measurements of the input gate capacitance and transfer current characteristics in ap+n HFT were made to establish the relationship between the inversion of the heavily-doped p+ region and the onset of device current. Since the simple theory of Section 3 indicates that current onset should correspond to the inversion of the p+ region [see, for instance, the definition of the threshold voltage VT in equation (4)], this experiment is of possible importance.

358

H.

C.

NATHANSON

Ap+n HFT with the circular geometry in Fig. 1 was fabricated with a 500 A oxide. The insulator was made thin so as to increase the sensitivity to the space-charge capacitance of the p+ region. This increased sensitivity is necessary since the extrinsic Debye length in material doped to 1018-l 01s cm-s is about lo-20 A. In order to assure that we were measuring predominantly the space-charge capacitance of the p+ region and not the n region, the gate was trimmed to within about two microns of the edge of the p+n junction. Less than 10% of the gate area overlapped the n region of the triode. Measurements of Co were conducted at 1 mc using a Boonton 75A-SS bridge, while ISAT was measured at a value of Vo = + 5 V using a Keithley 610 A electrometer. Drift effects were minimised by operating at 77°K.

CC&-)

I,,

166

ok-) -

2 5.6 i

3

5.3’

’ -30

-20

-10 Gote

I 0 Voltage

IO

20

I 30

I

FIG. 9. Gate capacitance and saturation current measurement of a p+n HFT at 77°K.

In Fig. 9, gate capacitance Co (F) and saturation current 1,s~~ are plotted for a typical unit with the gate voltage VG as a parameter. For gate voltages more negative than -25 V, Co remains constant at 5.64 pF. As VG is made more positive, Co decreases, consistent with the depletion of holes at the interface. At a VC of about 18 V, Co again

becomes approximately independent of VC, indicating that appreciable accumulation of electrons has begun. Measurement of 1s~~ vs. VG in the same figure indicates that a sharp rise in the saturation current of the reverse biased p+n junction occurs at a gate voltage of about + 16 V. Since this rise in current is a continuous process, we report that value of gate voltage where the rise in current first becomes obvious above the noise level of the measurement system (about 2 x lo-11 amps). This sharp rise of 1s~~ at a critical value of VG is characteristic of the HFT. Field-effect analysis of the data above, assuming a Co on the p+ side of 1019 cm-3 indicates that the gate voltage at the onset of inversion and the voltage at which l,sA~ rises sharply are, at most, a few kT/g apart. Thus the characteristically sharp rise in the transfer characteristics of the high field triode probably corresponds to the onset of inversion of the surface of the p+ contact in the device, consistent with the proposed model. Further confirmation of gate inversion of the p+ region has recently been obtained in a p+n HFT using a scanning electron microscope to sense the establishment of the inversion layer under the gate electrode. The fact that p+n triodes require a boron surface concentration of at least 101s cm-s if typical HFT action is to occur has already been discussed in conjunction with Fig. 2. In addition, experiments on the complementary n+p high field device indicate an upper limit for CO if the HFT is to be operative. A number of attempts to fabricate the n+p device using a POCls phosphorus source at a predeposition temperature of about 1150°C resulted in failure. In all cases, a surface concentration in excess of 1020 cm-s was obtained. No perceptible modulation of the reverse characteristic of the n+p junction in these devices was seen before oxide breakdown occurred. However, successful fabrication of an n+p HFT was accomplished when the phosphorus surface concentration in the nf region was lowered by employing a phosphorus nitride source. Measurements of the surface concentration of the n+ region using sheet resistivity-junction depth techniques yielded a Co of about 2 x 101s cme3. The VI characteristics of the resulting device are shown at the bottom of Fig. 10. This device exhibits the characteristically high output impedance and

A HIGH

FIELD

saturation voltage insensitivity of the normal HFT. In Fig. 10, the structure appearing in the VI characteristic for - Vo greater than 25 V is time dependent and not completely understood at present. Similar structure has been seen inp+n HFT’s at high values of Vo. Attempts to fabricate pi-n devices using high boron surface concentrations have also yielded inoperative or inferior devices. The conclusion from the above is that, experimentally, the surface impurity concentration on the diffused side of the

_

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359

the tunneling impedance will be low. The device current is then limited by the necessity of inverting the heavily doped semiconductor surface within the limits set by the dielectric breakdown strength of the insulator. Assuming an ultimate dielectric strength, EULT (V cm-l), of about 107 V/cm in SiOs, the expression for L’T in equation (4) may be used to obtain a value for Cb, the maximum surface concentration which can be inverted and therefore can possibly result in high field triode action. Again

_

l---Y0

.‘.“C,:’ .:. “.Nt’:. . ... _’,., .:._,,

-VGate

t N+P

+ -“D

N+P Triode SOUrCe:

P3N5 at 485Y wax = 300!4+ pp = l.OR cm kLLL.LLw -vD VG = -35 volts - 0.5 volts/step

FIG. 10. An n-tp high field triode. Horz. = 5 V/div.

Vex-t. = 0.05 mA/div. HFT must be within certain limits if the device is to be operative. This conclusion is again quite consistent with the proposed model in which the p region acts as both a tunneling site and a region over which the n channel is induced. For low values of Cs, inversion of the diffused contact surface is easily achieved, resulting in a large channel conductance. However, the impedance of the tunneling region is quite high, since the depletion region separating the two carrier species is wide for low values of Co. Conversely, at very high values of C’s, the depletion width at the surface is quite thin. As long as states are available for tunneling,

assuming that there are no surface interface :

C’ =

(EozEULT’2)2

0

M 3x

states at the

1019 cm-3 (12)

¶W4P,

taking +p, M &/2 = 0.5 V. Thus, for devices doped to higher than about 3 x 101s cm-a, the gate insulator of the HFT should break down before modulation is observed. This is indeed the case in devices seen to date. The threshold voltages for high field triode operation may be quite high. For instance, an onset of 40 V is predicted for a device with a

360

H.

C.

NATHANSON

2000 A oxide and a Co of 5 x 101s cm-s. Such a high onset voltage may have an appreciable effect on the qualitative behavior of the high field triode It is theoretically possible to characteristic. markedly reduce the threshold voltage I+ in the high field device by diffusing a thin n type impurity layer onto the surface of thep+ region so as to bring the surface to the onset of inversion. With this method, compensation of the p+ contact must necessarily take place within about an extrinsic Debye length from the surface if a tunneling contact is to be established. The depth control necessary in this diffusion places severe technological restrictions on such an approach. As a result, substantial reduction of the threshold voltage for conduction in the HFT is unlikely without placing severe stress on the gate insulator in the device. In Fig. 11, an attempt is made to fit the theory of the HFT to observed experimental characteristics. In Fig. 11(a), the VI characteristics of a circular 1000 A n+p HFT are illustrated. The device in this figure was fabricated using a PsNs phosphorus source. Sheet resistance-junction depth

measurements indicated a Cs on the n+ diffused region of 2 x l@s cm-3, assuming a complementary error function impurity distribution. In Fig. 11(b) the theoretical VI characteristic of this n+p device has been generated using equations (5) through (9). A value VT = -67 V, which corresponds fairly closely to the experimental onset voltage obtained for this device using a Tektronics 575 curve tracer, has been used in these equations. A fit has been achieved using the values LEFF = 5 p and pp w 15 cm2 V-1 set-1. This low value of hole mobility is consistent with motion of holes confined to a potential well a few tens of angstroms wide at the surface. The qualitative agreement between theory and experiment is apparent from a comparison of Figs. 11(a) and (b). However, the quantity (Avs,~jAI’o) in Fig. 11(a) is larger than the theoretical value dVsAT/dVG = W = O-03 shown in Fig. 11(b). This is probably due to the presence of a series resistance due to either a non-zero tunneling impedance and/or an n+/aluminum contact resistance. The possible contribution of such a series resistance is sketched as the dotted

lOOpa

A-Q= 0 0

"D (al

-20 Volts

lOOpa

= -72

CJ I 2

FIG. 11. Comparison of model with experiment: circular n+p triode; (b) Theoretical fit with NN = pp = 15 cm2 V-l sect’; (c) Log plot

(a)

I 5

I

10 iVG - 671 Volts

I 20

Experimental VI curve of 1.4~ 1Ol9 cmm3, LEFF = 5 p, of ISAT vs. VG~.

A HIGH

FIELD

line in Fig. 11(b). The behavior of the quantity (hvs~~/AVo) in p+n triodes seems to follow much more closely the theory than in the n+$ triodes fabricated to date. Solving for Co using the value VT = -67 V, we find from equation (4) that z 1.4 x lOlQ cm-3(13) assuming $N, z O-5 V.

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As a final piece of corroborating experimental evidence, the important role which substrate pinch-off plays in the characteristics of the HFT is demonstrated in Fig. 12. In this figure, the triode characteristic is traced in two different modes. In Fig. 12(a), the p+ region is grounded and the n region is swept positively; in Fig. 12(b), the n region is grounded while the p+ region is swept negatively. In both cases, the p+n junction is reverse biased. Note the marked difference in output impedance in the two cases, even though

2 Fixed Values of +VG

+VD at 2 Voltsidiv

-

-VD at 2 Volts/div

-

FIG. 12. VI characteristics of a p+n HFT in two different connections illustrating strong role of substrate pinch-off.

A plot of ISAT versus (Vo- 67) can be seen in Fig. 11(c). In this logarithmic plot, a slope of two is in evidence over one order of magnitude, consistent with equation (8). However, it is noted that the slope obtained in a plot of this type was often sensitive to the value of VT selected. It was possible to obtain in certain cases slopes ranging from about 1.5 through about 3 depending upon the value of VT. Considering the experimental uncertainty in selecting VT unambiguously, the excellent qualitative fit obtained for theory versus experiment seems to preclude going to a more complicated model for a first-order description of the device.

a knee in the characteristic occurs at about the same absolute value of device voltage in either connection. This behavior is again consistent with the proposed model. The variation in output impedance in the two connections follows directly from the fact that the p+ contact is effectively the electron “source” in the device. The two connections (a) and (b) correspond, then, to “common source” and “common drain” respectively, the latter connection known to be of low impedance in the ordinary field effect transistor. The fact that a knee appears at the same value of Vo in both connections in Fig. 12 is further indication of the

H. C. NATHANSON

362

presence of an additional pinch-off mechanism which is independent of gate voltage-namely, substrate pinch-off. 5. DISCUSSION Experimental data on a high oxide field insulated-gate triode has been presented. Gateinduced tunneling has been offered as a necessary, though secondary mechanism in the model used to describe the devices reported here. High values of onset voltage and low values of g,, IsAT and dI’SAT/dvo are attributed to the presence of the highly doped p+ layer under the active channel of the device. Experimentally, the value of C’s z 101s cm-s obtained from the n+p HFT in Fig. 11 is larger than the measured value of 2 x 101s cm-3 obtained from sheet resistance-junction depth measurements. Such a discrepancy is consistent with the known rejection of phosphorus by a growing SiOs layer during oxidation. A process of this type has been known to produce ultra-thin surface layers of high phosphorus concentration at the oxide-semiconductor interface.@*) A spike of impurities of concentration 101s cm-s and, say 100 A thick would make little electrical contribution to the sheet conductance of an n+ region doped to 2 x 101s cm-3 and 3 p thick. However, since the Debye length in 1019 cm-s material is less than 100 A, the gate electrode effectively “sees” a 1019 cm-s surface concentration. The analogous observation, the depZe/ion of boron at the Si-SiOs interface,@) has been seen in all p+n HFT’s fabricated to date. The threshold voltage of the gate-induced tunneling contact is, in fact, proposed as a sensitive tool to study impurity concentrations a few tens of angstroms from the interface after oxidation. Drift of the characteristics of the HFT can be pronounced at room temperature for newly fabricated devices. For this reason, many of the experiments reported here were carried out at 77°K. It is interesting to note that the p+n devices exhibit an 1s~~ which increases with time, while the reverse is true of the n+p devices. Both types eventually stabilise, although the n+p triodes stabilise more quickly and without the slight degradation of output resistance which may accompany a stabilised p+n triode. The detailed contribution of the tunneling region to the voltage-current characteristic of the high

field triode has been ignored in the first order model presented here. Essentially, it has been assumed that the diffused region doping at the tunneling site is quite high. The depletion region separating the bulk from the inversion layer is then thin, leading to a situation controlled by the number of electrons available to carry current away from the tunneling site. Even with highly doped diffused regions, however, the impedance of the tunneling region can be significant at very low values of Vo. This is because the Fermi level corresponding to a doping level which can be “easily” inverted by the gate field lies slightly outside the band edge. The lower values of Vo are thus expended in aligning states in the “bulk” and inversion layer so that tunneling can commence. The tunneling impedance in this region predominates. Since the Fermi level in 1Ols cm-a material is only a few kT from the band edge, the above effect has been ignored in this analysis in the interest of simplicity. Also, for simplicity, the two-dimensional aspects of the tunneling contact have been neglected. A detailed analysis of the two-dimensional aspects of the tunneling region by HOFSTEIN(~~) in a similar device are in qualitative agreement with the observations reported here. Any assessment of the ultimate utility of the HFT must consider a number of factors, some of which are: topology, stability, gain and speed. The fact that the high field triode has only a single diffused junction gives the device some advantage in its use as an element in integrated circuits. Arrays of p+n and n+p HFT’s on the same chip can be geometrically implemented with relative simplicity. The high oxide field necessary for HFT operation (a few times 10s V/cm) tends to make the HFT drift more than the ordinary surfacecontrolled field effect transistor. Similar drift behavior in HFT’s of widely different geometry indicates that drift in these devices occurs not only along the surface of, but also within the SiOa insulator. Although drift in the n+p triode is much less objectionable than in the p+n triode, more experimentation is necessary to stabilise both devices at these high oxide fields. Theoretical results in this paper have indicated that the HFT has a voltage. gain about W-1 times higher than the equivalent regular surface field

A HIGH

FIELD

effect transistor (equation 11). This result is in fact conservative. In the derivation, it was assumed, in the interest of simplicity, that space charge widening at the pfn junction occurred completely on thepf side. The converse is approximately true. Thus, the effective channel width LEFF is almost completely independent of the voltage Vn up to values of Vo corresponding to avalanche breakdown of the bulkp+n junction. For this reason, very high voltage gain throughout a wide range of VD is not uncommon in the HFT. High field triodes exhibiting gains of 200 out to device voltages of 150 V and more have already been reported.(s) Since the effective “doping” on the high resistivity region underneath the gate is quite high due to charge induced by the intense gate field, the actual gate width needed at the surface of the HFT may be on the order of microns even though the depletion width inside the bulk on the high resistivity side widens distances on order mils at high values of Vo. Thus, the small gate area needed to effect gain through high values of Vo makes the HFT attractive for medium frequency, high “mu” applications. Theoretical calculation of the speed of the HFT (equation (10)) indicates that the device is slower by a factor of about W than the equivalent surface transistor fabricated on an insulating substrate. Recent experimental results have verified the implications of equation (ll), namely, that the speed of the HFT can be markedly increased by decreasing the oxide thickness in the device. Devices fabricated with 100 A oxides have displayed values of transconductance and input capacitance consistent with nanosecond risetimes. However, in most practical cases, W,,, is limited to a minimum of about 500 A. With a CO consistent with tunneling, the factor “9” is about 0.05 which is too low for a device intended for high frequency operation. 6. CONCLUSIONS

The speed of a high field insulated-gate tunneling device has been shown to be inherently lower

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363

than the speed of the regular insulated-gate transistor due to high values of threshold voltage and strong substrate pinch-off. The amplification factor of the structure, however, has been shown to be inherently quite high, indicating that the device may possess considerable potential in the medium frequency range once the causes of drift are brought under control. In any case, a recognition of the interplay between voltage gain, bandwidth and substrate resistivity in this high field triode may result in a better understanding of insulatedgate surface-controlled devices. Acknowledgements-The author would like to thank A. G. JORDAN, N. A. JORDAN and J. R. SZEDON of our laboratories and C. GOLDBERGnow at Bell Laboratories, New Jersey, for many helpful and stimulating discussions. In addition, the author would like to thank W. NEWELL for a critical reading of the manuscript, and acknowledge the assistance of L. R. SULAK and E. A. HALCAS during the experimental portion of this work. REFERENCES 1. D. KAHNG and M. M. ATALLA, (1960) Solid State Device Research Conf, Pittsburgh, Pa. 2. P. K. WEIMER, Proc. Inst. Radio Engrs. 50, 1462 (1962). 3. S. R. HOFSTEIN and F. P. HEIMAN, Proc. Inst. Elect. Electron. Engrs. 51, 1190 (1963). 4. H. K. J. IHANTOLA and J. L. MOLL, Solid-State Electron. 7, 423 (1964). 5. W. SHOCKLEYand W. W. HOOPER, (1964) Solid State Device Research Conf, Boulder, Colorado. 6. C. G. B. GARRETT and W. H. BRATTAIN, J. Appl. Phys. 27, 299 (195.5). 7. M. M. ATALLA,. I. M. Ross and F. SMMITS,U.S. Patent No. 3.045.129 (1963). 8. H. C. NATHAN~ON,‘J. R: SZE~ON and N. A. JORDAN (1963) Electron Devices Meeting, Washington, D.C. 9. F. LEUENBERGER,J. Appl. Phys. 33, 2911 (1962). 10. W. L. BROWN, Phys. Rev. 91, 518 (1953). 11. W. SHOCKLEE., Proc. Inst. Radio Engrs. 40, 1365 (1952). 12. K. LEHOVEC, A. SLOBODSKOYand J. L. SPRAGUE, Phys. Stat. Solidi 3, 447 (1963). 13. D. GREEN and H. C. NATHANSON,PYOC. Inst. Electron. Engrs. (to be published). 14. T. H. YEH, J. Appl. Phys. 33, 2849 (1962). 15. S. R. HOFSTEIN, (private communication).