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A high output swing current-steering DAC using voltage controlled current source
Microelectronics Journal 68 (2017) 32–39
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A high output swing current-steering DAC using voltage controlled current source Qinjin Huanga,b,c, Fengqi Yua,b,c, a b c
MARK
⁎
Shenzhen Institutes of Advanced Technology, Chinese Academy of Sciences, Shenzhen University Town, 1068 Xueyuan Avenue, Shenzhen, China University of Chinese Academy of Sciences, Beijing, China Institute of Microelectronics of Chinese Academy of Sciences, Beijing, China
A R T I C L E I N F O
A B S T R A C T
Keywords: Digital-to-analogue converter (DAC) Voltage-controlled-current-source (VCCS) Single supply Single-ended voltage
As the supply voltage decreasing to near 1 V, the output swing of the CS-DAC (current-steering digital-to-analogue converter) is limited by the minimum biasing voltage of the current source array, which is approximately 0.4 V. This voltage takes one-third of the 1.2 V power supply, which makes the single-ended CS-DAC not practical. To eliminate the output swing limitation, a voltage-controlled current source (VCCS) is proposed to realize high-swing single-ended voltage output for CS-DAC. The VCCS has the same input voltage as the biasing voltage. It generates a matching output current to make the minimum output voltage of the single-ended CS-DAC be able to reach the ground. The VCCS adopts a cascode structure in the output path, thus its performance is independent of DAC output changes. Careful matching is made inside VCCS, as well as between VCCS and DAC. Consequently, this design is robust to the process, supply voltage, and temperature (PVT) variations. The proposed CS-DAC, implemented by 180-nm CMOS technology, has a 1 V output swing under 1.25–1.5 V power supply at 25 °C temperature. For all PVT variation corners, the measured minimum DAC output voltage, designed as 0.11 V, varies between 0.05 V and 0.113 V. The measured DNL and INL are normally less than 0.2 LSB and 0.5 LSB, respectively. The measured slewing time for rising and falling step input are 80 ns and 90 ns, respectively. The measured total power consumption is 1.5 mW.
1. Introduction Battery powered equipment generally demands single-supply-rail devices. These single-supply-rail devices have single-ended signal port rather than differential port. At the same time, supply voltage is declining to 1.5 V, and even to near 1 V. When the supply voltage is low, it is critical for single-ended voltage in/out ports to have high-swing or full-swing range, otherwise the signal swing is too small. Besides, power consumption is a key parameter for portable systems. As an important interface device, DACs operating at low power supply voltage with high-swing and low-power consumption are one of the research focuses. To generate high-swing single-ended voltage output, resistor-string DAC (RS-DAC) is commonly used [1–3]. The conventional structure of RS-DACs is shown in Fig. 1(a). The RS-DACs have advantages including monotonicity, low power, and full output range from ground to reference voltage. It is applicable for low-resolution and low-speed applications. However, for resolution greater than 10-bit, the voltage-select switches and the resistor units grow exponentially with the resolution number, leading to a large RC delay and a large die size. As a ⁎
Corresponding author. E-mail addresses: [email protected] (Q. Huang), [email protected] (F. Yu).
http://dx.doi.org/10.1016/j.mejo.2017.08.014 Received 14 June 2016; Received in revised form 11 July 2017; Accepted 29 August 2017 0026-2692/ © 2017 Elsevier Ltd. All rights reserved.
result, RS-DACs are used in speed lower than several mega samples per second, not available in higher resolution and higher speed applications. Comparing to RS-DACs, current-steering digital-to-analogue converters (CS-DACs) are naturally appropriate for high-resolution and high-speed applications. This is because current source has fast charging speed, small switching-delay, and independent of the number of bits of DAC. To achieve high-speed, CS-DACs are commonly configured in differential scheme, as shown in Fig. 1(b) [4]. In this way the differential CS-DAC's speed is not limited by the output amplifier. When CS-DAC is adopted in single-end applications, each of the differential outputs is available for single-ended voltage output. For single-ended voltage output, there exist two problems. One is its linearity performance suffering from finite output resistance of the current source unit [4]. The other is that the output swing is limited because the minimum saturation voltage of current source unit cannot be neglected under single power supply around 1 V. The first problem, limited output resistance, can be resolved traditionally by adding an operational amplifier at the output, together with a feedback resistor, as shown in Fig. 1(c). In this way the voltage at the
Microelectronics Journal 68 (2017) 32–39
Q. Huang, F. Yu
Fig. 1. Traditional single-ended DAC. (a) The conventional structure of RS-DACs. (b) The CS-DACs driving resistant load without output amplifier. (c) The CS-DACs driving load by a single-ended output amplifier.
The rest of the paper is organized as follows. In Section 2, swing limitation of single-ended voltage-output CS-DAC is discussed. Section 3 describes the design of the proposed high-swing DAC. The measurements, together with comparison among state-of-art full-swing DACs, are presented in Section 4. Finally the conclusions are given.
output of current-steering array is constant so that its linearity improves. This configuration is applicable for medium speed applications because the OP generally operates at lower speed than that of the current-steering array. Although CS-DAC with OP reaches compromise between speed and linearity, it is still hardly used in the applications demanding single-ended voltage output under low supply voltage [1]. The reason is that it still suffers from swing limitation [2]. The second problem, limited output swing, is more crucial for low voltage applications and causes great attention. Przyborowski and Idzik adopted an extra current mirror with traditional current-steering array and output-amplifier to eliminate the swing limitation and accomplish a high-swing output for single-ended voltage-output CS-DAC [5]. In their work, the extra current mirror is used to change the current direction from sourcing to sinking when the most-significant-bit (MSB) switches. However the current mirror has a limitation of a small current range which was 0.05 mA in their work. In addition, it introduces two problems. One is the possible mismatch of the extra current mirror in the MSB, leading to more stringent matching requirement. The other is that the current mirror decreases the full-scale switching speed because of the extra settling time caused by full current swing in the current mirror. Therefore the full-swing CS-DAC with an extra current mirror is mainly suitable for low-speed (< 1 MHz) applications. Park and Song proposed a full-swing CS-DAC consisting of a PMOS and a NMOS current source array, with a quaternary driver and without using output amplifier [6]. So it has a pro of high speed (up to 1 GHz). However it has two shortcomings. One is that the two current source arrays double not only the die size, but also the power consumption. The other is the mismatch and inconsistency between the two current source arrays. So the full-swing CS-DAC with a quaternary driver is generally used in high-speed (up to hundreds MHz) and high-power (> tens mW) applications. To resolve the problem of limited output swing of the traditional CSDAC with output-amplifier, as shown in Fig. 1(c), we propose a VCCS to generate a biasing current which directly eliminates the effect of the bias voltage for current source array. The proposed CS-DAC achieves high-swing output voltage by adding a small amount of power consumption and die area. Robustness has been considered in our proposed design. The extra VCCS do not affect the nonlinearity and dynamic performance of the previous CS-DAC. The main contribution of our work is to fill the gap between high-power high-speed CS-DAC and lowpower low speed one, i.e. for the applications of medium speed (up to tens MHz) and relative low power (1–2 mW). To the best of our knowledge, we have found very few publications on such topic.
2. Swing limitation of single-ended voltage-output CS-DAC Single-ended voltage-output CS-DAC generally adopts the scheme shown in Fig. 1(c). In this scheme, the output operational amplifier (OP) and feedback resistor are used as I-V converter and drive the load. The feedback resistor RFB and the current steering block connect to the negative input VNO of the OP. The positive input voltage VP of the OP is a bias voltage that sets the current sources in saturation region. In this way, VP defines the minimum output voltage of the DAC which is given in Eq. (1).
VOUT = IU × (2N − 1 × bN − 1 + 2N − 2 × bN − 2 + …+2 × b1 + b0) × RFB + VP (1) For two-transistor-cascode current source, the minimum biasing voltage VP is two times of the overdrive voltage, approximately 0.4 V in 180 nm CMOS technology. In other words, the minimum output voltage of CS-DAC is 0.4 V [9]. It is about one-third of the supply voltage which is around 1.2 V. Consequently, the single-ended CS-DAC is not practical for such applications. To solve this problem, we propose a technique to lower the minimum output voltage to accomplish a high-swing CS-DAC. 3. The proposed high-swing DAC In this section, a high-swing DAC is proposed. We will discuss the architecture of the high-swing CS-DAC with a VCCS. In addition, the design detail of the VCCS will be described and its mismatch will be analyzed. 3.1. Architecture To expand the swing range of single-ended voltage-output CS-DAC, this paper adopts a VCCS to generate a biasing current IB. This current is injected into the negative input node of the amplifier and the difference between IB and IO flows through the feedback resistor, as shown in Fig. 2. In this way, a voltage drop is generated from VNO to VOUT. This voltage drop is designed to match the biasing voltage VP of the currentsteering sources. When they match accurately, the minimum output 33
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The last part is composed of R1, R2 and Mp3. R1 and R2 generate a divided voltage V1, whose value is set by the ratio R1:R2 = 9:1. The gate of the cascode transistor Mp3 is connected to V1. Mp2 and Mp3 are kept in saturation region by V1 and VNO. The drain of Mp3 is the current output terminal for IB. Because of cascode structure, Mp3 keeps Mp2 away from the effect of VNO fluctuation. As a result, current IB is little affected by the variation of steering current. With input VP, the VCCS generates an output current IB. The current IB is injected into node VNO and flows through RFB. Combining (2)–(4), we have
R VOUT MIN = VP − IB × RFB = VP × ⎛1 − FB ⎞ RM ⎠ ⎝ ⎜
voltage of VOUT can be as low as the ground. As a result, the swing range is extended and high-swing output is realized. The high-swing output can be expressed as
VOUT = IU × (2N − 1 × bN − 1 + 2N − 2 × bN − 2 + …+2 × b1 + b0) × RFB + VP (2)
In (2), VP-IB × RFB is zero for an ideal situation. The value of VP-IB × RFB is affected by IB. To reduce the error at VOUT brought by the variation of IB, it is vital to keep IB as the required constant when the DAC output changes. IB is required settle fast enough when the output changes. In addition, it is critical to keep the variation of IB, namely, the variation of VP-IB × RFB small over PVT variation, which is challenge in the design. 3.2. Voltage-controlled-current-source To resolve the IB fluctuation caused by steering-current IO changes, we adopt cascode structure in the path. To deal with PVT variations, we carefully consider the matching. The VCCS schematic, which consists of three parts, is shown in Fig. 3. The first part consists of an operational amplifier OP1, Mn1 and RM. The positive input of OP1 is VP which is approximately equal to VNM since open-loop-gain of OP1 is large. IB0 is generated by the first part and expressed as
3.3. Mismatch analysis As discussed above, three pairs of elements in Fig. 3, Mp1 and Mp2, RFB and RM, R1 and R2, need matching consideration. Their mismatch effect is analyzed as following. The mismatch between RFB and RM, as well as the mismatch between transistors Mp1 and Mp2, affect the actual value of minimum output voltage. If the intended values are RFB and RM, IB and IB0, and the actual values are rFB and rM, iB and iB0, then the mismatch δR and δI equal to
(3)
IB0 = VP / RM
The second part is a current mirror formed by identical transistors Mp1 and Mp2. As a result, (4)
IB0 = IB
(5)
Eq. (5) indicates that the ratio between RFB and RM determines VPIB×RFB. In real implementation, VP-IB×RFB is determined not only by the matching between RFB and RM, the matching between transistors Mp1 and Mp2, but also by the non-ideality of the OP. As discussed above, three pairs of elements in Fig. 3, Mp1 and Mp2, RFB and RM, R1 and R2, need matching consideration. For better matching, the layouts are in a common centroid scheme. The operational amplifier OP1 in VCCS determines the input character of the VCCS. The input stage of the OP1 consists of a PMOS differential pair with an NMOS current mirror load and a PMOS tail current source. Its output stage consists of an NMOS diode-connected load and a PMOS common-source amplifier. The maximum common-mode input voltage of the OP1 can be expressed as Vdd–VGS–VOVERDRIVE which is about 0.6 V for 1.2 V supply. So the input (VP) range of VCCS is from 0 to 0.6 V, can cover the bias voltage VNO of the current steering block, as shown in Fig. 3, which is 0.4 V. The gain of the OP1 affects the validation of Eq. (5). Since the output of the OP1 is around 1 V, for a 40 dB gain, the input voltage difference between VP and VNM of OP1 must be less than 10 mV which is 2.5% of Vp (i.e. 0.4 V). The gain of this two-stage OP1 is 49 dB so that the approximation of Eq. (5) holds.
Fig. 2. Block diagrams of the proposed single-ended CS-DAC with VCCS.
− IB × RFB
⎟
δR =
rFB / rM −1 RFB / RM
(6)
δI =
iB −1 iB0
(7)
Combines (2)–(7) to computes the actual VOUT_MIN with mismatch.
R VOUT MIN actual = VP − iB × rFB = VP × ⎛1 − FB ⎞ (1 + δR)(1 + δI ) RM ⎠ ⎝ ⎜
⎟
(8)
The inaccuracy of an on-chip resistors can be as much as ± 20% to 30%. However the mismatch ratio between two similar components can be controlled to be better than ± 1% generally, and in many cases, to be better than ± 0.1% [16]. From Eq. (8), one can see that the proposed CS-DAC avoids using single resistor and current, instead using two resistance ratio or current ratio. Even though we choose a relative large mismatch ratio of ± 1%, the deviation of VOUT_MIN is about ± 2%, i.e. 2 mV of 100 mV. So the mismatch has very little effect on the swing range of the CS-DAC. The mismatch between R1 and R2, affects the gate bias voltage V1 of cascode transistor Mp3. With the power supply from 1.2 to 1.5 V, a mismatch ratio of ± 1% causes about 1–2 mV deviation, which does
Fig. 3. The schematic diagram of VCCS in CS-DAC.
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not affect the proper bias condition of the cascode scheme in all PVT corners. 3.4. Current-steering DAC The CS-DAC consists of latches, thermometer encoder, and current steering block. Two stages of latches are adopted. The first stage is the input latches which hold the input data. The second stage is inserted between thermometer encoder and the current-steering switches. It synchronizes the encoded signals to improve dynamic performance of CS-DAC. The CS-DAC employs unary selection strategy which uses thermometer coding. Comparing with binary selection, the unary selection presents better linearity, as well as better dynamic performance. The unary selection is implemented by thermometer encoder which includes row/column 3–8 thermo-encoder and matrix encoders [7]. The current array is built by 64 unary current sources. An INL yield model is used to design the minimum size of current source transistor [8].
σ (I ) ≤ I
(WL)min
Fig. 4. The schematic of OP.
1 2N + 2 *C 2 2 4AVT ⎤/2 ⎛ σ (I ) ⎞ = ⎡Aβ2 + 2⎥ ⎢ V − V I ( ) GS T ⎦ ⎝ ⎠ ⎣
(6′)
constant in the common-mode input range [11]. In addition its offset is greater than that of a PMOS pair. Therefore a PMOS pair input stage is chosen when the input signal is in the common-mode voltage range. R1 together with R2/M13/M14/M15, are used to bias the output transistor M16/M17. Resistor R1 is designed to compromise the value of the gate voltage of M5/M6 and the drain-source voltage of M5/M7. Considering the current mirror characteristic, R1 is adjusted to make the gate voltage of M5/M6 properly biased and make the drain-source voltage of M5/M7 be the same as that of M6/M8. With a feedback resistor RFB, the output amplifier is used as an I-toV converter. A full-scale current pulse IO may drive the amplifier into slew-limitation or into an overload condition, causing excessive distortion. To obtain better pulse response of the CS-DAC circuit, a feedback capacitor CFB is added in parallel with the feedback resistor RFB, as shown in Fig. 2 [12]. The output amplifier of Fig. 4 has a gain of 68 dB, a gain-bandwidthproduct of 28.6 MHz and a phase margin of 85 degree for 1 pF capacitor load. It consumes 416 μA static current.
(7′)
In Eq. (6), for a yield of 99.5%, coefficient C is about 3.2. Resolution N is 6. In Eq. (7), the technology mismatch parameters AVT2 and Aβ2 are provided by the foundry. The overdrive voltage (VGS-VT) is chosen as 0.2 V. The minimum active area of an current source is calculated as (WL)min ≈ 12.35 µm2. After the transistor size has been determined, its width and length are calculated by a given overdrive voltage and the current, shown in Eq. (8). In this design, the total current is 5 mA. For 6-bit accuracy, the unary current is 7.94μA.
W /L =
1 μ *Cox *(VGS − VT )2 / I 2 2 n
(8′)
The ratio W/L of current source transistor is about 1/3.9. With value of (WL)min and W/L, the current source dimensions are W = 1.78 µm and L = 6.94 µm. The current-steering DAC adopted the scheme similar to Fig. 1(c). The current source unit is implemented by cascode structure to improve the parallel resistance. Diode-connected transistor is used as load in each sw path of the switch array [9]. In this way the voltage fluctuation is dramatically reduced comparing to only one load ZDM for all switch paths, as shown in Fig. 1(c).
4. Measurement and analysis The die micrograph is shown in Fig. 5. The core die size is 0.2 mm*0.6 mm. The proposed CS-DAC prototype is implemented using Global Foundry standard 180-nm CMOS technology. To test the proposed CS-DAC, a FPGA with 50 MHz clock is used to generate input data sequence. A 6½-digit performance digital-multimeter (DMM), Keysight-34461A, has been used to measure the static output voltage. The DAC has a resolution of 6 bits. The feedback resistance is 2 KΩ. The total steering current IO is 500 μA. The unary current ILSB is 7.94 μA. Bias voltage VP is 400 mV. The minimum DAC output voltage is designed to be about 0.11 V. The ratio RFB:RM is set to be 11:8. The total power consumption of the CS-DAC is 1.5 mW for 1.35 V power supply. The power consumption of VCCS is 0.472 mW, while the current
3.5. Output amplifier For voltage output CS-DAC with an output OP, the maximum speed of the CS-DAC is largely limited by the OP. For a large-signal step response, the settling time of OP, as the reciprocal of speed, is determined by its internal transition speed, output driving strength, and the zeros/ poles location [10]. The settling time of OP is the sum of slewing time and small signal settling time. Smaller slewing time requires more power consumption to increase the internal transition speed and output driving strength. Reasonable small-signal settling time demands effective design of zeros/poles location to compromise the gain-bandwidth and the phase margin. Therefore, designing low-power low-voltage OP with fast speed is a challenge. The circuit configuration for the OP is shown in Fig. 4. The OP comprises a folded cascode input stage and a class AB output stage. The input transistor pair (M1–M4) and the cascode mirror (M5-M14, R1, R2) builds the input stage. The input stage adopts a PMOS differential input pair, rather than PMOS and NMOS pairs which aim at rail-to-rail input. A drawback of the rail-to-rail input stage is that the gm is not a
Fig. 5. The core die micrograph of the proposed CS-DAC with VCCS.
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Fig. 6. DC characteristic of VCCS: (a) The measured output current IB versus input voltage VP of VCCS, (b) The measured output current IB versus output voltage VNO of VCCS.
VCCS's IB to the output steering current Io of DAC is critical for the DAC performance. To improve the settling time of IB, the cascode structure is used. Fig. 7 indicates that without cascode transistor the settling time of IB is greater than 60 ns. While with cascode transistor the settling time of IB is about 5 ns. Therefore the speed of high-swing DAC with VCCS would not be limited by VCCS for up to 200 MHz. In Fig. 8(a), the minimum output voltage of CS-DAC without VCCS is limited by 0.4-V biasing voltage of current-source. While with the VCCS, the minimum output is 0.1 V as designed. By lowering the minimum output to near ground, the proposed single-ended voltage output CS-DAC realizes a high swing, 0.1–1.1 V, under a 1.25-V supply. In Fig. 8(b), the DNLs of CS-DAC with and without VCC are both around 0.05 LSB. The INL are both around 0.3 LSB. The DNL and INL of CS-DACs with and without VCCS change little. In other words, the VCCS has little effect on the linearity of the CS-DAC. In addition, in Fig. 8(c), the simulated SFDR of CS-DAC with VCCS is compared with that of CS-DAC with ideal current reference instead of VCCS, where the sampling frequency is 50 MHz, the signal frequency up to 11 MHz and the load capacitance 1 pF. Their simulated SFDR decrease with the increasing frequency due to the limited speed of low-power output amplifier. Their SFDRs are almost the same. It means that in mediumspeed low-power applications the VCCS do not affect the dynamic performance of CS-DAC. Fig. 9 shows the minimum and maximum of the CS-DAC output in all PVT corners. The minimum output voltage value is set by VP-IB × RFB which is near zero, so it is important to minimize its variation over all PVT corners. Especially it cannot be lower than zero, otherwise it could be limited to the ground. Fig. 9 shows that the typical lowest output voltage of the DAC is 106 mV, under 1.35-V supply and temperature 20 °C. The measured minimum lowest-output-voltage is 50 mV under 1.5-V and 80 °C. The variation of the lowest output voltages is 63 mV for all PVT corners. The value of the lowest output voltage is small because careful matching is made inside VCCS, as well as between VCCS and DAC. Fig. 9 shows that the typical DAC's highest-outputvoltages is 1050 mV, under 1.35-V and 20 °C. The measured maximum highest-output-voltages is 1220 mV, under 1.2-V and 80 °C. The variation of DAC's highest-output-voltage is 363 mV for all PVT corners. The main reasons of the variation of DAC's highest-output-voltage are the linearity between the metal-resistance and the temperature, and the highest-output-voltage is not compensated by matching. The chip 1–5 in Fig. 9 are five dies randomly selected for the process variation test. Fig. 10 shows the measured full-swing pulse response with capacitor load 12 pF under different supply-voltages and temperature 25 °C. The rising time of the pulse response is 80 ns for rising from 10% to 90% and 90 ns for falling from 90% to 10%. When supply voltage changes, the response time varies by several ns. Fig. 11 shows the measurements of the DNL and INL of the CS-DAC for different supply voltages and different temperatures. The typical
steering block and output amplifier consume 1.03 mW. The power supply can be as low as 1.25 V with normal 1.35 V. Temperature variation is from −40 ℃ to 80 ℃. The CS-DAC requires the VCCS with a linear trans-conductance, a large enough output resistance, and fast enough dynamic response of its output. Three measurement results, Fig. 6(a), Fig. 6(b), and Fig. 7, show that the designed VCCS fulfills the CS-DAC requirement, as discussed below. Fig. 6(a), the measured VP-IB, confirms the VCCS input range and its linearity of IB to VP. The trans-conductance of VCCS is determined by the relationship between the input voltage VP and output current IB. The VP - IB performance is largely limited by the OP1 in VCCS. The input stage of the OP1 consists of a PMOS differential pair. From Section 3.2, the input range of VCCS is designed from 0 to 0.6 V. Fig. 6(b) presents the measured output characteristic VNO-IB. The VNO-IB relationship is determined by the output path of the current mirror in VCCS. The maximum output voltage VNO is Vdd–2*VOVERDRIVE which is approximately 0.8 V for 1.2 V supply. The measured output resistance of VCCS is greater than 1 MΩ when VNO is around 0.4 V. In other words, the error of output current IB is less than 0.1 μA if a 0.1 V fluctuation of VNO occurs. So the IB error is much smaller than unary current ILSB in our work. If higher resolution is required, gain boost method is recommended to increase the output resistance by insert an amplifier between node V1 and transistor Mp3 [13]. Fig. 7 shows the simulated settling time of output current of VCCS, with and without cascode transistor when total steering-current IO changes from zero to full scale 0.5 mA. Such dynamic response of the
Fig. 7. The settling of VCCS output current IB with and without cascode transistor for the total steering-current IO being between zero and full scale.
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Fig. 8. (a) Measured full scale input vs output of CS-DAC with and without VCCS, (b) Measured DNL/INL of CS-DAC with and without VCCS, (c) Simulated SFDR of CS-DAC with VCCS and with ideal current reference instead of VCCS.
DNL and INL are less than 0.2 and 0.5 LSB, respectively, except for 1.25-V supply and temperature 80 °C. The maximum DNL and INL, 0.7 and 1.6 LSB, respectively, happens at 1.25-V supply and temperature 80 °C. For 1.25-V supply and temperature 80 °C, the DAC's highestoutput-voltage is 1.22 V. As a result the output around highest value is limited by the power-supply and worst nonlinearity. Fig. 12 shows the measured spectrum of the CS-DAC with an input frequency of 35.203 kHz at a 12.5-MS/s update rate, a 1.35-V supply, and 25-°C temperature. The measured SNDR, ENOB and SFDR are 27.91 dB, 4.34 bits and 44 dBc, respectively. To give an overall performance comparison, the figure-of-merit (FOM) including area efficiency is introduced [14]. The larger the FOM, the better the overall performance is.
FOM =
2n × samplingrate area × power
(9)
The area efficiency (AE) is defined in (10) [15]. The smaller the AE, the better area efficiency is.
AE =
area 2ENOB
(10)
Table 1 presents the performance comparison of our work with the state-of-the-art designs of high-swing CS-DACs. These DACs were implemented based on current-steering architecture, and all have highswing single-ended voltage output. For the buffered-voltage-output CSDACs, [5] and this work use an output amplifier as a trans-conductance.
Fig. 10. The pulse response of DAC output for capacitor load 12 pF under different supply-voltages and temperature 25 °C. The clock of the input data is 2 MHz, and the pulse width is 1 µs. The output response is measured by an oscilloscope with 2-GSps sampling-rate.
Fig. 9. The minimum and maximum of the CS-DAC output versus process, supply voltage, and temperature.
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Table 1 Comparison of the state of the art designs.
Output Type
Technology Architecture
Resolution SNDR (dB) ENOB (bit) SFDR (dBc) Full scale current (mA) Full scale output voltage (V) Supply Voltage (V) DNL/INL (LSB) Sample rat (MS/s) Power Consumption (mW) Area (mm2) FOM AE
Fig. 11. The measured DNL and INL of the CS-DAC for different supply voltage and different temperature. The input sampling frequency is 40 Hz. The input increases linearly with 1LSB step. The time duration of each input step is about 0.4 s. The value of 1LSB varies from 12 mV to 18 mV in the temperature range. The measurement resolution of DMM was 10 µV.
[5] 2010TNS
[6] 2015TCAS-II
This work
Full-swing (Buffered Voltage) 0.35 µm CMOS current steering + amplifier 10 – – – 0.05 2.5
Full-swing (Unbuffered Voltage) 0.11 µm CMOS current steering + output selector 6 35 5.52 43 1.65 3.2
Full-swing (Buffered Voltage) 0.18 µm CMOS
3.3 0.42/0.42 0.5 0.6
Digital: 1.2 Analogue: 3.3 0.7/0.7 1000 19.1
0.18 4.74e3 –
0.46 7.28e3 1002
current steering + amplifier 6 27.91 4.34 44 0.5 1 1.25 to 1.5 0.05/0.33 20 1.5 @1.35 V supply 0.12 7.11e3 593
The label “–” means parameters not given in the reference. Spectrum test was carried with a input frequency of 35.203 kHz at a 12.5-MS/s update rate, a 1.35-V supply and 25-°C temperature.
the area in [5] can be reduced by approximately half. Even though [5] uses 0.35 µm technology to design a 10-bit DAC, its area is a little larger than our work and quite smaller than that in [6]. So the die area of [5] is the best, while the area efficiency of [6] is the worst. 5. Conclusion Fig. 12. The measured spectrum of the CS-DAC with a 35.203-KHz signal and a 12.5-MS/ s update rate.
This work has presented a technique to improve the output voltage swing of a single-ended CS-DAC under low supply voltage. By using a VCCS, the minimum DAC output voltage can reach approximately zero. Therefore the proposed CS-DAC achieves almost rail-to-rail single-end voltage output by adding a small amount of power and die area. Furthermore, careful matching has been made inside VCCS, as well as between VCCS and DAC. Therefore the minimum output voltage is arithmetically controllable and robust to PVT variations. Simulation and measurement show that the linearity and dynamic performance of our proposed CS-DAC is not limited by the VCCS. The proposed high-swing single-end voltage output CS-DAC is particularly suitable for the applications of low supply voltage, medium speed (up to tens MHz), and relative low power (1–2 mW).
They have a better drive strength but a worse dynamic linearity than the unbuffered CS-DAC. The SNDR of this work is less than that of [6], mainly because the output amplifier introduces more distortion in a wide frequency range. The full-scale output voltage range depends on the voltage margin at VDD and ground side, which directly affects the voltage distortion. With the same supply voltage, the unbuffered scheme in [6] needs less top or ground voltage margin than the buffered ones. Therefore the supply voltage range utilization for output swing of the former is higher. Table 1 reflects the relationship between power and speed. The higher the sampling rate, the more power consumption is required. The CS-DAC in [5] aims at low-power low-speed application, while the one in [6] is for high-speed applications with high power. This work proposes an alternative high-swing solution for medium speed applications with relative low power. To make a fair performance comparison, the FOM can be served as an estimate of overall performance of a design [14]. The FOM of [5] is least, so its overall performance is the worst in the three. The FOM of our work is almost the same as that of [6]. It means the overall performance of our work and [6] are similar. Our work makes reasonable trade-off among speed, power, and area for the applications of low supply voltage and medium speed. As for [6], it aims at high-speed applications; its high-speed merit compensates for its poor area efficiency. The area efficiency of our work is better than [6] because the AE in [6] is larger than that of ours, as seen in Table 1. The reason is that in [6] both PMOS and NMOS current source array are used, resulting in double die area. By using an extra current mirror in the MSB switching,
Acknowledgments This work was supported in part by National key R & D plan (grant number 2016YFC0105002 and 61674162), Shenzhen Key Lab for RF Integrated Circuits, Shenzhen Shared Technology Service Center for Internet of Things, Guangdong government funds (grant numbers 2013S046 and 2015B010104005), Shenzhen government funds (grant numbers JCYJ20160331192843950 and CXZZ20150601160410510), and Shenzhen Peacock Plan. References [1] T.I. Incorporated. Products for digital to analog converter. Available: 〈http://www. ti.com/lsds/ti/data-converters/digital-to-analog-converter-products.page〉, 2016. [2] R. Pierco, G. Torfs, J. Verbrugghe, B. Bakeroot, J. Bauwelinck, A 16 channel high-
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[3]
[4] [5] [6]
[7] [8]
[9] B. Ma, Q. Huang, F. Yu, A 12-bit 1.74-mW 20-MS/s DAC with resistor-string and current-steering hybrid architecture, in: proceedings of the 28th IEEE International System-on-Chip Conference (SOCC), 2015, 2015, pp. 1–6. [10] P.E. Allen, D.R. Holberg, CMOS Analog Circuit Design, Second Edition, 2011. [11] R. Hogervorst, J.P. Tero, R.G.H. Eschauzier, J.H. Huijsing, A compact power-efficient 3 V CMOS rail-to-rail input/output operational amplifier for VLSI cell libraries, IEEE J. Solid-State Circuits 29 (1994) 1505–1513. [12] W. Kester, 3 - Buffering DAC Analog Outputs - Data Conversion Handbook - Section 6, Data Conversion Handbook, (2005), pp. 415–422. [13] W.M.C. Sansen, Analog Design Essentials, Springer, 2006. [14] X. Wu, P. Palmers, M.S.J. Steyaert, A 130 nm CMOS 6-bit full Nyquist 3 GS/s DAC, IEEE J. Solid-State Circuits 43 (2008) 2396–2403. [15] R. Dai, Y. Zheng, Z. Wang, H. Zhu, W. Kong, S. Zou, A 10-bit 2.5-MS/s SAR ADC with 60.46 dB SNDR in 0.13-μm CMOS technology, Analog Integr. Circuits Signal Process. 80 (2014) 255–261. [16] A. Hastings, The Art of Analog Layout, 2th ed., Prentice Hall, 2006.
voltage driver with 14 bit resolution for driving piezoelectric actuators, Circuits Syst. I: Regul. Pap. IEEE Trans. 62 (2015) 1726–1736. L. Chih-Wen, Y. Ping-Yeh, L. Ying-Ting, A column driver architecture with double time-division multiplexing RDACs for TFT-LCD applications, Solid-State Circuits, IEEE J. 49 (2014) 2352–2364. F. Maloberti, Data Converters, Springer, 2010. D. Przyborowski, M. Idzik, A 10-bit low-power small-area H[2]igh-Swing CMOS DAC, IEEE Trans. Nucl. Sci. 57 (2010) 292–299. P. Geunyeong, S. Minkyu, A CMOS current-steering D/A converter with full-swing output voltage and a quaternary driver, Circuits Syst. II: Express Briefs IEEE Trans. 62 (2015) 441–445. T. Miki, Y. Nakamura, M. Nakaya, S. Asai, Y. Akasaka, Y. Horiba, An 80-MHz 8-bit CMOS D/A converter, IEEE J. Solid-State Circuits 21 (1986) 983–988. A. Van den Bosch, M. Steyaert, W. Sansen, An accurate statistical yield model for CMOS current-steering D/A converters, in: Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on Circuits and Systems, 2000, vol. 4 2000, pp. 105–108.
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Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
A high output swing current-steering DAC using voltage controlled current source Qinjin Huanga,b,c, Fengqi Yua,b,c, a b c
MARK
⁎
Shenzhen Institutes of Advanced Technology, Chinese Academy of Sciences, Shenzhen University Town, 1068 Xueyuan Avenue, Shenzhen, China University of Chinese Academy of Sciences, Beijing, China Institute of Microelectronics of Chinese Academy of Sciences, Beijing, China
A R T I C L E I N F O
A B S T R A C T
Keywords: Digital-to-analogue converter (DAC) Voltage-controlled-current-source (VCCS) Single supply Single-ended voltage
As the supply voltage decreasing to near 1 V, the output swing of the CS-DAC (current-steering digital-to-analogue converter) is limited by the minimum biasing voltage of the current source array, which is approximately 0.4 V. This voltage takes one-third of the 1.2 V power supply, which makes the single-ended CS-DAC not practical. To eliminate the output swing limitation, a voltage-controlled current source (VCCS) is proposed to realize high-swing single-ended voltage output for CS-DAC. The VCCS has the same input voltage as the biasing voltage. It generates a matching output current to make the minimum output voltage of the single-ended CS-DAC be able to reach the ground. The VCCS adopts a cascode structure in the output path, thus its performance is independent of DAC output changes. Careful matching is made inside VCCS, as well as between VCCS and DAC. Consequently, this design is robust to the process, supply voltage, and temperature (PVT) variations. The proposed CS-DAC, implemented by 180-nm CMOS technology, has a 1 V output swing under 1.25–1.5 V power supply at 25 °C temperature. For all PVT variation corners, the measured minimum DAC output voltage, designed as 0.11 V, varies between 0.05 V and 0.113 V. The measured DNL and INL are normally less than 0.2 LSB and 0.5 LSB, respectively. The measured slewing time for rising and falling step input are 80 ns and 90 ns, respectively. The measured total power consumption is 1.5 mW.
1. Introduction Battery powered equipment generally demands single-supply-rail devices. These single-supply-rail devices have single-ended signal port rather than differential port. At the same time, supply voltage is declining to 1.5 V, and even to near 1 V. When the supply voltage is low, it is critical for single-ended voltage in/out ports to have high-swing or full-swing range, otherwise the signal swing is too small. Besides, power consumption is a key parameter for portable systems. As an important interface device, DACs operating at low power supply voltage with high-swing and low-power consumption are one of the research focuses. To generate high-swing single-ended voltage output, resistor-string DAC (RS-DAC) is commonly used [1–3]. The conventional structure of RS-DACs is shown in Fig. 1(a). The RS-DACs have advantages including monotonicity, low power, and full output range from ground to reference voltage. It is applicable for low-resolution and low-speed applications. However, for resolution greater than 10-bit, the voltage-select switches and the resistor units grow exponentially with the resolution number, leading to a large RC delay and a large die size. As a ⁎
Corresponding author. E-mail addresses: [email protected] (Q. Huang), [email protected] (F. Yu).
http://dx.doi.org/10.1016/j.mejo.2017.08.014 Received 14 June 2016; Received in revised form 11 July 2017; Accepted 29 August 2017 0026-2692/ © 2017 Elsevier Ltd. All rights reserved.
result, RS-DACs are used in speed lower than several mega samples per second, not available in higher resolution and higher speed applications. Comparing to RS-DACs, current-steering digital-to-analogue converters (CS-DACs) are naturally appropriate for high-resolution and high-speed applications. This is because current source has fast charging speed, small switching-delay, and independent of the number of bits of DAC. To achieve high-speed, CS-DACs are commonly configured in differential scheme, as shown in Fig. 1(b) [4]. In this way the differential CS-DAC's speed is not limited by the output amplifier. When CS-DAC is adopted in single-end applications, each of the differential outputs is available for single-ended voltage output. For single-ended voltage output, there exist two problems. One is its linearity performance suffering from finite output resistance of the current source unit [4]. The other is that the output swing is limited because the minimum saturation voltage of current source unit cannot be neglected under single power supply around 1 V. The first problem, limited output resistance, can be resolved traditionally by adding an operational amplifier at the output, together with a feedback resistor, as shown in Fig. 1(c). In this way the voltage at the
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Fig. 1. Traditional single-ended DAC. (a) The conventional structure of RS-DACs. (b) The CS-DACs driving resistant load without output amplifier. (c) The CS-DACs driving load by a single-ended output amplifier.
The rest of the paper is organized as follows. In Section 2, swing limitation of single-ended voltage-output CS-DAC is discussed. Section 3 describes the design of the proposed high-swing DAC. The measurements, together with comparison among state-of-art full-swing DACs, are presented in Section 4. Finally the conclusions are given.
output of current-steering array is constant so that its linearity improves. This configuration is applicable for medium speed applications because the OP generally operates at lower speed than that of the current-steering array. Although CS-DAC with OP reaches compromise between speed and linearity, it is still hardly used in the applications demanding single-ended voltage output under low supply voltage [1]. The reason is that it still suffers from swing limitation [2]. The second problem, limited output swing, is more crucial for low voltage applications and causes great attention. Przyborowski and Idzik adopted an extra current mirror with traditional current-steering array and output-amplifier to eliminate the swing limitation and accomplish a high-swing output for single-ended voltage-output CS-DAC [5]. In their work, the extra current mirror is used to change the current direction from sourcing to sinking when the most-significant-bit (MSB) switches. However the current mirror has a limitation of a small current range which was 0.05 mA in their work. In addition, it introduces two problems. One is the possible mismatch of the extra current mirror in the MSB, leading to more stringent matching requirement. The other is that the current mirror decreases the full-scale switching speed because of the extra settling time caused by full current swing in the current mirror. Therefore the full-swing CS-DAC with an extra current mirror is mainly suitable for low-speed (< 1 MHz) applications. Park and Song proposed a full-swing CS-DAC consisting of a PMOS and a NMOS current source array, with a quaternary driver and without using output amplifier [6]. So it has a pro of high speed (up to 1 GHz). However it has two shortcomings. One is that the two current source arrays double not only the die size, but also the power consumption. The other is the mismatch and inconsistency between the two current source arrays. So the full-swing CS-DAC with a quaternary driver is generally used in high-speed (up to hundreds MHz) and high-power (> tens mW) applications. To resolve the problem of limited output swing of the traditional CSDAC with output-amplifier, as shown in Fig. 1(c), we propose a VCCS to generate a biasing current which directly eliminates the effect of the bias voltage for current source array. The proposed CS-DAC achieves high-swing output voltage by adding a small amount of power consumption and die area. Robustness has been considered in our proposed design. The extra VCCS do not affect the nonlinearity and dynamic performance of the previous CS-DAC. The main contribution of our work is to fill the gap between high-power high-speed CS-DAC and lowpower low speed one, i.e. for the applications of medium speed (up to tens MHz) and relative low power (1–2 mW). To the best of our knowledge, we have found very few publications on such topic.
2. Swing limitation of single-ended voltage-output CS-DAC Single-ended voltage-output CS-DAC generally adopts the scheme shown in Fig. 1(c). In this scheme, the output operational amplifier (OP) and feedback resistor are used as I-V converter and drive the load. The feedback resistor RFB and the current steering block connect to the negative input VNO of the OP. The positive input voltage VP of the OP is a bias voltage that sets the current sources in saturation region. In this way, VP defines the minimum output voltage of the DAC which is given in Eq. (1).
VOUT = IU × (2N − 1 × bN − 1 + 2N − 2 × bN − 2 + …+2 × b1 + b0) × RFB + VP (1) For two-transistor-cascode current source, the minimum biasing voltage VP is two times of the overdrive voltage, approximately 0.4 V in 180 nm CMOS technology. In other words, the minimum output voltage of CS-DAC is 0.4 V [9]. It is about one-third of the supply voltage which is around 1.2 V. Consequently, the single-ended CS-DAC is not practical for such applications. To solve this problem, we propose a technique to lower the minimum output voltage to accomplish a high-swing CS-DAC. 3. The proposed high-swing DAC In this section, a high-swing DAC is proposed. We will discuss the architecture of the high-swing CS-DAC with a VCCS. In addition, the design detail of the VCCS will be described and its mismatch will be analyzed. 3.1. Architecture To expand the swing range of single-ended voltage-output CS-DAC, this paper adopts a VCCS to generate a biasing current IB. This current is injected into the negative input node of the amplifier and the difference between IB and IO flows through the feedback resistor, as shown in Fig. 2. In this way, a voltage drop is generated from VNO to VOUT. This voltage drop is designed to match the biasing voltage VP of the currentsteering sources. When they match accurately, the minimum output 33
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The last part is composed of R1, R2 and Mp3. R1 and R2 generate a divided voltage V1, whose value is set by the ratio R1:R2 = 9:1. The gate of the cascode transistor Mp3 is connected to V1. Mp2 and Mp3 are kept in saturation region by V1 and VNO. The drain of Mp3 is the current output terminal for IB. Because of cascode structure, Mp3 keeps Mp2 away from the effect of VNO fluctuation. As a result, current IB is little affected by the variation of steering current. With input VP, the VCCS generates an output current IB. The current IB is injected into node VNO and flows through RFB. Combining (2)–(4), we have
R VOUT MIN = VP − IB × RFB = VP × ⎛1 − FB ⎞ RM ⎠ ⎝ ⎜
voltage of VOUT can be as low as the ground. As a result, the swing range is extended and high-swing output is realized. The high-swing output can be expressed as
VOUT = IU × (2N − 1 × bN − 1 + 2N − 2 × bN − 2 + …+2 × b1 + b0) × RFB + VP (2)
In (2), VP-IB × RFB is zero for an ideal situation. The value of VP-IB × RFB is affected by IB. To reduce the error at VOUT brought by the variation of IB, it is vital to keep IB as the required constant when the DAC output changes. IB is required settle fast enough when the output changes. In addition, it is critical to keep the variation of IB, namely, the variation of VP-IB × RFB small over PVT variation, which is challenge in the design. 3.2. Voltage-controlled-current-source To resolve the IB fluctuation caused by steering-current IO changes, we adopt cascode structure in the path. To deal with PVT variations, we carefully consider the matching. The VCCS schematic, which consists of three parts, is shown in Fig. 3. The first part consists of an operational amplifier OP1, Mn1 and RM. The positive input of OP1 is VP which is approximately equal to VNM since open-loop-gain of OP1 is large. IB0 is generated by the first part and expressed as
3.3. Mismatch analysis As discussed above, three pairs of elements in Fig. 3, Mp1 and Mp2, RFB and RM, R1 and R2, need matching consideration. Their mismatch effect is analyzed as following. The mismatch between RFB and RM, as well as the mismatch between transistors Mp1 and Mp2, affect the actual value of minimum output voltage. If the intended values are RFB and RM, IB and IB0, and the actual values are rFB and rM, iB and iB0, then the mismatch δR and δI equal to
(3)
IB0 = VP / RM
The second part is a current mirror formed by identical transistors Mp1 and Mp2. As a result, (4)
IB0 = IB
(5)
Eq. (5) indicates that the ratio between RFB and RM determines VPIB×RFB. In real implementation, VP-IB×RFB is determined not only by the matching between RFB and RM, the matching between transistors Mp1 and Mp2, but also by the non-ideality of the OP. As discussed above, three pairs of elements in Fig. 3, Mp1 and Mp2, RFB and RM, R1 and R2, need matching consideration. For better matching, the layouts are in a common centroid scheme. The operational amplifier OP1 in VCCS determines the input character of the VCCS. The input stage of the OP1 consists of a PMOS differential pair with an NMOS current mirror load and a PMOS tail current source. Its output stage consists of an NMOS diode-connected load and a PMOS common-source amplifier. The maximum common-mode input voltage of the OP1 can be expressed as Vdd–VGS–VOVERDRIVE which is about 0.6 V for 1.2 V supply. So the input (VP) range of VCCS is from 0 to 0.6 V, can cover the bias voltage VNO of the current steering block, as shown in Fig. 3, which is 0.4 V. The gain of the OP1 affects the validation of Eq. (5). Since the output of the OP1 is around 1 V, for a 40 dB gain, the input voltage difference between VP and VNM of OP1 must be less than 10 mV which is 2.5% of Vp (i.e. 0.4 V). The gain of this two-stage OP1 is 49 dB so that the approximation of Eq. (5) holds.
Fig. 2. Block diagrams of the proposed single-ended CS-DAC with VCCS.
− IB × RFB
⎟
δR =
rFB / rM −1 RFB / RM
(6)
δI =
iB −1 iB0
(7)
Combines (2)–(7) to computes the actual VOUT_MIN with mismatch.
R VOUT MIN actual = VP − iB × rFB = VP × ⎛1 − FB ⎞ (1 + δR)(1 + δI ) RM ⎠ ⎝ ⎜
⎟
(8)
The inaccuracy of an on-chip resistors can be as much as ± 20% to 30%. However the mismatch ratio between two similar components can be controlled to be better than ± 1% generally, and in many cases, to be better than ± 0.1% [16]. From Eq. (8), one can see that the proposed CS-DAC avoids using single resistor and current, instead using two resistance ratio or current ratio. Even though we choose a relative large mismatch ratio of ± 1%, the deviation of VOUT_MIN is about ± 2%, i.e. 2 mV of 100 mV. So the mismatch has very little effect on the swing range of the CS-DAC. The mismatch between R1 and R2, affects the gate bias voltage V1 of cascode transistor Mp3. With the power supply from 1.2 to 1.5 V, a mismatch ratio of ± 1% causes about 1–2 mV deviation, which does
Fig. 3. The schematic diagram of VCCS in CS-DAC.
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not affect the proper bias condition of the cascode scheme in all PVT corners. 3.4. Current-steering DAC The CS-DAC consists of latches, thermometer encoder, and current steering block. Two stages of latches are adopted. The first stage is the input latches which hold the input data. The second stage is inserted between thermometer encoder and the current-steering switches. It synchronizes the encoded signals to improve dynamic performance of CS-DAC. The CS-DAC employs unary selection strategy which uses thermometer coding. Comparing with binary selection, the unary selection presents better linearity, as well as better dynamic performance. The unary selection is implemented by thermometer encoder which includes row/column 3–8 thermo-encoder and matrix encoders [7]. The current array is built by 64 unary current sources. An INL yield model is used to design the minimum size of current source transistor [8].
σ (I ) ≤ I
(WL)min
Fig. 4. The schematic of OP.
1 2N + 2 *C 2 2 4AVT ⎤/2 ⎛ σ (I ) ⎞ = ⎡Aβ2 + 2⎥ ⎢ V − V I ( ) GS T ⎦ ⎝ ⎠ ⎣
(6′)
constant in the common-mode input range [11]. In addition its offset is greater than that of a PMOS pair. Therefore a PMOS pair input stage is chosen when the input signal is in the common-mode voltage range. R1 together with R2/M13/M14/M15, are used to bias the output transistor M16/M17. Resistor R1 is designed to compromise the value of the gate voltage of M5/M6 and the drain-source voltage of M5/M7. Considering the current mirror characteristic, R1 is adjusted to make the gate voltage of M5/M6 properly biased and make the drain-source voltage of M5/M7 be the same as that of M6/M8. With a feedback resistor RFB, the output amplifier is used as an I-toV converter. A full-scale current pulse IO may drive the amplifier into slew-limitation or into an overload condition, causing excessive distortion. To obtain better pulse response of the CS-DAC circuit, a feedback capacitor CFB is added in parallel with the feedback resistor RFB, as shown in Fig. 2 [12]. The output amplifier of Fig. 4 has a gain of 68 dB, a gain-bandwidthproduct of 28.6 MHz and a phase margin of 85 degree for 1 pF capacitor load. It consumes 416 μA static current.
(7′)
In Eq. (6), for a yield of 99.5%, coefficient C is about 3.2. Resolution N is 6. In Eq. (7), the technology mismatch parameters AVT2 and Aβ2 are provided by the foundry. The overdrive voltage (VGS-VT) is chosen as 0.2 V. The minimum active area of an current source is calculated as (WL)min ≈ 12.35 µm2. After the transistor size has been determined, its width and length are calculated by a given overdrive voltage and the current, shown in Eq. (8). In this design, the total current is 5 mA. For 6-bit accuracy, the unary current is 7.94μA.
W /L =
1 μ *Cox *(VGS − VT )2 / I 2 2 n
(8′)
The ratio W/L of current source transistor is about 1/3.9. With value of (WL)min and W/L, the current source dimensions are W = 1.78 µm and L = 6.94 µm. The current-steering DAC adopted the scheme similar to Fig. 1(c). The current source unit is implemented by cascode structure to improve the parallel resistance. Diode-connected transistor is used as load in each sw path of the switch array [9]. In this way the voltage fluctuation is dramatically reduced comparing to only one load ZDM for all switch paths, as shown in Fig. 1(c).
4. Measurement and analysis The die micrograph is shown in Fig. 5. The core die size is 0.2 mm*0.6 mm. The proposed CS-DAC prototype is implemented using Global Foundry standard 180-nm CMOS technology. To test the proposed CS-DAC, a FPGA with 50 MHz clock is used to generate input data sequence. A 6½-digit performance digital-multimeter (DMM), Keysight-34461A, has been used to measure the static output voltage. The DAC has a resolution of 6 bits. The feedback resistance is 2 KΩ. The total steering current IO is 500 μA. The unary current ILSB is 7.94 μA. Bias voltage VP is 400 mV. The minimum DAC output voltage is designed to be about 0.11 V. The ratio RFB:RM is set to be 11:8. The total power consumption of the CS-DAC is 1.5 mW for 1.35 V power supply. The power consumption of VCCS is 0.472 mW, while the current
3.5. Output amplifier For voltage output CS-DAC with an output OP, the maximum speed of the CS-DAC is largely limited by the OP. For a large-signal step response, the settling time of OP, as the reciprocal of speed, is determined by its internal transition speed, output driving strength, and the zeros/ poles location [10]. The settling time of OP is the sum of slewing time and small signal settling time. Smaller slewing time requires more power consumption to increase the internal transition speed and output driving strength. Reasonable small-signal settling time demands effective design of zeros/poles location to compromise the gain-bandwidth and the phase margin. Therefore, designing low-power low-voltage OP with fast speed is a challenge. The circuit configuration for the OP is shown in Fig. 4. The OP comprises a folded cascode input stage and a class AB output stage. The input transistor pair (M1–M4) and the cascode mirror (M5-M14, R1, R2) builds the input stage. The input stage adopts a PMOS differential input pair, rather than PMOS and NMOS pairs which aim at rail-to-rail input. A drawback of the rail-to-rail input stage is that the gm is not a
Fig. 5. The core die micrograph of the proposed CS-DAC with VCCS.
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Fig. 6. DC characteristic of VCCS: (a) The measured output current IB versus input voltage VP of VCCS, (b) The measured output current IB versus output voltage VNO of VCCS.
VCCS's IB to the output steering current Io of DAC is critical for the DAC performance. To improve the settling time of IB, the cascode structure is used. Fig. 7 indicates that without cascode transistor the settling time of IB is greater than 60 ns. While with cascode transistor the settling time of IB is about 5 ns. Therefore the speed of high-swing DAC with VCCS would not be limited by VCCS for up to 200 MHz. In Fig. 8(a), the minimum output voltage of CS-DAC without VCCS is limited by 0.4-V biasing voltage of current-source. While with the VCCS, the minimum output is 0.1 V as designed. By lowering the minimum output to near ground, the proposed single-ended voltage output CS-DAC realizes a high swing, 0.1–1.1 V, under a 1.25-V supply. In Fig. 8(b), the DNLs of CS-DAC with and without VCC are both around 0.05 LSB. The INL are both around 0.3 LSB. The DNL and INL of CS-DACs with and without VCCS change little. In other words, the VCCS has little effect on the linearity of the CS-DAC. In addition, in Fig. 8(c), the simulated SFDR of CS-DAC with VCCS is compared with that of CS-DAC with ideal current reference instead of VCCS, where the sampling frequency is 50 MHz, the signal frequency up to 11 MHz and the load capacitance 1 pF. Their simulated SFDR decrease with the increasing frequency due to the limited speed of low-power output amplifier. Their SFDRs are almost the same. It means that in mediumspeed low-power applications the VCCS do not affect the dynamic performance of CS-DAC. Fig. 9 shows the minimum and maximum of the CS-DAC output in all PVT corners. The minimum output voltage value is set by VP-IB × RFB which is near zero, so it is important to minimize its variation over all PVT corners. Especially it cannot be lower than zero, otherwise it could be limited to the ground. Fig. 9 shows that the typical lowest output voltage of the DAC is 106 mV, under 1.35-V supply and temperature 20 °C. The measured minimum lowest-output-voltage is 50 mV under 1.5-V and 80 °C. The variation of the lowest output voltages is 63 mV for all PVT corners. The value of the lowest output voltage is small because careful matching is made inside VCCS, as well as between VCCS and DAC. Fig. 9 shows that the typical DAC's highest-outputvoltages is 1050 mV, under 1.35-V and 20 °C. The measured maximum highest-output-voltages is 1220 mV, under 1.2-V and 80 °C. The variation of DAC's highest-output-voltage is 363 mV for all PVT corners. The main reasons of the variation of DAC's highest-output-voltage are the linearity between the metal-resistance and the temperature, and the highest-output-voltage is not compensated by matching. The chip 1–5 in Fig. 9 are five dies randomly selected for the process variation test. Fig. 10 shows the measured full-swing pulse response with capacitor load 12 pF under different supply-voltages and temperature 25 °C. The rising time of the pulse response is 80 ns for rising from 10% to 90% and 90 ns for falling from 90% to 10%. When supply voltage changes, the response time varies by several ns. Fig. 11 shows the measurements of the DNL and INL of the CS-DAC for different supply voltages and different temperatures. The typical
steering block and output amplifier consume 1.03 mW. The power supply can be as low as 1.25 V with normal 1.35 V. Temperature variation is from −40 ℃ to 80 ℃. The CS-DAC requires the VCCS with a linear trans-conductance, a large enough output resistance, and fast enough dynamic response of its output. Three measurement results, Fig. 6(a), Fig. 6(b), and Fig. 7, show that the designed VCCS fulfills the CS-DAC requirement, as discussed below. Fig. 6(a), the measured VP-IB, confirms the VCCS input range and its linearity of IB to VP. The trans-conductance of VCCS is determined by the relationship between the input voltage VP and output current IB. The VP - IB performance is largely limited by the OP1 in VCCS. The input stage of the OP1 consists of a PMOS differential pair. From Section 3.2, the input range of VCCS is designed from 0 to 0.6 V. Fig. 6(b) presents the measured output characteristic VNO-IB. The VNO-IB relationship is determined by the output path of the current mirror in VCCS. The maximum output voltage VNO is Vdd–2*VOVERDRIVE which is approximately 0.8 V for 1.2 V supply. The measured output resistance of VCCS is greater than 1 MΩ when VNO is around 0.4 V. In other words, the error of output current IB is less than 0.1 μA if a 0.1 V fluctuation of VNO occurs. So the IB error is much smaller than unary current ILSB in our work. If higher resolution is required, gain boost method is recommended to increase the output resistance by insert an amplifier between node V1 and transistor Mp3 [13]. Fig. 7 shows the simulated settling time of output current of VCCS, with and without cascode transistor when total steering-current IO changes from zero to full scale 0.5 mA. Such dynamic response of the
Fig. 7. The settling of VCCS output current IB with and without cascode transistor for the total steering-current IO being between zero and full scale.
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Fig. 8. (a) Measured full scale input vs output of CS-DAC with and without VCCS, (b) Measured DNL/INL of CS-DAC with and without VCCS, (c) Simulated SFDR of CS-DAC with VCCS and with ideal current reference instead of VCCS.
DNL and INL are less than 0.2 and 0.5 LSB, respectively, except for 1.25-V supply and temperature 80 °C. The maximum DNL and INL, 0.7 and 1.6 LSB, respectively, happens at 1.25-V supply and temperature 80 °C. For 1.25-V supply and temperature 80 °C, the DAC's highestoutput-voltage is 1.22 V. As a result the output around highest value is limited by the power-supply and worst nonlinearity. Fig. 12 shows the measured spectrum of the CS-DAC with an input frequency of 35.203 kHz at a 12.5-MS/s update rate, a 1.35-V supply, and 25-°C temperature. The measured SNDR, ENOB and SFDR are 27.91 dB, 4.34 bits and 44 dBc, respectively. To give an overall performance comparison, the figure-of-merit (FOM) including area efficiency is introduced [14]. The larger the FOM, the better the overall performance is.
FOM =
2n × samplingrate area × power
(9)
The area efficiency (AE) is defined in (10) [15]. The smaller the AE, the better area efficiency is.
AE =
area 2ENOB
(10)
Table 1 presents the performance comparison of our work with the state-of-the-art designs of high-swing CS-DACs. These DACs were implemented based on current-steering architecture, and all have highswing single-ended voltage output. For the buffered-voltage-output CSDACs, [5] and this work use an output amplifier as a trans-conductance.
Fig. 10. The pulse response of DAC output for capacitor load 12 pF under different supply-voltages and temperature 25 °C. The clock of the input data is 2 MHz, and the pulse width is 1 µs. The output response is measured by an oscilloscope with 2-GSps sampling-rate.
Fig. 9. The minimum and maximum of the CS-DAC output versus process, supply voltage, and temperature.
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Table 1 Comparison of the state of the art designs.
Output Type
Technology Architecture
Resolution SNDR (dB) ENOB (bit) SFDR (dBc) Full scale current (mA) Full scale output voltage (V) Supply Voltage (V) DNL/INL (LSB) Sample rat (MS/s) Power Consumption (mW) Area (mm2) FOM AE
Fig. 11. The measured DNL and INL of the CS-DAC for different supply voltage and different temperature. The input sampling frequency is 40 Hz. The input increases linearly with 1LSB step. The time duration of each input step is about 0.4 s. The value of 1LSB varies from 12 mV to 18 mV in the temperature range. The measurement resolution of DMM was 10 µV.
[5] 2010TNS
[6] 2015TCAS-II
This work
Full-swing (Buffered Voltage) 0.35 µm CMOS current steering + amplifier 10 – – – 0.05 2.5
Full-swing (Unbuffered Voltage) 0.11 µm CMOS current steering + output selector 6 35 5.52 43 1.65 3.2
Full-swing (Buffered Voltage) 0.18 µm CMOS
3.3 0.42/0.42 0.5 0.6
Digital: 1.2 Analogue: 3.3 0.7/0.7 1000 19.1
0.18 4.74e3 –
0.46 7.28e3 1002
current steering + amplifier 6 27.91 4.34 44 0.5 1 1.25 to 1.5 0.05/0.33 20 1.5 @1.35 V supply 0.12 7.11e3 593
The label “–” means parameters not given in the reference. Spectrum test was carried with a input frequency of 35.203 kHz at a 12.5-MS/s update rate, a 1.35-V supply and 25-°C temperature.
the area in [5] can be reduced by approximately half. Even though [5] uses 0.35 µm technology to design a 10-bit DAC, its area is a little larger than our work and quite smaller than that in [6]. So the die area of [5] is the best, while the area efficiency of [6] is the worst. 5. Conclusion Fig. 12. The measured spectrum of the CS-DAC with a 35.203-KHz signal and a 12.5-MS/ s update rate.
This work has presented a technique to improve the output voltage swing of a single-ended CS-DAC under low supply voltage. By using a VCCS, the minimum DAC output voltage can reach approximately zero. Therefore the proposed CS-DAC achieves almost rail-to-rail single-end voltage output by adding a small amount of power and die area. Furthermore, careful matching has been made inside VCCS, as well as between VCCS and DAC. Therefore the minimum output voltage is arithmetically controllable and robust to PVT variations. Simulation and measurement show that the linearity and dynamic performance of our proposed CS-DAC is not limited by the VCCS. The proposed high-swing single-end voltage output CS-DAC is particularly suitable for the applications of low supply voltage, medium speed (up to tens MHz), and relative low power (1–2 mW).
They have a better drive strength but a worse dynamic linearity than the unbuffered CS-DAC. The SNDR of this work is less than that of [6], mainly because the output amplifier introduces more distortion in a wide frequency range. The full-scale output voltage range depends on the voltage margin at VDD and ground side, which directly affects the voltage distortion. With the same supply voltage, the unbuffered scheme in [6] needs less top or ground voltage margin than the buffered ones. Therefore the supply voltage range utilization for output swing of the former is higher. Table 1 reflects the relationship between power and speed. The higher the sampling rate, the more power consumption is required. The CS-DAC in [5] aims at low-power low-speed application, while the one in [6] is for high-speed applications with high power. This work proposes an alternative high-swing solution for medium speed applications with relative low power. To make a fair performance comparison, the FOM can be served as an estimate of overall performance of a design [14]. The FOM of [5] is least, so its overall performance is the worst in the three. The FOM of our work is almost the same as that of [6]. It means the overall performance of our work and [6] are similar. Our work makes reasonable trade-off among speed, power, and area for the applications of low supply voltage and medium speed. As for [6], it aims at high-speed applications; its high-speed merit compensates for its poor area efficiency. The area efficiency of our work is better than [6] because the AE in [6] is larger than that of ours, as seen in Table 1. The reason is that in [6] both PMOS and NMOS current source array are used, resulting in double die area. By using an extra current mirror in the MSB switching,
Acknowledgments This work was supported in part by National key R & D plan (grant number 2016YFC0105002 and 61674162), Shenzhen Key Lab for RF Integrated Circuits, Shenzhen Shared Technology Service Center for Internet of Things, Guangdong government funds (grant numbers 2013S046 and 2015B010104005), Shenzhen government funds (grant numbers JCYJ20160331192843950 and CXZZ20150601160410510), and Shenzhen Peacock Plan. References [1] T.I. Incorporated. Products for digital to analog converter. Available: 〈http://www. ti.com/lsds/ti/data-converters/digital-to-analog-converter-products.page〉, 2016. [2] R. Pierco, G. Torfs, J. Verbrugghe, B. Bakeroot, J. Bauwelinck, A 16 channel high-
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