A high precision low dropout regulator with nested feedback loops

Microelectronics Journal 42 (2011) 966–971

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Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo

A high precision low dropout regulator with nested feedback loops Chua-Chin Wang , Ron-Chi Kuo, Tung-Han Tsai National Sun Yat-Sen University, Department of Electrical Engineering, 70 Lian-Hai Rd., Kaohsiung, Taiwan

a r t i c l e i n f o

a b s t r a c t

Article history: Received 15 July 2010 Received in revised form 16 March 2011 Accepted 21 March 2011 Available online 19 May 2011

A high precision low dropout regulator (LDO) with nested feedback loops is proposed in this paper. By nesting a zero-tracking compensation loop inside of the negative feedback loop comprising an error amplifier, the independence of off-chip capacitor and effective series resistance (ESR) is ensured for different load currents and operating voltages. This circuit is designed and fabricated using a 0:35 mm standard CMOS process. The die area is a 1350 mm  560 mm. The measurement results show that the total error of the output voltage caused by line and load variations is less than 7 3% in low quiescent current (Iddq) or low voltage scenarios. Besides, the smallest dropout of the LDO, 0.11 V, while the output current is 165 mA, the output load is 4:7 mF and 20 in parallel. & 2011 Elsevier Ltd. All rights reserved.

Keywords: Low dropout Low noise High precision LDO

1. Introduction The LDO (low-dropout) regulator is generally utilized to translate a voltage level or provide a stable output voltage, which has been considered as one of the most important components for the power management of wireless applications, e.g., cellular phones, hand-held computers, and particularly implanted wireless biomedical chips [1]. Traditional linear LDO regulators usually consist of a two-stage error amplifier, a power output stage and a negative feedback loop. However, since the stability and accuracy of the regulated output voltage is the most critical factor in many field applications such as biomedical chips, traditional designs suffer from poor efficiency as the difference between the input and output voltages is enlarged [2]. To attain a fast transient response and an accurate output voltage, several prior LDO regulators were proposed, which utilized high gain amplifiers with either a cascade or cascode topology. It results in the stability problem due to the appearance of inherent three poles. Besides, the varying load current also affects the stability [3–5]. Thus, several frequency compensation techniques to ensure the stability of the LDO regulator was proposed to resolve this problem [4–16]. Nevertheless, those compensation techniques usually come with disadvantages. For example, cascode compensation with a dynamic bandwidth boosting was proposed in [10,13], which guaranteed stability over the full range of alternating load current at the expense of high power consumption.

 Corresponding author. Tel.: þ 886 7 5252000x4144; fax: þ 886 7 5254199.

E-mail addresses: [email protected] (C.-C. Wang), [email protected] (R.-C. Kuo), [email protected] (T.-H. Tsai). 0026-2692/$ - see front matter & 2011 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2011.03.014

It is not welcomed in mobile devices, particularly. Besides, the off-chip capacitor and its ESR (equivalent series resistor) are designed to move the zero around to achieve a pole-zero cancelation and keep the phase margin larger than 601 to remain the feedback system stable [18]. However, the off-chip capacitor increases the area of the printed-circuit board (PCB) and the ESR value might drift owing to the variation of the temperature and different materials. Therefore, the off-chip capacitor scheme is not acceptable in many applications demanding high precision. In this work, a new compensation architecture independent of the offchip capacitor and its ESR is presented to enhance the LDO regulator’s performance regarding the transient response and the noise rejection. Besides, a bandgap reference integrated with an error amplifier in a feedback loop is proposed to achieve the high precision of LDO.

2. LDO circuit design Fig. 1 shows the block diagram of the proposed LDO, which is composed of a reference voltage bandgap, an error amplifier, a source follower, a power MOS (MP), a voltage divider composed of R1 and R2, a variable resistance Rc. 2.1. Bandgap reference To generate a stable voltage against process and temperature variations, a bandgap reference circuit is adopted [3]. To enhance the capability against the supply voltage variation and the noise coupling from the substrate, a feedback loop with an error amplifier (EAB) is used as shown in Fig. 2. Assuming the gain of

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VIN 3.45 V ~ 5 V

Reference Voltage Bandgap ( 1.2 V )

EA OUT

Acts as a resistor Rc MA Cc

EAF

MP Source Follower

VOUT 3.3 V

1 F

R2

Mc

Quiescent current = VREF / R1

C1 VFB R1

Fig. 1. Architecture of the proposed low noise low dropout regulator.

VIN

VIN 3.45 V ~ 5 V

M12 M11

M13 VB4

M14

M9

M8

M10 MP

M6

M5

EAOUT

M7 VREF

R1

R2

Source Follower

R4

Fig. 3. The schematic of source follower.

I3 M3

EAB

M4 Vy

Vx

M1 I1

M2

VB3

VB4

R3

I2 Q1

VDD

Q2

VP

Q3

VN

VB3

VB2 EAOUT Fig. 2. The schematic of bandgap reference.

VB2 the EAB is very large, Vx and Vy are approximately equal, where Vy and Vx are the voltages at the inverting and noninverting input terminals of EAB, respectively. In Fig. 2, transistors M1 and M2 are both operating in saturation region. Taking channel-length modulation into consideration, the drain currents of M1 and M2, I1 and I2, can be written as I1 ¼

b1

I2 ¼

b2

2

2

2

ðVGS1 VTH1 Þ ð1 þ lVDS1 Þ

ð1Þ

ðVGS2 VTH2 Þ2 ð1 þ lVDS2 Þ

ð2Þ

where VGS1 and VGS2 are the gate to source voltage of M1 and M2, respectively, VTH1 and VTH2 are the threshold voltage of M1 and M2, respectively, l is the channel-length modulation coefficient,

VB1 VB1

Fig. 4. Error amplifier (EAF).

VDS1 and VDS2 are the drain to source voltage of M1 and M2, respectively, b1 and b2 represent the device parameters of M1 and M2, respectively. Given that I1 ¼ I2, VGS1 ¼ VGS2 , VDS1 ¼ VDS2 , we attain the following equation: VGS1 þVBE1 ¼ VGS2 þI1  R3 þVBE2

ð3Þ

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Then, the sensitivity of I3 versus temperature can be derived as

Eq. (3) can be rewritten as I2 ¼

VBE1 VBE2 þVGS1 VGS2 VBE1 VBE2 ¼ ¼ I3 R3 R3

ð4Þ

Since VBE ¼ VT  lnðIc=IsÞ, and the size of Q2 and Q3 are both the n times of that of Q1, I3 can be expressed as I3 ¼

VT  lnðnÞ R3

ð5Þ

@I3 K lnðnÞ ¼  @T q R3

ð6Þ

Since Is ¼ cT 4 þ m expðEq=KTÞ, where c and m are constants, the sensitivity of VBE versus temperature can be derived as follows: @VBE VBE ð4þ mÞVT Eq=q ¼ 1:5 ðmV=KÞ ¼ T @T

ð7Þ

where T¼300 K, VBE ¼ 0.75 V, in Eq. (7). In Fig. 2, VREF ¼ I3  R4þVBE3. Hence, the sensitivity of VREF versus temperature can be derived as Series Pass Element

@VREF R4 K VBE ð4 þ mÞVT Eq=q ¼  lnðnÞ þ @T R3 T T

S

G

Cgd

Vgsgp

Vgs

Rds

ð8Þ

Thus, the sensitivity of VREF can be eliminated by adjusting the value of R4 to generate a stable reference voltage.

D

2.2. Source follower Zo

As shown in Fig. 3, source follower is used to drive the large capacitive load and the small resistive load. The EAOUT is fed into the source follower to drive MP in the saturation region, where VB4 is a bias voltage connected to EAF, as shown in Fig. 4.

gp R2 RESR ga

Vin Rpar

Cpar

R1 Vref

Vo

Cb Co

Fig. 5. The small signal equivalent model of LDO.

Iout

2.3. Error amplifier Speed and gain always determine the performance of the LDO, and the speed of the LDO are mainly determined by the error amplifier, i.e., EAF, in Fig. 1. In order to reduce the the noise from VIN, EAF is implemented with a folded cascode structure, as

Fig. 6. Bandgap reference simulations given different process corners.

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Power Supply

Digital Oscilloscope Function Generator Current/ Meter VOUT LDO VIN Fig. 7. VREF is stable given different VIN from 3 to 5 V.

1350 µm VOUT

VOUT resister

VREF

GND (core) GND (core)

BandGap

Fig. 9. Measurement environment for the proposed LDO.

560 µm

PWM (W/L = 80,000/0.35 um)

GND

VIN VREF Fig. 8. Die photo of the proposed LDO.

shown in Fig. 4, where VB4 is a voltage bias coupled to the following source follower. Moreover, the cascode structure can enlarge the gain to provide a precise output voltage of LDO. 2.4. Frequency compensation In a negative feedback system, the stability is always a critical issue. To ensure the stability of the system, the phase margin of the open loop gain should be carefully designed. Traditionally, the small signal equivalent model of LDO is shown in Fig. 5 [17], where ga is the transconductance of error amplifier, Cpar and Rpar are the parasitic capacitor and resistor of error amplifier, respectively, gp is the transconductance of power MOS, Co is the load capacitor, RESR is the load effective series resistance, Cb is the bypass capacitor, and Iout is the load current. In most cases, Co is much larger than Cb , the output impedance, Z0 , can be simplified as Z0 

Rds ð1 þSRESR Co Þ ½1 þ SðRds þRESR ÞCo   ½1 þ SðRds JRESR ÞCb 

ð9Þ

By Eq. (9), three poles and one zero could be attained. However, the phase margin is not high enough for a LDO and the output voltage may be easily oscillated. In other words, the phase margin of the traditional LDO is dominated by the load. Therefore, two frequency compensation methods are adopted to keep our LDO apart from load capacitor and its ESR, which are given in detail with following two sections. 2.4.1. Zero-tracking compensation The main pole frequency of the LDO will varied with its load. When the load current decreases and the equivalent output resistance increases, the frequency of main pole determined by the output capacitor and resistor will move forward left to reduce the LDO’s bandwidth. The circuit may then become unstable

when the bandwidth is reduced. Therefore, a mobile zero varying with load current is needed for LDO [12]. As shown in Fig. 1, the PMOS, MA , is biased in the triode region to act as a variable resistance. Its resistance is varied with the voltage at VOUT, which is the load voltage. Therefore, the zero is varied with the dominant pole to avoid the bandwidth reduction of the LDO. Meanwhile, the phase margin is also compensated. 2.4.2. Nested Miller compensation A small Miller capacitor, Mc, is coupled to the gate of MA on the feedback path, as shown in Fig. 1. Besides, the feedback voltage divider composed of R1 nd R2 is connected with C1 in parallel to generate a extra zero and pole. When the pole’s frequency equals (1þR2/R1)  k times of the zero’s frequency, the noise of the system can be eliminated, where k is an experimental constant. According to our measurement in Section 3, the frequency of the pole is about 2.75 times of the zero’s frequency.

3. Simulation and measurement 3.1. Simulation of the bandgap reference The low noise LDO is designed and fabricated using a 0:35 mm standard CMOS process. The bandgap reference with a compensated error amplifier has been simulated given the temperature from  40 to 120 1C. As shown in Fig. 6, VREF has a variation of 71 mV from the mean value 1.204 V given different process corners. A stable VREF is obtained given different VIN from 3 to 5 V, as shown in Fig. 7. 3.2. Measurement results for the proposed LDO Fig. 8 shows the die photo of the proposed circuit. The measured environment is set up as Fig. 9, which is composed of an infinium Oscilloscope, a function generator, and a power supply. The input port of the proposed LDO, VIN, is connected to the power supply. Fig. 10 presents the smallest dropout of the LDO, 0.018 V, while the output current is 165 mA, the output load is 4:7 mF and 20 O in parallel. Figs. 11 and 12 show the transient response of LDO in the line regulation measurement. Fig. 12 is the detailed illustration of Fig. 11 with VIN switching from 3.45 to 5 V. It can be observed that VOUT is stable with a settling time

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Power supply

VIN

LDO

VOUT M0 R5

Function gererator

R6

CLK R5 = 1K Ohm R6 = 14 Ohm

Fig. 13. Measurement configuration for LDO load regulation.

Fig. 10. The smallest dropout with output current ¼ 165 mA.

Fig. 14. Measured load regulation of proposed LDO.

Fig. 11. Measured line regulation of proposed LDO.

Fig. 15. Measured settling time of LDO load regulation.

Fig. 12. Measured settling time of LDO line regulation.

less than 36:55 ms and a line regulation of 0.012%. When load regulation is measured, the test configuration with R5 ¼ 1 KO and R6 ¼ 14 O in Fig. 13 is used, where R5 and R6 are load resistances. Fig. 14 shows the measured transient response of LDO at

VIN¼3.3 V with the output current switching from 120 to 0 mA. Fig. 15 is the detailed illustration of Fig. 14, where CLK represents the transient when M0 is turned off. VOUT is stabilized with a settling time less than 42:54 ms and a load regulation of 0.005%. Figs. 16 and 17 shows the measured PSRR when VIN is at 30.08 and 3.08 kHz, respectively. The quiescent current, Iddq, is 50 mA with a load current ¼ 134.35 mA. The performance comparison of LDOs is shown in Table 1. Our design has the edge of minimal line regulation, load regulation and dropout voltage. 4. Conclusion In this paper, a bandgap reference with a compensated error amplifier for high precision LDO is disclosed. This design

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PSRR stays over 50 dB even if the operating frequency is up to 3.08 kHz.

Acknowledgments This investigation is partially supported by Ministry of Economic Affairs, Taiwan, under Grant 99-EC-17-A-01-S1-104 and under Grant 99-EC-17-A-19-S1-133. It is also partially supported by National Science Council, Taiwan, under Grant NSC99-2221E-110-082-MY3, NSC99-2923-E-110-002-MY2, NSC-99-2221E-110-081-MY3, NSC-99-2220-E-110-001, and EZ-10-09-44-98. The authors would like to express their deepest gratefulness to CIC (Chip Implementation Center) of NARL (National Applied Research Laboratories), Taiwan, for their thoughtful chip fabrication service.

References Fig. 16. Measured PSRR at VIN ¼ 30.08 kHz.

Fig. 17. Measured PSRR at VIN ¼ 3.08 kHz.

Table 1 Performance comparison of LDO.

Process (mm) Year Line regulation (%) Load regulation (%) Dropout (V) ESR zero required Iddq (mA) ILmax (mA)

[10]

[4]

[5]

[8]

Ours

0.18 2009 0.024 0.7 0.3 Yes 0.028 N/A

0.18 2008 N/A N/A N/A No 0.027 150

0.35 2007 N/A N/A 0.2 No 0.02 200

0.18 2009 0.231 0.101 0.541 Yes 0.035 150

0.35 2010 0.012 0.005 0.11 No 0.05 240

is independent of the off-chip capacitor and its ESR. The measurement results justify its high precision with line regulation¼ 0.012% and load regulation¼0.005%. Moreover, the

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