A high precision SOI MEMS–CMOS ±4g piezoresistive accelerometer

Sensors and Actuators A 210 (2014) 77–85

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Sensors and Actuators A: Physical journal homepage: www.elsevier.com/locate/sna

A high precision SOI MEMS–CMOS ±4g piezoresistive accelerometer Anindya Lal Roy a,∗ , Hrishikesh Sarkar a , Anupam Dutta b , Tarun Kanti Bhattacharyya c a

Advanced Technology Development Centre Indian Institute of Technology, Kharagpur, West Bengal, India Semiconductor Research and Development Centre IBM Corporation, Bangalore, Karnataka, India c Department of Electronics and Electrical Communication Engineering Indian Institute of Technology, Kharagpur, West Bengal, India b

a r t i c l e

i n f o

Article history: Received 31 May 2013 Received in revised form 24 January 2014 Accepted 24 January 2014 Available online 5 February 2014 Keywords: MEMS Piezoresistive accelerometer CMOS front-end ASIC Variable-gain Temperature compensation SOI

a b s t r a c t System development and characterization of a low noise low offset SOI MEMS–CMOS PCB-integrated multi-chip ±4g piezoresistive accelerometer sensor comprising a coupled multi-bandwidth variable-gain amplifier block and a thermal sensitivity and offset compensation block is presented in this work. Custom design and fabrication has been carried out for both the SOI MEMS sensor and the analog front-end for high precision and operational reliability. The system is shown to have a scale factor of ∼4 mV/g and an output nonlinearity <1% of full-scale output with a cross-axis sensitivity <1%. Cyclic loading experiments exhibit distortionless operation over ∼1000,000 cycles without failure indicative of an extremely robust system. © 2014 Elsevier B.V. All rights reserved.

1. Introduction Low frequency inertial measurements form the basis of an exhaustive range of applications such as motion guidance and navigation [1,2], flow and orientation sensing [3,4], geophysical and industrial structural health monitoring [5], biomedical vibration sensing and nanoscale detection systems [6,7]. Rapidly evolving microelectronic fabrication techniques and micromachining processes have led to the development of microelectromechanical systems (MEMS) sensors principled upon inertial measurements carried out through electromechanical signal transduction of various kinds and conditioning the raw sensor output using front-end CMOS interfacing technology. Among the plethora of such combined implementations, the MEMS accelerometer has been one of the most extensively researched sensors apart from devices such as pressure sensors [8] and gyroscopes [9] and has been commercialized in recent years, finding usage in a range of applications from smart phones to automobiles. Current state-of-the-art in MEMS accelerometer technology employed commercially exploits compliant mechanisms of surface and bulk micromachined MEMS microstructures for capacitive [10], piezoelectric [11], piezoresistive [12,13], optical [14], quantum tunneling [15] and other transduction mechanisms [16] in response to

∗ Corresponding author. Tel.: +91 3222281720. E-mail address: [email protected] (A.L. Roy). 0924-4247/$ – see front matter © 2014 Elsevier B.V. All rights reserved. http://dx.doi.org/10.1016/j.sna.2014.01.036

externally applied inertial forces. Exhaustive research has been conducted on the analysis [17–19] and process development of piezoresistive accelerometer devices [20–22], architecture and implementation of their respective front-end circuits [23,24] and testing methodologies [25]. However, to the best of our knowledge, not a lot of complete literature is available on the development and interfacing issues in piezoresistive MEMS–CMOS accelerometer applications and its impact on the system under test. Interfacing low frequency piezoresistive MEMS accelerometers involves the design of a readout circuit which drives the sensor electronics as per the operating condition requirements. In this work, we concurrently develop our sensor and circuit blocks, adding the flexibility of multi-bandwidth variable-gain operation to a novel temperature compensation scheme which eliminates the need for on-board temperature sensing elements while being compatible with progressively shrinking CMOS processes in terms of sensitivity. We investigate the functioning of the integrated system shown in Fig. 1 (green sensor block and red circuit block) on a printed circuit board (PCB) which is subjected to extensive system-level dynamic excitation tests after the individual chips are thoroughly characterized for interfacing. Detailed development of the MEMS–CMOS accelerometer system is elaborated on in the subsequent sections which are organized as follows: Section 2 develops the background of the MEMS–CMOS system presented here. Section 3 covers the implementation of the SOI MEMS accelerometer sensor and the CMOS front-end as well as their interfacing while the test results of the

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Fig. 1. (top left) Complete SOI MEMS–CMOS accelerometer system schematic (green section: MEMS piezoresistive accelerometer; red sections: ASIC blocks) (top right) MEMS out-of-plane accelerometer schematic illustrating system suspension elements (beams), inertial element (seismic mass) and sensing elements (resistors) where the sensing direction is normal to the plane of the diagram (bottom) Current biased Wheatstone bridge schematic showing resistance response during sensor operation due to applied stresses along the relevant axes. (For interpretation of the references to color in this figure legend, the reader is referred to the web version of this article.)

individual blocks and PCB-interfaced system are elaborated upon in Section 4. Concluding observations regarding performance and reliability issues are summarized in Section 5 along with suggestions for future design and fabrication improvements. 2. MEMS–CMOS piezoresistive accelerometer: System development 2.1. MEMS piezoresistive acceleration sensor An inverse nonlinear dependence of output sensitivity on temperature affects the deployment of piezoresistive sensors despite appreciable sensitivity and efficient noise performance (conductance fluctuation induced 1/f noise is the primary source of low frequency distortion [26]) with electrostatic and piezoelectric mechanisms being preferred and alternative variants (optical, thermal, SAW) being researched intensively. Besides temperature sensitivity, uniaxial bulk micromachined sensors are highly susceptible to temperature offsets as well as electromechanical crosstalk between the primary out-of-plane sensing axis and the inplane perturbations due to foundry mismatch and schematic layout issues resulting in loss of precision. To nullify the device and system-scale disadvantages of piezoresistive accelerometers, the authors propose a current-biased accelerometer system implemented by the schematic illustrated in Fig. 1 which employs a Wheatstone-bridge type piezoresistive outof-plane acceleration sensor interfaced with a low-noise variable gain amplifier block and a thermal sensitivity and offset estimation and compensation block for MEMS output conditioning and bridge bias generation over user-defined bandwidths. A quad-beam mechanical structure (Fig. 2) was implemented for our MEMS sensor with an adaptively-biased piezoresistive Wheatstone-bridge for signal transduction. Current bias (Ibias ) is preferred due to reliability in varied ambient conditions and its insensitivity to the downscaling of CMOS technology which results in sensitivity

retention. The Wheatstone bridge is configured such that perturbations along the out-of-plane axis are registered as bridge terminal voltages while those along the in-plane lateral axes are nullified as depicted in Fig. 1.The MEMS accelerometer sensor can be modeled as a distributed mass-spring-damper (MSD) system [27]. Dynamics of driven quad-beam single degree-of-freedom (SDOF) MSD systems realized using bulk micromachining fabrication techniques can be expressed as ˙ = FM (t) : ∀t ∈ R⊕ MMSD u¨ +  (u, u)

(1-a)

Ki ui +

(1-b)

˙ =  (u, u)

 i∈Z⊕



Ci u˙ i ≈ KMSD u + CMSD u˙

i∈Z⊕

where MMSD (=LBH) is the equivalent distributed mass of the MSD system,  is a function denoting the inertial forces acting on the system and is a function of transducer displacement (u) ˙ while FM is the applied mechanical excitation and velocity (u) expressed as a function of time t.  can be decomposed into a sum of polynomials whose coefficients represent the respective stiffness and damping constants. Ignoring the nonlinear terms, the system reduces to a linear MSD model with a distributed spring constant KMSD (=4Ebh3 /l3 ) and damping constant CMSD (=ˇB3 L/d3 ) where l, b, h are the length, breath and thickness of the flexures; L, B, H are the length, breadth and thickness of the seismic mass,  is the density of the device material, d is the gap between sensor and wafer-scale glass cap for damping and over-range protection, assuming symmetry in mass displacement during device operation,  is the viscosity of the air ambient within the glass encapsulation while E is the Young’s modulus of the compliant sensor material and ˇ is a damping factor dependent on the ratio B/L of the damped mechanical structure. Sensor design is primarily guided by the attempt to maximize out-of-plane sensitivity while completely rejecting lateral signals with the Wheatstone bridge configuration explained earlier. The seismic mass and the beams are of dimensions 2200 ␮m × 2200 ␮m × 675 ␮m and

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variations resulting in tolerances in resistor values and consequently, bridge output voltages. 2.2. CMOS front-end ASIC

Fig. 2. Metal packaged and wire bonded SOI MEMS piezoresistive quad-beam accelerometer with labeled pins [GND: ground, Is: current bias, Vp and Vn: differential output] (above); wafer-level glass-encapsulated device (below) and scanning electron micrograph of a section of the device (inset).

1100 ␮m × 200 ␮m × 20 ␮m, respectively. The natural frequency of vibration of the quad-beam structure is estimated using Rayleigh–Ritz methods (f1st mode ∼ 1.54 kHz) and is chosen according to the requirement of being far away from the device operating frequency to prevent resonant operation and at the same time, not too high so as to increase the effective stiffness, thereby decreasing the mechanical sensitivity of the structure. The effective constants of the MSD model are determined by the laws of beam dynamics and squeezed-film fluid damping and are dependent on the structural dimensions and the properties of the operating ambient as seen from the design equations. Mechanical simulations of this device were carried out using CoventorWareTM and the results obtained were in close correspondence to our analytical estimates with appreciable stress sensitivity which is the primary figure of merit in sensor design. The sensing piezoresistive elements are so aligned as to sense only the longitudinal strain that is exerted along their length direction (Fig. 1) and the primary sensing direction is out-of-plane with the Wheatstone compensating bridge being configured such that all other perturbations are rejected. The current biased sensing bridge was designed in accordance with the sensitivity requirements, keeping in mind the input common mode range (ICMR) of the interfacing ASIC which is kept quite wide as illustrated later in order to accommodate the MEMS process

The readout circuit has been developed to be a flexible interface to the MEMS sensor, providing for multi-bandwidth operation at adaptive voltage gains for appropriate bridge signal strengths. Multi-bandwidth variable-gain amplifiers effectively improve the overall signal-to-noise ratio (SNR) by switching to higher gain bands, sacrificing the bandwidth to minimize the introduction of noise from weaker signals and vice versa. In addition, the problem of temperature dependence of sensitivity and offset and their compensation: an issue inherent to every piezoresistive sensor, has been addressed through the use of a novel adaptive bridge biasing scheme to be detailed later on. The CMOS front-end can be classified as two fundamental signal conditioning blocks: the main amplifier (MA) block and the thermal sensitivity and offset compensation (OSC) block controlled by supporting clock and bias generation blocks. The MA block provides variable system gain at adjustable system bandwidths depending on the MEMS sensor output levels along with aiding in dynamic offset and low frequency noise cancellation while the OSC block modulates the Wheatstone-bridge bias voltage based on the sensor output feedback to generate a thermally compensated adaptive biasing scheme for sensitivity and offset compensation. The MA block comprises a pair of auto-zeroed (AZ) amplifiers operating in ping-pong mode (at fAZ = 12.5 kHz) within a couple of chopper (CH) modulation-demodulation sections [28–30]. Most low frequency (LF) CMOS operation exhibits increased input referred offset levels (treated as very low frequency noise) and flicker noise (1/f dependence) which dominates the thermal noise components and the nested architecture segregates the signal from the LF noise, enabling continuous-time signal processing along with the elimination of noise-folding observed in AZ amplifiers [31] and alleviating charge leakage from the offset storage capacitors and charge injection in the sampling switches to a high degree. Translation of the LF noise (offset and 1/f) around the chopper frequency (fCH = 100 kHz) after demodulation requires low-pass filtering (LPF) for the removal of modulated noise components which can be achieved by cascading a continuous-time LPF (CTLPF) and a switched-capacitor LPF (SCLPF) with the nested AZ–CH scheme for eliminating high frequency offsets and enabling scalable system bandwidth. The filter cutoff (fcutoff ) is so chosen as to provide a high attenuation at fCH for comprehensive noisecancellation along with the ability to accommodate a user-defined variable system bandwidth based on the applied range of excitation frequency. These LPFs are designed so as to accommodate user-defined, scalable system bandwidth depending on the frequency regime of the MEMS sensor output signal. A peak detector (PD) section, employing amplitude demodulation based on MEMS sensor output levels, ensures amplifier linearity by monitoring the output levels of the cascaded LPF block using signal envelope detection and comparators to generate a 2-bit state output. A stable output swing is maintained by feeding the PD output to a digital finite state machine (FSM) block which performs gain controlling functions to realize a high-precision variable gain amplifier. FSM implementation is done using a D-flip flop Johnson (switch-tail ring) counter which classifies its range of inputs into three gain bands and performs signal routing operations through appropriate bands for proper gain levels at various signal bandwidths. The OSC block compensates for the nonlinear dependence of the MEMS bridge sensitivity on ambient thermal conditions by adopting a temperature-dependent adaptive bridge bias voltage generated by routing Ibias through an external resistor Rext shown in Fig. 3b and c. For a reference temperature of T0 (=300 K) and measurement temperature T, the bridge bias (Vbias ), sensitivity of the accelerometer

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Fig. 3. (a) Main amplifier (MA) block interfaced with MEMS sensor output; (b) sensitivity compensation block; (c) Offset compensation block.

(S) and the adaptive bias reference (V bias ) with current bias Ibias and negative temperature coefficient of sensitivity (˛S k ) can be written as Vbias ( ) = Ibias R0 (1 +



˛kR  k ) : ∀ = (T − T0 )

(2)

k∈N⊕

S( ) = Vbias S0 (1 +



˛kS  k ) : ∀ = (T − T0 )

(3)

k∈N⊕

  Vbias

=

(1 +



−1 ˛kS  k )

3. Sensitivity calibration (1) Determine the MEMS sensor bridge sensitivity (S) over the investigated temperature range. (2) Determine the bias current extrema Ibias MAX and Ibias MIN required to keep the value of S constant at Tref . (3) Estimate the VBias characteristics for the current extrema over the investigated temperature range. (4) Value of VBias (maximum temperature) for Ibias MAX is the upper limit of the bias voltage denoted by VBias MAX and the value of Vbias (minimum temperature) for Ibias MIN is the lower limit of the bias voltage denoted by Vbias MIN .

(4)

k∈N⊕

where  denotes the temperature step with respect to reference temperature (T0 ), R0 represents the resistance at the reference temperature and S0 is the sensitivity at the same. The sensitivity compensation scheme adapts the generated bias voltage (Vbias ) according to V bias (=Vref ) which is a piecewise-linear approximation of the compensated bias formulated in (4). A negative feedback loop varies Ibias to keep Vbias equal to Vref with the sensitivity compensation schematic of the OSC block shown in Fig. 3b. Vbias is amplified by the variable-gain amplifier (shown in the block) through off-chip feedback resistors. Outlined below is the calibration scheme for the thermal sensitivity compensation circuit which estimates the circuit parameters (feedback resistor values and range of bias voltages).

The voltage range of Vbias MAX to Vbias MIN is divided into 10 equal segments by the resistive ladder, thereby creating unequally spaced (nonlinear) temperature divisions. These intermediate voltages are compared to Vbias through a comparator chain whose output controls the feedback resistor gain for adaptive bias generation. Mismatch of MEMS bridge resistances and their respective temperature coefficients generate temperature dependent offsets Voffset MEMS which are also compensated by the OSC block. Subblock no. 1 determines Ibias using Vbias and VRext to generate a signal (proportional to Ibias ) X while sub-block no. 2 comprising unity-gain subtractors calculate the voltages across the bridge arm resistors which is then processed by sub-block no. 3 to generate signal P. Multiplier–multiplexer (M&M) sections comprising variable-gain inverting amplifiers and selectable phase inverters with off-chip gain control resistors produce weighted versions of Ibias denoted

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Fig. 4. Schematic of the clock generation scheme showing all the ASIC clocks generated from the external 200 kHz clock frequency.

Table 1 ASIC clock specifications. Clock type

Number of clocks

Frequency (kHz)

Chopper MA Auto-zero Chopper OSC FSM clock Filter clock

6 8 6 1 4

100 12.5 2.5 1 200, 25, 12.5 and 0.780

by Y and Z while another M&M section amplifies P to Q and on comparative analysis among Q, Y and Z, produces the predicted offset voltage Voffset OSC . The expressions for M&M block gains are tabulated in Table 1. The components of the MA and OSC blocks are driven at different clock frequencies and bias currents/voltages which are generated by supporting schemes described below. A primary 0–1.8 V, 200 kHz external clock signal is fed through a counter and various non-overlapping and complementary clock generation sub-blocks to produce all CH, AZ, SCLPF and FSM clock signals. Various clock frequencies used and the basic clock generation schematic is illustrated in Fig. 4 and Table 2 which shows the 25 clock signals used to drive the ASIC. 4. System implementation and interfacing Sensor fabrication was carried out using a custom bulk micromachining process on optically flat 150 mm SOI wafers (650 /) to minimize any parasitic substrate effects and losses whatsoever. Table 2 System specifications. Parameter

Specification

Full-scale output (FSO) range Nonlinearity Cross-axis sensitivity Bandwidth

0 to ±4g <1% FSO <1% 50 Hz, 800 Hz, 2 kHz and 8.5 kHz (at ±3 dB level, user-defined) 37 dB, 52 dB and 62 dB (variable-gain) ∼2.9 ␮V √ ∼45 nV/ Hz 20 ◦ C to 140 ◦ C

Gain bands Offset Noise Temperature range

Usage of SOI wafers also reduced on-wafer variations [32] in etched beam thicknesses resulting in extremely low tolerances with respect to spring constants and by extension, device sensitivity. Piezoresistors (PZR) (p-type, boron-doped, ∼300 /) were ion implanted for precise resistor profile definition of 120 ␮m × 20 ␮m × 1 ␮m and minimization of thermal spread of dopant. The heavily doped piezoresistors with optimal Al/p-Si contact areas for reduced 1/f noise signatures were limited to the surface ∼1 ␮m for maximizing the stress sensitivity of the aluminum (Al) lift-off metalized Wheatstone-bridge. Individual resistor values were measured to be ∼1.5 k with a 5.3% variation in on-chip resistance over the wafer. The layout of the metal track, ∼20 ␮m in width, was designed over the beams and the device frame so as to avoid mobile beam-mass junctions which are susceptible to high-cycle fatigue and creep thereby lowering the operational reliability of thin film interconnects. The mechanical structure is designed as a coplanar quad-beam/seismic mass system supported on a rigid frame using deep reactive-ion etching (DRIE) techniques. Four bond pads (Al) on the frame serve as input/output (grounding, bias current and differential bridge output). Avoidance of beam-mass junctions leading to crossover of interconnects is nullified by passivation bridging using vias through silicon nitride for proper routing. Very high aspect-ratio (AR) plasma (dry) etch methods prove to be advantageous in that traditional anisotropic bulk micromachining of 1 0 0 SOI wafers result in trapezoidal cross-sections of the sensing mass and hence, lower inertia sensitivity compared to the DRIE fabricated rectangular cross-sections. Post-release wafer-scale glass encapsulation of the device was carried out for critical damping using a 14 ␮m air gap using an SU-8 adhesive bonding technique comprising DRIEprocessed glass wafers bonded to UV-irradiated SU-8 photoresist polymer (N2 ambient, atmospheric pressure) which is then hard baked (∼90 ◦ C) to ensure good hermeticity and very low residual stresses (due to temperature-assisted slow solidification of the viscous polymer–wafer interface) on the trilayer (glass–SOI–glass) microfabricated system. Packaging is done after laser dicing using a 5-pin metal can package with gold (Au) wire bonding. Both waferlevel encapsulated as well as the metal-can packaged devices are shown in Fig. 2. The sensitivity/offset-compensated low-noise variable-gain amplifier ASIC was fabricated using the 180 ␮m (UMC) CMOS process technology with 120-pin quad-flat packaging

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Fig. 5. (a) Gain spectrum of the primary gain band (GB0) showing the response at all four bandwidths (50 Hz, 800 Hz, 2 kHz and 8.5 kHz); (b) total harmonic distortion (THD) characteristics over a range of different frequencies; (c) total harmonic distortion (THD) characteristics at different signal amplitudes; (d) variation of gain as a function of input common mode voltage from which the input common mode range (ICMR) can be determined (range within the dotted lines).

(QFP) for interfacing with the MEMS sensor. High pin-count of the ASIC is merely a manifestation of all the individual blocks’ internal probing and testing circuits. These packaged devices were then mounted and interfaced on a custom 2-layer PCB for tests. Separate voltage regulators (LP5900) [33] were used to generate three supply voltages for the ASIC and AD586 [34] was used to provide ±5 V supply to the interfacing amplifiers while Agilent 6629A [35] supplies +5 V DC to operate the regulators. Shielded signal lines were used as input and output lines and a thick metal line was used to separate the power supply form the core ASIC. The entire second PCB layer is used as the ground plane. The following section deals with individual wafer and integrated PCB tests carried out for characterizing the system and individual system component (MEMS + ASIC) properties over a broad range of operating conditions.

calculated from the sensitivity calibration model, is divided into 10 equal sections using the resistive ladder in Fig. 3b and the intermediate voltages generated are compared with the adaptive VBias (at t = ti ) using the comparator chain while its outputs control the gain and hence, the adaptive VBias is generated (at the instant t = ti+1 ) based on the piecewise-linear interpolation of the function given by (4). Sensor interfacing involves circuit parameter definition over the desired operating range as well as identifying weaknesses in circuit design and foundry tolerances. Primary factors affecting total MEMS–CMOS system output comprise ASIC parameters such as overall system gain, output linearity, ICMR and noise and waveform distortion. Fig. 5a clearly illustrates the stability of the ASIC amplifier primary gain band (GB0) over user-defined bandwidths. Total harmonic distortion (THD) is a measure of nonlinearity of output waveforms and can be estimated from the corresponding frequency spectra amplitudes Ai using



5. Performance evaluation MEMS sensor bridge resistance measurements were carried out at 20 ◦ C and a tolerance of ±10% over an average value of ∼3 k was obtained. This tolerance factor can be accounted for by a 5% on-wafer variation of resistivity coupled with the tolerance factor of the ion implantation process. Thermal measurements to obtain the MEMS Wheatstone-bridge bias parameters for calibration of the front-end OSC block were done on a wafer probe station (Thermal stage PM5/Agilent B1500 Device Analyzer [36]). Thermal dependence of Wheatstone-bridge sensitivity and offset was measured over a range of 20 ◦ C to 140 ◦ C and from the characteris  tics; the highly nonlinear negative temperature coefficients ˛iS of equivalent MEMS bridge resistance in the sensitivity expression (3) can be extracted. The range VBias MAX and VBias MIN , as

THD(%) =

A2i

i∈N⊕

A1

× 100 : ∀Ai = ith harmonic

(5)

The variation of THD with input signal frequency, input voltage amplitudes and system bandwidth is shown Fig. 5b and c. For 8.5 kHz bandwidth, inter-modulation products between the input frequency and the AZ frequency increases the THD and this effect increases with increasing input frequency. Similar observations are made for increasing signal voltages although higher signal frequency has a more pronounced effect on THD degradation than higher voltage amplitudes as is seen in Fig. 5c for input frequencies 500 Hz and 5 kHz. Low noise interfacing of differential output sensors with CMOS front-ends requires stable amplifier

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Fig. 7. (a) Test PCB setup with MEMS (red) and ASIC (blue); (b) output characteristics (voltage–acceleration) of the SOI MEMS–CMOS referenced with ADXL78 (upper inset) and AIS326DQ (lower inset) at 100 Hz loading from ±1g to ±4g showing high linearity (blue bubbles) for mounting the MEMS either way out-of-plane and extremely low cross-axis sensitivity (red bubbles). (For interpretation of the references to color in this figure legend, the reader is referred to the web version of this article.)

Fig. 6. (a) Input referred offset (IRO) variation with MEMS bridge resistance; (b) input referred noise (IRN) spectrum with various configurations of CH and AZ; (c) percentage relative offset (PRO) and sensitivity (PRS) variation with temperature.

common-mode properties: a wide ICMR with high common-mode signal attenuation. From the gain characteristics at various input common-mode voltages in Fig. 5d, we determine the lower and upper common-mode limits (∼510 mV and ∼1680 mV, respectively) of the ICMR. Amplification issues aside, input referred offset and noise compensation are two key aspects of the MA block. Its variation with MEMS sensor resistance (Fig. 6a) yields an input referred offset (IRO) value (at zero resistance) of ∼2.9 ␮V while exhibiting incremental behavior with increasing sensor resistance.

Fig. 6b demonstrates the dependence of the input referred noise spectrum on the MA core sub-blocks where the AZ + CH assisted √ noise cancellation gives a very low noise floor of ∼45 nV/ Hz (at 10 Hz) [37]. The trends seen in percentage relative offset (PRO) and sensitivity (PRS) error over the operating range of temperatures (Fig. 6c) indicate a <1% error in the MEMS sensor output compensation failure by the front-end with the overall amplifier and temperature compensation schemes consuming ∼4 mW in operation. Dynamic acceleration testing of the integrated SOI MEMS–CMOS accelerometer was carried out on electrodynamic vibration test platforms (Bruel and Kjaer LDS V555 low-force shaker [38] with STMicroelectronics AIS326DQ 2g/6g accelerometer [39] as the reference device and Spectral Dynamics SD-8360-13/DA-40 medium-to-high force shaker [40] with Analog Devices ADXL78 [41] accelerometer as the reference device). Two sets of measurements were done to estimate output match. The PCB was screw-mounted on a 10 mm-thick rigid Al plate which was bolted to the shaker stage for excitation tests. The system was subjected to a 20–100 Hz sinusoidal excitation (over ∼1000,000 cycles without failure) with a 300 ␮A sensor current bias and referenced with the ADXL78 and the AIS326DQ capacitive accelerometers. The complete test board is depicted in Fig. 7a while Fig. 7b shows the complete range of voltage–acceleration (V–g) characteristics (with

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Table 3 Gain coefficients.

Systems (NPMASS), Govt. of India for funding this work and their laboratory colleagues for their technical support.

Gain coefficient

Sign

GM&M#1

Positive

GM&M#2

Negative

Expression

 R2 +R3 −R1 −R4  A0 × R4 +R2 −R1 −R3  R2 +R23 −R1 −R4  (R2 R4 −R3 R1 ) × R +R −R −R 4 4 2 1 3  Rn

GM&M#3

Positive

n=1 (R3 R2 −R1 R4 ) 4 

Rn n=1

the reference outputs shown in the insets). It is observed from the V–g characteristics that the MEMS–CMOS system exhibits a high degree of linearity along with very low noise outputs as was targeted. The output waveforms captured on a LeCroy WaveSurfer 42Xs digital storage oscilloscope can be seen in the inset of Fig. 7b where the contrast between the SOI MEMS system and the reference ADXL78 and AIS326DQ is clearly visible along with its highly linear full-scale output (FSO) ±16.5 mV (nonlinearity <1% FSO). The phase difference of 180◦ can be explained by the fact that the reference capacitive devices were mounted 180◦ opposite of standard alignment. We obtained a scale factor ∼4 mV/g and a planar cross-axis sensitivity of <1%. Table 3 lists the critical system specifications that define the ‘smart’ accelerometer developed. 6. Conclusion Front-end interfacing and system-scale development and characterization of the SOI MEMS Wheatstone-bridge type piezoresistive accelerometer sensor and the analog front-end ASIC comprising a low-noise high precision variable-gain amplifier with thermal sensitivity and offset compensation schemes forms the basis of this paper with the interdependence of sensor and circuit parameters and the consequent system performance detailed in preceding sections. The hermetically encapsulated MEMS sensor is shown to be a highly linear and robust device while the ASIC achieves extremely low percentage relative sensitivity (PRS) and offset (PRO) compensation errors and the adaptive bridge biasing (Ibias ) circumvents the sensitivity issues arising from CMOS process downscaling. The front-end accomplishes desired low-offset low-noise sensor output conditioning over all bandwidths with minimal values of input referred offset and low frequency flicker noise. While we have quite successfully demonstrated the individual development of the MEMS and the ASIC, issues remain with interfaced MEMS accelerometer solutions such as wafer and PCB area efficiency, interface wire bond failures, and foundry mismatch. Sensor bridge resistance mismatch and subsequent thermal offset and sensitivity compensation errors need to be addressed for better offset and dopant conductance fluctuation induced flicker noise (1/f) performance. Further lowering of IRO/IRN requires even more rigorous post-layout tuning as well as the improvement in layout symmetry and use of smaller passives for performance enhancement. Low power systems may be realized by optimal tuning of the duty cycle of the AZ clocks. Commercialized monolithic MEMS–CMOS integration of resistive bridge-type accelerometers, however, remains incomplete. In this context, exploring modified sensor geometries and foundry processes like poly-SiGe might add new direction to the field of MEMS-based inertial sensing. Acknowledgments The authors would like to thank the Aeronautical Development Agency (ADA) and the National Programme on Micro And Smart

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Biographies

Anindya Lal Roy completed his B.Tech. from the National Institute of Technology (NIT), Durgapur in 2010 and is currently pursuing M.S. (research) at the Indian Institute of Technology (IIT), Kharagpur. He has remained a research fellow at IIT Kharagpur, working on MEMS inertial sensors. He has also been a visiting scholar at the University of Southern California where he worked on inkjet-printed CNT–FETs. His research interests are in the field mesoscopic physics, particularly solid-state implementation and the dynamics of micro/nanoscale systems.

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Hrishikesh Sarkar completed his B.Tech. and M.Tech. from the Institute of Radiophysics and Electronics (IRPEL), University of Calcutta in 2007 and 2009, respectively, and is currently pursuing Ph.D. at the Indian Institute of Technology (IIT), Kharagpur. He has also served as a research fellow at IIT Kharagpur and has been a faculty affiliated to the West Bengal University of Technology (WBUT) prior to returning to full time doctoral research. His interests are in the field of MEMS and their interfacing signal conditioning circuits.

Anupam Dutta completed his B.Tech. and M.S. (research) from the Institute of Radiophysics and Electronics (IRPEL), University of Calcutta in 2007 and 2011, respectively, and the Indian Institute of Technology (IIT), Kharagpur, respectively. He has worked at the Indian Space Research Organization (ISRO) in the field of microprocessor design and his research interests broadly cover electron devices and MEMS–CMOS integration. Currently, he is with the IBM Semiconductor Research and Development Centre and is working on the development of compact models for silicon-based bulk and SOI technologies. Tarun Kanti Bhattacharyya completed his B.Sc. and B.Tech. from the Institute of Radiophysics and Electronics (IRPEL), University of Calcutta in 1984 and 1987 and his M.E. and Ph.D. from Jadavpur University in 1991 and 1996, respectively. He has served as a scientist in national research laboratories like the Indian Association for Cultivation of Science (IACS), Central Glass and Ceramic Research Institute (CGCRI) as well as the University of Kaiserslautern. His research interests include thin film sensors, spintronics, MEMS–CMOS integration, low power RF and mixed signal circuits and nanoelectronics. He is currently an Associate Professor at the Indian Institute of Technology (IIT), Kharagpur and has served as a visiting faculty at the Universities of Michigan, Washington and California (Irvine). He has been awarded the UNIDO (Vienna) fellowship and the IBM outstanding faculty award for his contributions to science and engineering and handles several international (Indo–Italy, Indo–Japan, Indo–US) collaborative projects at IIT Kharagpur.