- Email: [email protected]
A high-speed differential resistor ladder
Microelectronics Journal 43 (2012) 433–438
Contents lists available at SciVerse ScienceDirect
Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
A high-speed differential resistor ladder D. De Caro n, M. Coppola, N. Petra Department of Electronic and Telecommunications Engineering, University of Napoli ‘‘Federico II’’, via Claudio 21, I-80125 Napoli, Italy
a r t i c l e i n f o
abstract
Article history: Received 13 September 2011 Received in revised form 2 March 2012 Accepted 6 March 2012 Available online 29 March 2012
This paper describes the implementation of a novel high speed differential resistor ladder. In this paper it is shown that the novel ladder yields, theoretically, up to a sixteen fold reduction of the propagation delay with respect to the conventional differential ladder. In order to ease the design process, an accurate analytical model for the ladder INL is also derived in the paper. Simulation results, for a BiCMOS 0.25 mm technology, show that the novel ladder results in a fivefold increase of the maximum sampling frequency when employed to design an 8 bit Flash converter. A 65% higher speed is also highlighted when the ladder is employed in a Folding and Interpolating 8 bit converter. & 2012 Elsevier Ltd. All rights reserved.
Keywords: Analog–digital conversion Analog folding Folding/interpolation Resistor ladder
1. Introduction The resistor ladder is one of the key elements in the development of a high speed A/D converter (ADC). In Flash ADCs [1–4] the resistor ladder generates the reference voltages which correspond to the quantization thresholds of the converter. Performances higher than Flash converters are obtained by using Folding and Interpolating architectures [5–14]. The resistor ladder is still one of the basic elements of these converters, where it generates the set of reference voltages required by the folders. Although in Folding and Interpolating ADCs the array length is reduced, the resistor ladder remains one of the main performance bottlenecks [14]. In the following sections we will focus on a resistor ladder with N-1 thresholds (N ¼2n in an n-bit Flash ADC). Basically we can distinguish between two ladder topologies: single-ended and differential. In single-ended ladders, generally employed in CMOS converters [3–7], the input voltage is compared with a set of N-1 voltages generated by a resistor divider. In bipolar implementations this solution is generally not preferred since the INL of the converter becomes proportional to N2, because of DC bowing effect [1]. Apparently the resistor divider voltages are static. However, due to capacitive feedthrough, the input signal switching excites a transient of the resistor divider voltages [1,7]. Because of this phenomenon (known as AC bowing effect) the ADC speed becomes dependent on N. AC bowing effect can be alleviated by inserting decoupling capacitances or buffers, with a heavy price paid in terms of silicon area.
n
Corresponding author. Tel.: þ39 081 768 3680; fax: þ39 081 768 5925. E-mail address: [email protected] (D. De Caro).
0026-2692/$ - see front matter & 2012 Elsevier Ltd. All rights reserved. http://dx.doi.org/doi:10.1016/j.mejo.2012.03.006
Differential ladders are generally the preferred choice in bipolar ADCs [9–14]. In these circuits the differential input voltage propagates through two N-resistors arrays, and the threshold voltages correspond to the zero-crossing points of the differential voltages across the two arrays. In addition to well known advantages of differential against single-ended topologies, like the rejection of common mode noise, the main advantage of differential resistor ladder is the reduced INL [15]. In fact, as we will also see in the following sections, in differential ladders the DC bowing effect, completely or partially, appears as a common mode and is therefore, in large part, canceled by the differential nature of the circuit. The main drawback of differential ladders is the speed. In fact the maximum sampling frequency of the converter is limited by the settling time of the arrays, which is proportional to N2. Two techniques can be used to speed-up bipolar ADCs: distributed sample and hold (SH) [14], and high-speed ladders [9,10]. As an example the differential ladder proposed in Refs. [9,10] can achieve up to a fourfold reduction of the array settling time, with respect to a conventional differential array. However, as we will show in the following sections, this improvement is paid with a worsening of the converter INL. In this paper a novel differential resistor ladder is proposed [16]. The novel array can achieve, theoretically, up to a sixteen fold reduction of the settling time and a noticeable reduction of INL with respect to the conventional differential ladder. The paper is organized as follows: Section 2 recalls the conventional resistor ladder. The novel resistor ladder is described in Section 3. In this section it is also given an analytical model for both the ladder INL and the propagation delay. Section 4 reports the simulated INL of the different ladders, for different N values.
434
D. De Caro et al. / Microelectronics Journal 43 (2012) 433–438
Finally Section 5 presents the simulated performances of Flash and Folding/Interpolating ADC using the different resistor ladders.
2. Conventional resistor ladder Fig. 1 shows the conventional differential ladder. We define Vd j ¼Vp j Vn j the differential output voltages of the ladder. In this case the ladder threshold voltages Vrj correspond to the differential input voltages for which Vd j ¼0. A simple analysis of the circuit reveals that, in the hypothesis Ip j ¼In j ¼0, the threshold voltages are V ref N ð1Þ j Vr j ¼ 2 N
Fig. 2. Typical differential ladder loads both in Flash and in Folding and Interpolating converters: (a) differential pair driven by two emitter followers; (b) simple differential pair.
if the following bias current Iref is imposed: Iref ¼
1 V ref 2 NUR
ð2Þ
This equation can be easily verified by compensating PVT variations with a simple feedback circuit (see Ref. [12]). The non-linearity of the ladder depends on the load currents Ip j and In j. In a Flash converter the ladder is loaded with the input stages of the comparators; in a Folding and Interpolating converter the load of the ladder is composed by the input stages of the folders. Fig. 2 depicts the two typical loads of the single ladder output (Vp j, Vn j) in both cases. In Fig. 2a the load is composed by a differential pair driven by two emitter followers. In this case all input currents are almost equal each other and do not depend on the differential input voltage Vd j ¼Vp j Vn j: Ip1 ¼y¼ Ip N-1 ¼ In1 ¼y¼In N-1 ¼IDC. In this condition the circuit does not exhibit the DC bowing effect (see Ref. [15]). This can be intuitively explained: if all the currents Ip j, In j are equal, each of the two resistive arrays in Fig. 1 exhibits a non-linearity symmetric around j¼ N/2 [1]. Therefore, the INL of each array becomes a common mode component for the voltages Vd j (see Fig. 1) and is canceled by the CMRR of the differential pair of Fig. 2a. Fig. 2b depicts a situation in which the load of the single ladder output is composed by a simple differential pair. With respect to Fig. 2a, this solution gives a reduced offset voltage and propagation delay [1,6]. In this case, however, the input currents Ip j and In j
Fig. 3. Proposed differential Resistor Ladder for N ¼ 8.
become a function of the differential input voltage Vd j. The currents Ip j and In j are different and the non-linearity of each array is no longer symmetric. As a consequence the single arrays’ non-linearities are not perfectly canceled by the differential topology and a DC bowing effect arises. CMOS differential pairs exhibit a DC input current almost negligible. From the ladder point of view the employment of CMOS load circuits can be considered similar to the case of Fig. 2a, where DC input currents are constant. The main drawback of the differential ladder is the long propagation delay (tp) of the input signals through the two resistor arrays. In a first order approximation we can write tp
N2 RC 2
ð3Þ
where C is the load capacitance of each output node Vp j or Vn j.
3. Proposed resistor ladder
Fig. 1. Conventional Differential Ladders for N ¼8.
The schematic of the proposed differential resistor ladder is shown in Fig. 3 for the case N¼8. In this circuit the input signal Vin þ is applied to a first array composed by only two resistors. The three voltages, Va þ , Vb þ and Vc þ , generated by the first array, drive, through three emitter followers (Ba p, Bb p, Bc p), a second array, composed by N resistors. This second array is split by Va þ , Vb þ and Vc þ into two sub-arrays. The upper sub-array is biased with a voltage given by Va þ Vb þ ¼Vref/4 (if Eq. (2) is assumed). The lower sub-array is biased with a voltage Vb þ Vc þ which is also equal to Vref/4. The same reasoning can be applied to the two resistor arrays driven by Vin , on the right side of the figure. If we neglect the currents Ip j, In j, by comparing the circuit in Fig. 3 with the
D. De Caro et al. / Microelectronics Journal 43 (2012) 433–438
conventional differential ladder shown in Fig. 1, we can observe that the voltage drop on each sub-array (of N/2 resistors) is exactly the same between the two circuits. Since the arrays in the two circuits are biased with the same voltages, we can conclude that also the circuit of Fig. 3 gives the threshold voltages given by Eq. (1). As we will highlight in the following sections, from the design point of view, the first arrays are sensibly less critical with respect to the second arrays. This allows optimizing the power dissipation of proposed circuit, by biasing the first arrays with a current k times lower than the biasing current of the second arrays (Iref), as shown in Fig. 3. We will discuss the choice of the design parameter k, in Section 3.2. Another design parameter is the buffer biasing current Ibuff, whose choice will be detailed in Section 3.1. 3.1. Ladder non-linearity (INL) With reference to the linearity of the ladder, we can distinguish three contributions. The contribution of the first arrays, which generate Va þ , Vb þ , Vc þ , Va , Vb and Vc , is almost negligible since these arrays are composed by only two resistors and, in addition, they are loaded with almost constant currents. The second contribution is due to the load currents of the six buffers. Our design experience shows that this contribution can be easily made negligible with a careful choice of the buffers’ bias current. It can be noted that the offset voltages of the buffers may also impact the ladder INL. This effect, however, tends to be canceled by the CMRR of the ladder load, and, therefore, becomes again ascribable to a load effect. The final contribution, due to the four sub-arrays of N/2 resistors each, is the real linearity bottleneck. In the following sections, therefore, we will focus on this last contribution. Also in the case of proposed ladder we can distinguish between the two load cases of Fig. 2a and Fig. 2b. When the currents Ip j, In j are all equal (assuming the topology of Fig. 2a), each sub-array exhibits a symmetric non-linearity. This non-linearity is, therefore canceled by the CMRR of the differential pair of Fig. 2a. On the other hand, when the currents Ip j, In j are not equal (assuming the topology of Fig. 2b), asymmetries arise which result in a non-linear behavior. In order to come to an analytical expression of the INL in the latter case, we define V 0p j
¼ V p j 9V i n þ
; V 0n j ¼0
¼ V n j 9V i n ¼ 0
ð4Þ
From this definition we can also write V d j ¼ V i n þ V i n þV 0p j V 0n j
ð5Þ
Since Vrj ¼ (Vi n þ Vi n )9Vdj ¼ 0 we have Vr j ¼ V 0n j V 0p j
ð6Þ
From this last equation the INL of the whole ladder (INLj) can be written as INLj ¼ INLn j INLp j
ð7Þ
where INLp j and INLn j are the INL of Vp j and Vn j voltages respectively. The proposed circuit, see Fig. 3, is perfectly symmetric around the middle point j ¼N/2. We can therefore limit our study to j ¼1,y,N/2 1. We start by considering the INL of Vp j voltages. Fig. 4a shows the circuit needed to calculate INLp j, after the application of superposition principle. In this circuit rout represents the output resistance of the voltage buffers. Note that, for simplicity, we have neglected the effect of the currents and the resistances of the second sub-array (between Vb þ and Vc þ ) on the first sub-array (between Va þ and Vb þ ).1 1 This is not exactly true due to the presence of rout. As we will see later, however, our approach results in a very good approximation.
435
Fig. 4. Circuits for the calculation of INLp j: (a) circuit after the application of superposition principle; (b) circuit simplified with the Norton theorem.
In the case we are considering (Fig. 2b), the currents Ip i are different each other and depend on Vd i. For the computation of the INL of Vp j, it is interesting to observe that Vd i is zero for i¼j, it is positive for ioj and negative for i4j. We have verified that a very good approximation of the INL is obtained by using the following very simple model for Ip i currents: 8 io j > < IB =2 i ¼j I Ip i ¼ ð8Þ B > :0 i4 j where IB represents the maximum load current of the differential pair (IB ¼IEE/b), see Fig. 2b. In this hypothesis, Fig. 4b shows the circuit of Fig. 4a, simplified by employing the Norton theorem on the left of jth node. In this circuit the Norton equivalent current (Ieq) is given by j1 X iUR þ r out j1 r out IB 1 þ IB ¼ ð9Þ Ieq ¼ 2 jUR þ r out jURþ r out i¼1 The voltage Vp j can be easily computed from Fig. 4b: IB ðj þr out =RÞUðN=2j þ r out =RÞ URU V p j ¼ Ieq þ N=2 þ 2r out =R 2
ð10Þ
The INLp j can be easily obtained from Vp j after the cancellation of gain and offset errors:2 INLp j ¼ V p j
V p N=2 V p 0 jV p 0 N=2
ð11Þ
After the substitution of Eqs. (9), (10) and simple algebraic manipulations, Eq. (11) becomes j N r out j U j þ U URIB ð12Þ INLp j ¼ N þ 4r out =R 2 R Let us now consider the negative sub-array, again for j¼1,y,N/2 1. In this case we can repeat the same reasoning of positive sub-array. The only difference, revealed by observing Fig. 3, is that now 8 i oj > <0 In i ¼ IB =2 i ¼ j ð13Þ > :I i 4j B Comparing this equation with Eq. (8) we can conclude that INLn j ¼ INLp N=2j
ð14Þ
By using this equation the INLn j can be computed from Eq. (12). In conclusion by substituting this equation and Eq. (12) in Eq. (7) we have the INL of the whole array: INLj ¼
j 8j2 6jN þN 2 U URIB 4N 1 þ4r out =ðNURÞ
j ¼ 1,:::,N=21
ð15Þ
2 In this work the INL is defined as the deviation from the endpoint-fit line (see Ref. [2]).
436
D. De Caro et al. / Microelectronics Journal 43 (2012) 433–438
An important design parameter is the maximum INL (INLmax). In order to compute INLmax we can simply derive Eq. (15) and impose the derivative equal to zero. By proceeding in this way two solutions are obtained: pffiffiffi! N 3 17 jmax ¼ ð16Þ 4 3
It is interesting to observe that, according to Eq. (19) the propagation delay of the four sub-arrays is proportional to N2 R. The first arrays are biased with a current given by Iref/k, therefore the delay of the first arrays is proportional to k N R. We can therefore conclude that the delay of the first arrays is negligible if k5 N
ð20Þ
The maximum INL obtained with these two solutions is INLmax ¼
N2 RIB 1 pffiffiffi U rout 48 3 1 þ4 NR
ð17Þ
Both in Eq. (15) and in Eq. (17), the effect of rout is negligible when rout 5N R. From a design point of view this hypothesis is generally verified since the buffers have to be much faster than the whole array. It is also interesting to observe that, at the first order, the buffer non-linearity can be modeled as an output resistance dependent on the output current, that is, rout depends on j in Eq. (15). This suggests that, in the hypothesis rout 5N R, also the buffer non-linearities are negligible. From the expression (17) it is interesting to observe that the INLmax is proportional to N2 if rout 5N R. In this hypothesis, the proposed ladder results in more than one order of magnitude lower INLmax with respect to conventional single-ended ladder (INLmax ¼1/8N2IBR), see Ref. [1]. The resistance rout depends on the buffer biasing current Ibuff: rout EVT/Ibuff. The relationship rout 5N R therefore becomes Ibuf f b
VT NR
ð18Þ
A very good choice can be Ibuff ¼ Iref. This choice, in fact, respects Eq. (18) since Vref bVT (see Eq. (2)). In addition by choosing Ibuff ¼Iref, it is possible to completely simplify the biasing current generator of the two buffers Ba p and Ba n in Fig. 3. These buffers, in fact, become biased directly by the biasing currents of the second arrays. 3.2. Propagation delay (tp) The main advantage of the proposed circuit against the conventional topology is the speed. In fact, the most relevant contribution to the signal propagation delay in the topology of Fig. 3 is due to the four sub-arrays. In this case, the slowest signals are the four midpoints of each sub-array. Therefore, neglecting the delays of the first arrays and of the buffers, we can write tp
ðN=4Þ2 RC 2
ð19Þ
Eq. (19) corresponds to a sixteen fold reduction of the propagation delay, with respect to Eq. (3).
4. Resistor ladders performances The proposed resistor ladder has been designed for a BiCMOS 0.25 mm technology by using 50 GHz NPN HBT devices. For comparison also the conventional differential ladder and the high-speed ladder proposed in Refs. [9,10] have been designed in the same technology. In the following sections we will consider two N values: 64 and 256. For each N value all ladders have been designed and simulated by considering two R values: 1 O and 2.5 O. All arrays have been loaded with the topology of Fig. 2b, which, as observed before, represents both the most critical and the most common case. The proposed ladders with N ¼ 64 use k¼2, while k is equal to 4 for ladders with N ¼256. We have verified that this choice has a minimal impact both on delay and INL. In addition in all circuits Ibuff ¼Iref. Fig. 5a compares the simulated INL of the different ladders with N ¼256 and R¼1 O. It is interesting to observe that the highspeed ladder [9,10] shows a higher non-linearity with respect to conventional ladder both for N ¼64 and N ¼256. The lowest INL is obtained by using the proposed ladder. Fig. 5b compares the simulated and analytical INL (Eq. (15)) for the ladder with N ¼ 256 and R¼1 O. This figure highlights the very good agreement between analytical model and simulation, by giving a confirmation both of considered assumptions and proposed design strategy. The INLmax obtained in all considered ladders is reported in Table 1. The proposed ladder results in all cases in the lowest INLmax. The comparison between analytical and simulated INL confirms again the very good accuracy of the analytical INL model described in Section 3.1. Fig. 6 compares a transient simulation of the proposed ladder with the simulations of the conventional and high-speed ladder of Refs. [9,10], for N¼256. This simulation considers a full swing switch of the ladder input voltage. In these conditions the proposed ladder is clearly faster with respect to the other circuits, with a propagation delay as low as 0.6 ns. It is worth to highlight that the propagation delay may vary considerably as a function of considered ladder output or input voltage switch. A real measure of the ladder speed can only be obtained by inserting the ladder in the ADC and by measuring the total harmonic distortion (THD) of the
Fig. 5. Simulated ladders INL for N ¼ 256 and R¼ 1 O: (a) comparison among simulated ladders; (b) comparison between simulated and analytical INL of proposed ladder.
D. De Caro et al. / Microelectronics Journal 43 (2012) 433–438
converter as a function of sampling rate. This analysis is presented in the next section.
5. A/D Converters Performances In order to have a real indication of the performances of the proposed ladder we designed several ADCs using both Flash and Folding/Interpolating topologies. In the case of Flash converters, we considered two circuits: a 6 bit converter (N ¼64) and an 8 bit converter (N ¼256). Each circuit has been designed by using the three different ladder topologies (conventional, high-speed [9,10] and proposed) and two different R values for each topology (1 O, 2.5 O). All circuits employ the comparator described in Ref. [6] (based on the input stage of Fig. 2b) and an ideal track and hold amplifier. Fig. 7 shows the effective number of bits extracted from the THD and the signal to noise and distortion ratio (SNDR) obtained by simulating the 8 bit Flash converter using the proposed ladder. In graph of Fig. 7, the converter sampling frequency (fsample) is varied between 50 MHz and 1 GHz. The input frequency of the converter has been chosen according to Nyquist criterion (fsample/2). Since an ideal Track-and-Hold is inserted at the input of the converter, this condition corresponds to evaluate the worst-case performances for each considered fsample. At low sampling frequencies the converter exhibits a THD of 9 bit, limited by the ladder INL. The resulting SNDR (which includes also quantization noise) is slightly lower than 8 bit. By increasing the sampling frequency, due to limited ladder speed, a dynamic non-linear
437
behavior is introduced, which worsens the THD. For fsample ffi 600 MHz, the SNDR drops by 3 dB compared to its low frequency value. From the Shannon theorem we can conclude that the effective resolution bandwidth (ERB) of this converter is 600/2¼300 MHz. Table 2 reports the ERB obtained by simulating Flash ADCs designed by using the proposed, the conventional and the high speed [9,10] ladder topologies. This table includes also Power Dissipation data and Figure of Merit performance, computed according to Ref. [17] (FOM ¼PD/(2ERB 2ENOB)). By considering the 8 bit converters, we note that the fastest solution is obtained by using the proposed ladder with R¼1 O. This solution results in an ERB which is 4.6 times and 2.4 times higher than the ERB of converters employing conventional and high-speed [9,10] ladder topologies, respectively. It is also interesting to note that the proposed ladder with R ¼2.5 O dissipates about the same power of the conventional ladder with R ¼1 O, while providing a 3.2 times higher ERB. By looking to the FOM performances, we note that, if we consider the ladder only, the proposed ladder with R¼2.5 O, results in the better FOM. If, on the other hand, we consider the whole Flash converter, the solution with the best FOM is the one employing the proposed ladder with R¼1 O. From the power dissipation data reported in Table 2, in fact, we note that the power dissipation of the converters is dominated by the comparators. As a consequence the ladder sizing has a little impact of the converter power dissipation and a strong impact on the converter ERB. As a consequence the best sizing strategy at the level of the whole converter is having a high-speed and power hungry ladder. The analysis of 6 bit ladders and converters reported in Table 2, highlights a picture similar to the previous 8 bit case.
Table 1 INLmax of considered Resistor Ladders.
Fig. 7. Simulated effective number of bits (ENOB) extracted from the THD and the SNDR for the 8-bit Flash converter using proposed ladder with R¼ 1 O.
Fig. 6. Transient simulation of the three ladders (N ¼ 256, R¼ 1 O).
438
D. De Caro et al. / Microelectronics Journal 43 (2012) 433–438
Table 2 Effective Resolution Bandwidth (ERB) Power Dissipation (PD) and Figure of Merit (FOM) of Simulated Ladders and Flash Converters.
Table 3 Effective resolution bandwidth (ERB) power dissipation (PD) and figure of merit (FOM) of simulated folding and interpolating converters.
Table 3 reports the simulated performances of Folding and Interpolating converters employing the topology described in Refs. [9–11]. Two converters have been considered with a resolution of 8 bit and 9 bit, respectively. The 8 bit converter uses a ladder with N ¼42, while the 9 bit converter employs a ladder with N ¼82. The analysis of the data reported in Table 3 confirms that proposed ladder topology is useful also in improving both ERB and FOM of Folding and Interpolating converters. As an example the 9 bit Folding and Interpolating converter employing the proposed ladder results in an ERB which is about 1.8 times higher than the EBR of the same converter employing the conventional ladder.
6. Conclusions In this paper we have presented a novel differential ladder topology. As we have shown, the main advantage of proposed solution is decreasing the settling time of the ladder. When employed in Flash or in Folding and Interpolating converters this characteristic allows a substantial increase of the sampling frequency with respect to other ladder circuits.
References [1] B. Razavi, Principles of Data Conversion System Design, IEEE Press, 1995. [2] F. Maloberti, Data Converters, Springer, 2007. [3] A. Ismail, M. Elmasry, A 6-bit 1.6-GS/s low-power wideband flash ADC converter in 0.13-mm CMOS technology, IEEE J. Solid-State Circuits 43 (9) (2008) 1982–1990. [4] H. Yu, M.C.F. Chang, A 1-V 1.25-GS/S 8-bit self-calibrated flash ADC in 90-nm digital CMOS, IEEE Trans. Circuits Syst.-II: Express Briefs 55 (7) (2008) 668–672. [5] M.P. Flynn, B. Sheahan, A 400-Msample/s, 6-b CMOS folding and interpolating ADC, IEEE J. Solid-State Circuits 33 (12) (1998) 1932–1938. [6] F. Vessal, C.A.T. Salama, An 8-bit 2-Gsample/s folding-interpolating analogto-digital converter in SiGe technology, IEEE J. Solid-State Circuits 39 (1) (2004) 238–241. [7] A.G.W. Venes, R.J. van de Plassche, An 80-MHz, 80-mW, 8-b CMOS folding A/D converter with distributed track-and-hold preprocessing, IEEE J. SolidState Circuits 31 (12) (1996) 1846–1853. [8] H. Pan, A.A. Abidi, Signal Folding in A/D Converters, IEEE Trans. Circuits Syst. I: Regular Pap. 51 (2004) 3–14. [9] H. Kobayashi, et al., Design consideration for folding/interpolation ADC with SiGe HBT, Proc Instrum. Meas, Tech. Conf. 2 (1997) 1142–1147. IMTC/97. [10] H. Kobayashi, et al., A high speed 6 bit ADC using SiGe HBT, IEICE Trans. Fundam. 3 (1998) 389–397. E81-A. [11] H. Kobayashi, et al., AC performance improvement of folding/interpolation ADC with SiGe HBT, Proc Instrum. Meas. Tech. Conf. (1998) 1385–1390. IMTC/98. [12] P. Vorenkamp, R. Roovers, A 12-b, 60-M sample/s cascaded folding and interpolating ADC, IEEE J. Solid-State Circuits 32 (12) (1997) 1876–1886. [13] J. Lee, et al., A 5-b 10 G sample/s A/D converter for 10 Gb/s optical receivers, IEEE J. Solid-State Circuits 39 (10) (2004) 1671–1679. [14] B. Chan, et al., An ultra-wideband 7-bit 5-Gsps ADC implemented in submicron InP HBT technology, IEEE J. Solid-State Circuits 43 (10) (2008) 2187–2193. [15] W. Colleran, A 10bit 100 MS/s A/D Converter using Folding, Interpolation, and Analog Encoding, Ph.D. Dissertation, UCLA, Dec. 1993. [16] D. De Caro, M. Coppola, N. Petra, E. Napoli, A.G.M. Strollo, V. Garofalo, High speed differential resistor ladder for A/D converters, Proc. IEEE Int. Symp. Circuits Systems (ISCAS) (2010) 1723–1726. [17] R.H. Walden, Analog-to-digital converter survey and analysis, IEEE J. Sel. Areas Commun. 17 (4) (1999).
Contents lists available at SciVerse ScienceDirect
Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
A high-speed differential resistor ladder D. De Caro n, M. Coppola, N. Petra Department of Electronic and Telecommunications Engineering, University of Napoli ‘‘Federico II’’, via Claudio 21, I-80125 Napoli, Italy
a r t i c l e i n f o
abstract
Article history: Received 13 September 2011 Received in revised form 2 March 2012 Accepted 6 March 2012 Available online 29 March 2012
This paper describes the implementation of a novel high speed differential resistor ladder. In this paper it is shown that the novel ladder yields, theoretically, up to a sixteen fold reduction of the propagation delay with respect to the conventional differential ladder. In order to ease the design process, an accurate analytical model for the ladder INL is also derived in the paper. Simulation results, for a BiCMOS 0.25 mm technology, show that the novel ladder results in a fivefold increase of the maximum sampling frequency when employed to design an 8 bit Flash converter. A 65% higher speed is also highlighted when the ladder is employed in a Folding and Interpolating 8 bit converter. & 2012 Elsevier Ltd. All rights reserved.
Keywords: Analog–digital conversion Analog folding Folding/interpolation Resistor ladder
1. Introduction The resistor ladder is one of the key elements in the development of a high speed A/D converter (ADC). In Flash ADCs [1–4] the resistor ladder generates the reference voltages which correspond to the quantization thresholds of the converter. Performances higher than Flash converters are obtained by using Folding and Interpolating architectures [5–14]. The resistor ladder is still one of the basic elements of these converters, where it generates the set of reference voltages required by the folders. Although in Folding and Interpolating ADCs the array length is reduced, the resistor ladder remains one of the main performance bottlenecks [14]. In the following sections we will focus on a resistor ladder with N-1 thresholds (N ¼2n in an n-bit Flash ADC). Basically we can distinguish between two ladder topologies: single-ended and differential. In single-ended ladders, generally employed in CMOS converters [3–7], the input voltage is compared with a set of N-1 voltages generated by a resistor divider. In bipolar implementations this solution is generally not preferred since the INL of the converter becomes proportional to N2, because of DC bowing effect [1]. Apparently the resistor divider voltages are static. However, due to capacitive feedthrough, the input signal switching excites a transient of the resistor divider voltages [1,7]. Because of this phenomenon (known as AC bowing effect) the ADC speed becomes dependent on N. AC bowing effect can be alleviated by inserting decoupling capacitances or buffers, with a heavy price paid in terms of silicon area.
n
Corresponding author. Tel.: þ39 081 768 3680; fax: þ39 081 768 5925. E-mail address: [email protected] (D. De Caro).
0026-2692/$ - see front matter & 2012 Elsevier Ltd. All rights reserved. http://dx.doi.org/doi:10.1016/j.mejo.2012.03.006
Differential ladders are generally the preferred choice in bipolar ADCs [9–14]. In these circuits the differential input voltage propagates through two N-resistors arrays, and the threshold voltages correspond to the zero-crossing points of the differential voltages across the two arrays. In addition to well known advantages of differential against single-ended topologies, like the rejection of common mode noise, the main advantage of differential resistor ladder is the reduced INL [15]. In fact, as we will also see in the following sections, in differential ladders the DC bowing effect, completely or partially, appears as a common mode and is therefore, in large part, canceled by the differential nature of the circuit. The main drawback of differential ladders is the speed. In fact the maximum sampling frequency of the converter is limited by the settling time of the arrays, which is proportional to N2. Two techniques can be used to speed-up bipolar ADCs: distributed sample and hold (SH) [14], and high-speed ladders [9,10]. As an example the differential ladder proposed in Refs. [9,10] can achieve up to a fourfold reduction of the array settling time, with respect to a conventional differential array. However, as we will show in the following sections, this improvement is paid with a worsening of the converter INL. In this paper a novel differential resistor ladder is proposed [16]. The novel array can achieve, theoretically, up to a sixteen fold reduction of the settling time and a noticeable reduction of INL with respect to the conventional differential ladder. The paper is organized as follows: Section 2 recalls the conventional resistor ladder. The novel resistor ladder is described in Section 3. In this section it is also given an analytical model for both the ladder INL and the propagation delay. Section 4 reports the simulated INL of the different ladders, for different N values.
434
D. De Caro et al. / Microelectronics Journal 43 (2012) 433–438
Finally Section 5 presents the simulated performances of Flash and Folding/Interpolating ADC using the different resistor ladders.
2. Conventional resistor ladder Fig. 1 shows the conventional differential ladder. We define Vd j ¼Vp j Vn j the differential output voltages of the ladder. In this case the ladder threshold voltages Vrj correspond to the differential input voltages for which Vd j ¼0. A simple analysis of the circuit reveals that, in the hypothesis Ip j ¼In j ¼0, the threshold voltages are V ref N ð1Þ j Vr j ¼ 2 N
Fig. 2. Typical differential ladder loads both in Flash and in Folding and Interpolating converters: (a) differential pair driven by two emitter followers; (b) simple differential pair.
if the following bias current Iref is imposed: Iref ¼
1 V ref 2 NUR
ð2Þ
This equation can be easily verified by compensating PVT variations with a simple feedback circuit (see Ref. [12]). The non-linearity of the ladder depends on the load currents Ip j and In j. In a Flash converter the ladder is loaded with the input stages of the comparators; in a Folding and Interpolating converter the load of the ladder is composed by the input stages of the folders. Fig. 2 depicts the two typical loads of the single ladder output (Vp j, Vn j) in both cases. In Fig. 2a the load is composed by a differential pair driven by two emitter followers. In this case all input currents are almost equal each other and do not depend on the differential input voltage Vd j ¼Vp j Vn j: Ip1 ¼y¼ Ip N-1 ¼ In1 ¼y¼In N-1 ¼IDC. In this condition the circuit does not exhibit the DC bowing effect (see Ref. [15]). This can be intuitively explained: if all the currents Ip j, In j are equal, each of the two resistive arrays in Fig. 1 exhibits a non-linearity symmetric around j¼ N/2 [1]. Therefore, the INL of each array becomes a common mode component for the voltages Vd j (see Fig. 1) and is canceled by the CMRR of the differential pair of Fig. 2a. Fig. 2b depicts a situation in which the load of the single ladder output is composed by a simple differential pair. With respect to Fig. 2a, this solution gives a reduced offset voltage and propagation delay [1,6]. In this case, however, the input currents Ip j and In j
Fig. 3. Proposed differential Resistor Ladder for N ¼ 8.
become a function of the differential input voltage Vd j. The currents Ip j and In j are different and the non-linearity of each array is no longer symmetric. As a consequence the single arrays’ non-linearities are not perfectly canceled by the differential topology and a DC bowing effect arises. CMOS differential pairs exhibit a DC input current almost negligible. From the ladder point of view the employment of CMOS load circuits can be considered similar to the case of Fig. 2a, where DC input currents are constant. The main drawback of the differential ladder is the long propagation delay (tp) of the input signals through the two resistor arrays. In a first order approximation we can write tp
N2 RC 2
ð3Þ
where C is the load capacitance of each output node Vp j or Vn j.
3. Proposed resistor ladder
Fig. 1. Conventional Differential Ladders for N ¼8.
The schematic of the proposed differential resistor ladder is shown in Fig. 3 for the case N¼8. In this circuit the input signal Vin þ is applied to a first array composed by only two resistors. The three voltages, Va þ , Vb þ and Vc þ , generated by the first array, drive, through three emitter followers (Ba p, Bb p, Bc p), a second array, composed by N resistors. This second array is split by Va þ , Vb þ and Vc þ into two sub-arrays. The upper sub-array is biased with a voltage given by Va þ Vb þ ¼Vref/4 (if Eq. (2) is assumed). The lower sub-array is biased with a voltage Vb þ Vc þ which is also equal to Vref/4. The same reasoning can be applied to the two resistor arrays driven by Vin , on the right side of the figure. If we neglect the currents Ip j, In j, by comparing the circuit in Fig. 3 with the
D. De Caro et al. / Microelectronics Journal 43 (2012) 433–438
conventional differential ladder shown in Fig. 1, we can observe that the voltage drop on each sub-array (of N/2 resistors) is exactly the same between the two circuits. Since the arrays in the two circuits are biased with the same voltages, we can conclude that also the circuit of Fig. 3 gives the threshold voltages given by Eq. (1). As we will highlight in the following sections, from the design point of view, the first arrays are sensibly less critical with respect to the second arrays. This allows optimizing the power dissipation of proposed circuit, by biasing the first arrays with a current k times lower than the biasing current of the second arrays (Iref), as shown in Fig. 3. We will discuss the choice of the design parameter k, in Section 3.2. Another design parameter is the buffer biasing current Ibuff, whose choice will be detailed in Section 3.1. 3.1. Ladder non-linearity (INL) With reference to the linearity of the ladder, we can distinguish three contributions. The contribution of the first arrays, which generate Va þ , Vb þ , Vc þ , Va , Vb and Vc , is almost negligible since these arrays are composed by only two resistors and, in addition, they are loaded with almost constant currents. The second contribution is due to the load currents of the six buffers. Our design experience shows that this contribution can be easily made negligible with a careful choice of the buffers’ bias current. It can be noted that the offset voltages of the buffers may also impact the ladder INL. This effect, however, tends to be canceled by the CMRR of the ladder load, and, therefore, becomes again ascribable to a load effect. The final contribution, due to the four sub-arrays of N/2 resistors each, is the real linearity bottleneck. In the following sections, therefore, we will focus on this last contribution. Also in the case of proposed ladder we can distinguish between the two load cases of Fig. 2a and Fig. 2b. When the currents Ip j, In j are all equal (assuming the topology of Fig. 2a), each sub-array exhibits a symmetric non-linearity. This non-linearity is, therefore canceled by the CMRR of the differential pair of Fig. 2a. On the other hand, when the currents Ip j, In j are not equal (assuming the topology of Fig. 2b), asymmetries arise which result in a non-linear behavior. In order to come to an analytical expression of the INL in the latter case, we define V 0p j
¼ V p j 9V i n þ
; V 0n j ¼0
¼ V n j 9V i n ¼ 0
ð4Þ
From this definition we can also write V d j ¼ V i n þ V i n þV 0p j V 0n j
ð5Þ
Since Vrj ¼ (Vi n þ Vi n )9Vdj ¼ 0 we have Vr j ¼ V 0n j V 0p j
ð6Þ
From this last equation the INL of the whole ladder (INLj) can be written as INLj ¼ INLn j INLp j
ð7Þ
where INLp j and INLn j are the INL of Vp j and Vn j voltages respectively. The proposed circuit, see Fig. 3, is perfectly symmetric around the middle point j ¼N/2. We can therefore limit our study to j ¼1,y,N/2 1. We start by considering the INL of Vp j voltages. Fig. 4a shows the circuit needed to calculate INLp j, after the application of superposition principle. In this circuit rout represents the output resistance of the voltage buffers. Note that, for simplicity, we have neglected the effect of the currents and the resistances of the second sub-array (between Vb þ and Vc þ ) on the first sub-array (between Va þ and Vb þ ).1 1 This is not exactly true due to the presence of rout. As we will see later, however, our approach results in a very good approximation.
435
Fig. 4. Circuits for the calculation of INLp j: (a) circuit after the application of superposition principle; (b) circuit simplified with the Norton theorem.
In the case we are considering (Fig. 2b), the currents Ip i are different each other and depend on Vd i. For the computation of the INL of Vp j, it is interesting to observe that Vd i is zero for i¼j, it is positive for ioj and negative for i4j. We have verified that a very good approximation of the INL is obtained by using the following very simple model for Ip i currents: 8 io j > < IB =2 i ¼j I Ip i ¼ ð8Þ B > :0 i4 j where IB represents the maximum load current of the differential pair (IB ¼IEE/b), see Fig. 2b. In this hypothesis, Fig. 4b shows the circuit of Fig. 4a, simplified by employing the Norton theorem on the left of jth node. In this circuit the Norton equivalent current (Ieq) is given by j1 X iUR þ r out j1 r out IB 1 þ IB ¼ ð9Þ Ieq ¼ 2 jUR þ r out jURþ r out i¼1 The voltage Vp j can be easily computed from Fig. 4b: IB ðj þr out =RÞUðN=2j þ r out =RÞ URU V p j ¼ Ieq þ N=2 þ 2r out =R 2
ð10Þ
The INLp j can be easily obtained from Vp j after the cancellation of gain and offset errors:2 INLp j ¼ V p j
V p N=2 V p 0 jV p 0 N=2
ð11Þ
After the substitution of Eqs. (9), (10) and simple algebraic manipulations, Eq. (11) becomes j N r out j U j þ U URIB ð12Þ INLp j ¼ N þ 4r out =R 2 R Let us now consider the negative sub-array, again for j¼1,y,N/2 1. In this case we can repeat the same reasoning of positive sub-array. The only difference, revealed by observing Fig. 3, is that now 8 i oj > <0 In i ¼ IB =2 i ¼ j ð13Þ > :I i 4j B Comparing this equation with Eq. (8) we can conclude that INLn j ¼ INLp N=2j
ð14Þ
By using this equation the INLn j can be computed from Eq. (12). In conclusion by substituting this equation and Eq. (12) in Eq. (7) we have the INL of the whole array: INLj ¼
j 8j2 6jN þN 2 U URIB 4N 1 þ4r out =ðNURÞ
j ¼ 1,:::,N=21
ð15Þ
2 In this work the INL is defined as the deviation from the endpoint-fit line (see Ref. [2]).
436
D. De Caro et al. / Microelectronics Journal 43 (2012) 433–438
An important design parameter is the maximum INL (INLmax). In order to compute INLmax we can simply derive Eq. (15) and impose the derivative equal to zero. By proceeding in this way two solutions are obtained: pffiffiffi! N 3 17 jmax ¼ ð16Þ 4 3
It is interesting to observe that, according to Eq. (19) the propagation delay of the four sub-arrays is proportional to N2 R. The first arrays are biased with a current given by Iref/k, therefore the delay of the first arrays is proportional to k N R. We can therefore conclude that the delay of the first arrays is negligible if k5 N
ð20Þ
The maximum INL obtained with these two solutions is INLmax ¼
N2 RIB 1 pffiffiffi U rout 48 3 1 þ4 NR
ð17Þ
Both in Eq. (15) and in Eq. (17), the effect of rout is negligible when rout 5N R. From a design point of view this hypothesis is generally verified since the buffers have to be much faster than the whole array. It is also interesting to observe that, at the first order, the buffer non-linearity can be modeled as an output resistance dependent on the output current, that is, rout depends on j in Eq. (15). This suggests that, in the hypothesis rout 5N R, also the buffer non-linearities are negligible. From the expression (17) it is interesting to observe that the INLmax is proportional to N2 if rout 5N R. In this hypothesis, the proposed ladder results in more than one order of magnitude lower INLmax with respect to conventional single-ended ladder (INLmax ¼1/8N2IBR), see Ref. [1]. The resistance rout depends on the buffer biasing current Ibuff: rout EVT/Ibuff. The relationship rout 5N R therefore becomes Ibuf f b
VT NR
ð18Þ
A very good choice can be Ibuff ¼ Iref. This choice, in fact, respects Eq. (18) since Vref bVT (see Eq. (2)). In addition by choosing Ibuff ¼Iref, it is possible to completely simplify the biasing current generator of the two buffers Ba p and Ba n in Fig. 3. These buffers, in fact, become biased directly by the biasing currents of the second arrays. 3.2. Propagation delay (tp) The main advantage of the proposed circuit against the conventional topology is the speed. In fact, the most relevant contribution to the signal propagation delay in the topology of Fig. 3 is due to the four sub-arrays. In this case, the slowest signals are the four midpoints of each sub-array. Therefore, neglecting the delays of the first arrays and of the buffers, we can write tp
ðN=4Þ2 RC 2
ð19Þ
Eq. (19) corresponds to a sixteen fold reduction of the propagation delay, with respect to Eq. (3).
4. Resistor ladders performances The proposed resistor ladder has been designed for a BiCMOS 0.25 mm technology by using 50 GHz NPN HBT devices. For comparison also the conventional differential ladder and the high-speed ladder proposed in Refs. [9,10] have been designed in the same technology. In the following sections we will consider two N values: 64 and 256. For each N value all ladders have been designed and simulated by considering two R values: 1 O and 2.5 O. All arrays have been loaded with the topology of Fig. 2b, which, as observed before, represents both the most critical and the most common case. The proposed ladders with N ¼ 64 use k¼2, while k is equal to 4 for ladders with N ¼256. We have verified that this choice has a minimal impact both on delay and INL. In addition in all circuits Ibuff ¼Iref. Fig. 5a compares the simulated INL of the different ladders with N ¼256 and R¼1 O. It is interesting to observe that the highspeed ladder [9,10] shows a higher non-linearity with respect to conventional ladder both for N ¼64 and N ¼256. The lowest INL is obtained by using the proposed ladder. Fig. 5b compares the simulated and analytical INL (Eq. (15)) for the ladder with N ¼ 256 and R¼1 O. This figure highlights the very good agreement between analytical model and simulation, by giving a confirmation both of considered assumptions and proposed design strategy. The INLmax obtained in all considered ladders is reported in Table 1. The proposed ladder results in all cases in the lowest INLmax. The comparison between analytical and simulated INL confirms again the very good accuracy of the analytical INL model described in Section 3.1. Fig. 6 compares a transient simulation of the proposed ladder with the simulations of the conventional and high-speed ladder of Refs. [9,10], for N¼256. This simulation considers a full swing switch of the ladder input voltage. In these conditions the proposed ladder is clearly faster with respect to the other circuits, with a propagation delay as low as 0.6 ns. It is worth to highlight that the propagation delay may vary considerably as a function of considered ladder output or input voltage switch. A real measure of the ladder speed can only be obtained by inserting the ladder in the ADC and by measuring the total harmonic distortion (THD) of the
Fig. 5. Simulated ladders INL for N ¼ 256 and R¼ 1 O: (a) comparison among simulated ladders; (b) comparison between simulated and analytical INL of proposed ladder.
D. De Caro et al. / Microelectronics Journal 43 (2012) 433–438
converter as a function of sampling rate. This analysis is presented in the next section.
5. A/D Converters Performances In order to have a real indication of the performances of the proposed ladder we designed several ADCs using both Flash and Folding/Interpolating topologies. In the case of Flash converters, we considered two circuits: a 6 bit converter (N ¼64) and an 8 bit converter (N ¼256). Each circuit has been designed by using the three different ladder topologies (conventional, high-speed [9,10] and proposed) and two different R values for each topology (1 O, 2.5 O). All circuits employ the comparator described in Ref. [6] (based on the input stage of Fig. 2b) and an ideal track and hold amplifier. Fig. 7 shows the effective number of bits extracted from the THD and the signal to noise and distortion ratio (SNDR) obtained by simulating the 8 bit Flash converter using the proposed ladder. In graph of Fig. 7, the converter sampling frequency (fsample) is varied between 50 MHz and 1 GHz. The input frequency of the converter has been chosen according to Nyquist criterion (fsample/2). Since an ideal Track-and-Hold is inserted at the input of the converter, this condition corresponds to evaluate the worst-case performances for each considered fsample. At low sampling frequencies the converter exhibits a THD of 9 bit, limited by the ladder INL. The resulting SNDR (which includes also quantization noise) is slightly lower than 8 bit. By increasing the sampling frequency, due to limited ladder speed, a dynamic non-linear
437
behavior is introduced, which worsens the THD. For fsample ffi 600 MHz, the SNDR drops by 3 dB compared to its low frequency value. From the Shannon theorem we can conclude that the effective resolution bandwidth (ERB) of this converter is 600/2¼300 MHz. Table 2 reports the ERB obtained by simulating Flash ADCs designed by using the proposed, the conventional and the high speed [9,10] ladder topologies. This table includes also Power Dissipation data and Figure of Merit performance, computed according to Ref. [17] (FOM ¼PD/(2ERB 2ENOB)). By considering the 8 bit converters, we note that the fastest solution is obtained by using the proposed ladder with R¼1 O. This solution results in an ERB which is 4.6 times and 2.4 times higher than the ERB of converters employing conventional and high-speed [9,10] ladder topologies, respectively. It is also interesting to note that the proposed ladder with R ¼2.5 O dissipates about the same power of the conventional ladder with R ¼1 O, while providing a 3.2 times higher ERB. By looking to the FOM performances, we note that, if we consider the ladder only, the proposed ladder with R¼2.5 O, results in the better FOM. If, on the other hand, we consider the whole Flash converter, the solution with the best FOM is the one employing the proposed ladder with R¼1 O. From the power dissipation data reported in Table 2, in fact, we note that the power dissipation of the converters is dominated by the comparators. As a consequence the ladder sizing has a little impact of the converter power dissipation and a strong impact on the converter ERB. As a consequence the best sizing strategy at the level of the whole converter is having a high-speed and power hungry ladder. The analysis of 6 bit ladders and converters reported in Table 2, highlights a picture similar to the previous 8 bit case.
Table 1 INLmax of considered Resistor Ladders.
Fig. 7. Simulated effective number of bits (ENOB) extracted from the THD and the SNDR for the 8-bit Flash converter using proposed ladder with R¼ 1 O.
Fig. 6. Transient simulation of the three ladders (N ¼ 256, R¼ 1 O).
438
D. De Caro et al. / Microelectronics Journal 43 (2012) 433–438
Table 2 Effective Resolution Bandwidth (ERB) Power Dissipation (PD) and Figure of Merit (FOM) of Simulated Ladders and Flash Converters.
Table 3 Effective resolution bandwidth (ERB) power dissipation (PD) and figure of merit (FOM) of simulated folding and interpolating converters.
Table 3 reports the simulated performances of Folding and Interpolating converters employing the topology described in Refs. [9–11]. Two converters have been considered with a resolution of 8 bit and 9 bit, respectively. The 8 bit converter uses a ladder with N ¼42, while the 9 bit converter employs a ladder with N ¼82. The analysis of the data reported in Table 3 confirms that proposed ladder topology is useful also in improving both ERB and FOM of Folding and Interpolating converters. As an example the 9 bit Folding and Interpolating converter employing the proposed ladder results in an ERB which is about 1.8 times higher than the EBR of the same converter employing the conventional ladder.
6. Conclusions In this paper we have presented a novel differential ladder topology. As we have shown, the main advantage of proposed solution is decreasing the settling time of the ladder. When employed in Flash or in Folding and Interpolating converters this characteristic allows a substantial increase of the sampling frequency with respect to other ladder circuits.
References [1] B. Razavi, Principles of Data Conversion System Design, IEEE Press, 1995. [2] F. Maloberti, Data Converters, Springer, 2007. [3] A. Ismail, M. Elmasry, A 6-bit 1.6-GS/s low-power wideband flash ADC converter in 0.13-mm CMOS technology, IEEE J. Solid-State Circuits 43 (9) (2008) 1982–1990. [4] H. Yu, M.C.F. Chang, A 1-V 1.25-GS/S 8-bit self-calibrated flash ADC in 90-nm digital CMOS, IEEE Trans. Circuits Syst.-II: Express Briefs 55 (7) (2008) 668–672. [5] M.P. Flynn, B. Sheahan, A 400-Msample/s, 6-b CMOS folding and interpolating ADC, IEEE J. Solid-State Circuits 33 (12) (1998) 1932–1938. [6] F. Vessal, C.A.T. Salama, An 8-bit 2-Gsample/s folding-interpolating analogto-digital converter in SiGe technology, IEEE J. Solid-State Circuits 39 (1) (2004) 238–241. [7] A.G.W. Venes, R.J. van de Plassche, An 80-MHz, 80-mW, 8-b CMOS folding A/D converter with distributed track-and-hold preprocessing, IEEE J. SolidState Circuits 31 (12) (1996) 1846–1853. [8] H. Pan, A.A. Abidi, Signal Folding in A/D Converters, IEEE Trans. Circuits Syst. I: Regular Pap. 51 (2004) 3–14. [9] H. Kobayashi, et al., Design consideration for folding/interpolation ADC with SiGe HBT, Proc Instrum. Meas, Tech. Conf. 2 (1997) 1142–1147. IMTC/97. [10] H. Kobayashi, et al., A high speed 6 bit ADC using SiGe HBT, IEICE Trans. Fundam. 3 (1998) 389–397. E81-A. [11] H. Kobayashi, et al., AC performance improvement of folding/interpolation ADC with SiGe HBT, Proc Instrum. Meas. Tech. Conf. (1998) 1385–1390. IMTC/98. [12] P. Vorenkamp, R. Roovers, A 12-b, 60-M sample/s cascaded folding and interpolating ADC, IEEE J. Solid-State Circuits 32 (12) (1997) 1876–1886. [13] J. Lee, et al., A 5-b 10 G sample/s A/D converter for 10 Gb/s optical receivers, IEEE J. Solid-State Circuits 39 (10) (2004) 1671–1679. [14] B. Chan, et al., An ultra-wideband 7-bit 5-Gsps ADC implemented in submicron InP HBT technology, IEEE J. Solid-State Circuits 43 (10) (2008) 2187–2193. [15] W. Colleran, A 10bit 100 MS/s A/D Converter using Folding, Interpolation, and Analog Encoding, Ph.D. Dissertation, UCLA, Dec. 1993. [16] D. De Caro, M. Coppola, N. Petra, E. Napoli, A.G.M. Strollo, V. Garofalo, High speed differential resistor ladder for A/D converters, Proc. IEEE Int. Symp. Circuits Systems (ISCAS) (2010) 1723–1726. [17] R.H. Walden, Analog-to-digital converter survey and analysis, IEEE J. Sel. Areas Commun. 17 (4) (1999).