- Email: [email protected]
A high speed, low power consumption LVDS interface for CMOS pixel sensors
Nuclear Instruments and Methods in Physics Research A 769 (2015) 52–58
Contents lists available at ScienceDirect
Nuclear Instruments and Methods in Physics Research A journal homepage: www.elsevier.com/locate/nima
A high speed, low power consumption LVDS interface for CMOS pixel sensors Zhan Shi a, Zhenan Tang a, Yong Tian a,n, Hung Pham b,c, Isabelle Valin b,c, Kimmo Jaaskelainen b,c a
Dalian University of Technology, No. 2 Linggong Road, 116024 Dalian, PR China IPHC, 23 rue du Loess 67037 Strasbourg, France c CNRS, UMR7178, 67037 Strasbourg, France b
art ic l e i nf o
a b s t r a c t
Article history: Received 8 April 2014 Received in revised form 3 September 2014 Accepted 15 September 2014 Available online 22 September 2014
The use of CMOS Pixel Sensors (CPSs) offers a promising approach to the design of vertex detectors in High Energy Physics (HEP) experiments. As the CPS equipping the upgraded Solenoidal Tracker at RHIC (STAR) pixel detector, ULTIMATE perfectly illustrates the potential of CPSs for HEP applications. However, further development of CPSs with respect to readout speed is required to fulfill the readout time requirement of the next generation HEP detectors, such as the upgrade of A Large Ion Collider Experiment (ALICE) Inner Tracking System (ITS), the International Linear Collider (ILC), and the Compressed Baryonic Matter (CBM) vertex detectors. One actual limitation of CPSs is related to the speed of the Low-Voltage Differential Signaling (LVDS) circuitry implementing the interface between the sensor and the Data Acquisition (DAQ) system. To improve the transmission rate while keeping the power consumption at a low level, a source termination technique and a special current comparator were adopted for the LVDS driver and receiver, respectively. Moreover, hardening techniques are used. The circuitry was designed and submitted for fabrication in a 0.18-mm CMOS Image Sensor (CIS) process at the end of 2011. The test results indicated that the LVDS driver and receiver can operate properly at the data rate of 1.2 Gb/s with power consumption of 19.6 mW. & 2014 Elsevier B.V. All rights reserved.
Keywords: CPS Particle tracking Data transmission LVDS Low power
1. Introduction As depicted in Fig. 1, a CPS exploits p–n diodes formed by the N-well/P-epitaxial layer using CMOS technologies as a sensing element for the tracking of charged particles [1,2]. By leveraging the progress of commercial CMOS technologies and the availability of high resistivity substrates, the use of CPSs has become an attractive solution for equipping future vertex detectors. Compared with other pixel technologies, CPS technology offers many advantages, such as low cost, low power, high granularity, and low material budget [2]. The feasibility of using CPS technology for charged particle tracking has been demonstrated by the development of a EUDET beam telescope [3] and the construction of the pixel detector of the STAR experiment at RHIC [4,5]. However, the forthcoming high energy physic experiments, such as the upgrade of ALICE ITS (shown in Fig. 2) or the CBM Micro Vertex Detector (MVD), require both a higher readout speed, and radiation tolerance [6,7]. Those requirements motivate the development of a new
n
Corresponding author. E-mail addresses: [email protected] (Z. Shi), [email protected] (Z. Tang).
http://dx.doi.org/10.1016/j.nima.2014.09.043 0168-9002/& 2014 Elsevier B.V. All rights reserved.
generation of high speed CPSs based on 0.18-mm 1.8-V CIS technology. In such technology, a high speed transmission circuitry using low power supply technology is necessary to guaranty the high data rate of this sensor. For transmission rates from tens of Mb/s up to 2 Gb/s, LVDS is an attractive transmission technique. LVDS offers a low power and differential signaling system that consists of a LVDS driver and a receiver, as shown in Fig. 3. The driver injects into the transmission line a small current, typically 3.5 mA, the direction of which depends on the logic level to be sent. The receiver senses the polarity of the input voltage (through a 100 Ω resistor) to determine the logic level of the transmitted signal. Due to its differential signaling and small output swing, LVDS can achieve high transmission rates with low power consumption. Its maximum transmission rate is therefore higher than that of CMOS. Furthermore, compared with other differential transmission technologies, such as Current-Mode Logic (CML) and Low-Voltage Positive-Emitter-Coupled Logic (LVPECL), LVDS is more powerefficient. This work focuses on the development of a compact, high speed, low power and radiation tolerant LVDS circuit for a CPS based on 0.18-mm CIS technology. The paper is organized as
Z. Shi et al. / Nuclear Instruments and Methods in Physics Research A 769 (2015) 52–58
follows. The design of the LVDS driver is presented in Section 2, followed by the design of the LVDS receiver in Section 3. Section 4 is dedicated to the layout and measurement of the circuit. Finally, the work is concluded in Section 5.
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voltage is positive. On the contrary, if the input is negative, then the polarity of the output current and voltage is reversed. The CMFB circuit allows for the stabilization of the driver’s output common mode voltage at the reference voltage (Vref) to keep the output signal of the driver within the input common mode range of the
2. LVDS driver design A typical LVDS driver behaves as a current source with switched polarity. As shown in Fig. 4, the driver is composed of a control block, a driver core block, and a Common Mode Feedback (CMFB) block. The control block converts the CMOS single-ended input signal to a differential signal and generates control signals for the driver. The driver core block delivers the output current, the polarity of which corresponds to the output differential signal of the control bock. A schematic of a typical driver core is shown in Fig. 5(a). This circuit is composed of four MOS switches (M2–M5) arranged in a bridged configuration. If the input is positive, switches M2 and M5 are turned on and switches M3 and M4 are turned off, forming a current path from the power supply to ground. Thus, current flows from the positive output node (Voutp) to the negative output node (Voutn) and the differential output
Fig. 3. (a) The LVDS transmission scheme, and (b) an example of the LVDS signal.
Fig. 1. Operation principle of a CPS.
Fig. 4. LVDS driver block diagram.
Fig. 2. Cutout 3D view (left) and front view (right) of the ALICE ITS inner barrel.
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Z. Shi et al. / Nuclear Instruments and Methods in Physics Research A 769 (2015) 52–58
Fig. 6. Driver’s output mode with both source and end terminators.
Fig. 5. (a) A typical architecture of driver core, (b) driver core integrated with termination resistors in series with output PADs.
receiver. This voltage is generated from a bandgap reference to be less sensitive to Process–Voltage–Temperature (PVT) variations. Several techniques for the implementation of a high-speed LVDS driver at a low power supply voltage have been presented in Refs. [8–10]. In the open-drain configuration [8], the two MOS switches (M4 and M5 in Fig. 5(a)) are replaced by two 50-Ω resistors to obtain a higher voltage drop over the transistor M6. This approach alleviates the difficulty of maintaining this transistor in its saturation region. Meanwhile, this configuration offers a better impedance matching at the driver’s output. Hence, this design can achieve a high speed at the cost of a fourfold increase in the power consumption. In Ref. [9], Chen et al. proposed to use a double current source circuit in place of the basic driver core circuit. This technique improves the maximum speed of the driver while increasing its power consumption by two times. Alternatively, source termination in parallel with the driver [10] can also increase its data rate. However, the bias current of the driver core stage must be doubled to ensure the voltage swing of the output LVDS signal. As a result, all of those techniques are not suitable for the LVDS driver in CPSs due to their high power consumption. To increase the maximum speed and maintain low power consumption, the serial source termination technique is used in this work. By providing impedance matching between the source and the transmission line, serial source termination can improve the output signal fidelity and thus achieve a higher transmission rate. Fig. 3(a) represents a conventional LVDS transmission scheme in which only end termination is deployed. The far-end reflection function Rz ðωÞ, which is the fraction of the propagating signal that reflects back toward the source, can be written as: Rz ðωÞ ¼
Z L ðωÞ Z O ðωÞ ; Z L ðωÞ þ Z O ðωÞ
ð1Þ
where Z L ðωÞ is the load impedance and Z O ðωÞ is the characteristic impedance of a transmission line [11]. When Z L ðωÞ ¼ Z O ðωÞ, the reflection coefficient Rz ðωÞ becomes zero. Unfortunately, Z L ðωÞ cannot match exactly because of the variations of the terminating resistance and the transmission line impedance. To further reduce the reflected signal, source termination can be introduced as shown in Fig. 6. The source end reflection coefficient R1 ðωÞ is given by: R1 ðωÞ ¼
Z S ðωÞ Z O ðωÞ ; Z S ðωÞ þ Z O ðωÞ
ð2Þ
where Z S ðωÞ is the source impedance and is the characteristic impedance of a transmission line [11]. The reflected signal is significantly attenuated when Z S ðωÞ is equal to Z O ðωÞ. As illustrated
Fig. 7. (a) The control bock, (b) the driver core with sensing resistors for CMFB, (c) the CMFB circuit.
in Fig. 5(b), two 50-Ω resistors were added at the driver’s output to achieve the source impedance matching. In addition, four switch transistors, M2, M3, M4, and M5 were carefully designed so that their impedances will be negligible relative to the output impedance of the driver. Different from other techniques, serial source termination will not increase the power consumption of the driver because all of the currents of the core stage are fed into the termination resistors at the receiver end. The schematic of each LVDS driver block is shown in detail in Fig. 7. In Fig. 7(a), as mentioned above, the control block is composed of a single-to-differential-ended converter and a control signal generator. The latter allows for disabling the circuit to save power when necessary. Fig. 7(c) shows the detail of the CMFB circuit, including a differential amplifier (M11–M15) and a current mirror (M16–M18). The differential amplifier senses the common mode voltage VCM of the driver core output and compares it with the reference voltage VCM_REF. The difference between those two voltages is amplified and fed back to the driver core stage (through
Z. Shi et al. / Nuclear Instruments and Methods in Physics Research A 769 (2015) 52–58
the nodes Vp and Vm) to adjust the current of the core stage, maintaining VCM as close as possible to VCM_REF. Five additional switches are also implemented to power off the circuit.
3. LVDS receiver design The LVDS receiver converts the LVDS levels into CMOS levels. Fig. 8 represents a typical LVDS receiver implementation. The differential input voltage is detected by a Schmitt trigger (M1–M6) with a predefined hysteresis value to ensure the noise immunity of the circuit before being converted to single-ended CMOS levels at the output. However, this circuit can operate correctly only if the input common mode voltage is maintained within the limited range of 0 to 1.25 V. To extend the input common mode voltage range of the receiver, a rail-to-rail preamplifier was developed, as illustrated in Fig. 9. The PMOS input pair (MP1 and MP2) is turned on when the input common-mode voltage is low, while the NMOS input pair (MN1 and MN2) is turned on when the input common-mode voltage is high. As a result, a rail-to-rail input common-mode voltage range can be achieved. After being amplified by the input pairs, the differential input signal is converted to a single-ended
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signal through a cascode [12] current mirror (MP5–MP8). The NMOS pair (MN3 and MN4) forms a positive feedback loop to define the hysteresis voltage. Four switches are used to switch off the power supply in power down mode. Those switches are shown as ideal devices, and the bias network is replaced by several voltage sources to simply the amplifier schematic. Despite extending the input common mode voltage range, the preamplifier is not optimized as a high speed receiver because its propagation delay is relatively long. When a positive input is applied to the preamplifier, the cascode transistor MN8 (Fig. 9) falls out of the saturation region and the node outA is charged to the power supply voltage, with the current delivered by MP8. Subsequently, when the input of the preamplifier is negative, MN8 is recovered back to the saturation region, and then, the node outA is discharged to ground with the current delivered by MN8. However, as long as the cascode transistor MN8 still operates in the linear region, the discharging current of the node outA is restricted severely. The propagation time of the signal is therefore significantly delayed. As depicted in Fig. 10, to reduce the propagation delay, a current comparator [13] is inserted between the preamplifier stage and the output buffer stage (composed of CMOS inverters to increase the driving capability). The current comparator consists of a basic inverter (MC1 and MC2) and two source followers (MC3 and MC4). The source followers provide a feedback path to the input node (outA). If the input voltage of the current comparator VoutA is around the balance point ( VDD/2), then the following relationship is ensured V outA jV th;MC3 j o V out1 o V outA þ V th;MC4 ;
Fig. 8. Schematic diagram of a typical receiver.
Fig. 9. A rail-to-rail preamplifier for the LVDS receiver.
Fig. 10. A current comparator.
ð3Þ
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Z. Shi et al. / Nuclear Instruments and Methods in Physics Research A 769 (2015) 52–58
where V th;MC3 and V th;MC4 are thresholds of MC3 and MC4, respectively. The current comparator acts as a normal inverter because both of the two source follower transistors are turned off. However, if the variation of VoutA from its balance point is large enough to force V out1 rV outA jV th;MC3 j or V out1 Z V outA þ V th;MC4 , either MC3 or MC4 will be turned on. Current is thus fed back to the preamplifier’s output (outA) to balance that current being delivered. Consequently, the action of MC3 and MC4 is to provide an automatic clamp for the output of the preamplifier, thereby maintaining the cascode current mirror transistors in their normal saturation conditions; as a result, there is no significant recovery delay present for the propagation. In addition to improving the driving capability, the output buffer stage also provides two inverted signals (out1 and out2) to control the NMOS pair (MN3 and MN4) for hysteresis generation.
4. Layout and measurement The proposed LVDS driver and receiver circuits were integrated as two separated modules in the MIMOSA32 prototype submitted in November, 2011, as shown in Fig. 11. To minimize the peripheral area of the CPS, the driver and the receiver are fully integrated into IO cells with Electro-static-discharge (ESD) protection circuits and bonding pads. As a result, the cell size of the driver is the same as that of the receiver and is equal to 0.145 mm 0.25 mm. In addition, the enclosed layout technique and the P þ guard rings are adopted to be tolerant of the Total Ionizing Dose (TID) levels of over 1 mrad. Two test schemes were designed for the purpose of calibration of the driver and the receiver, as shown in Fig. 12. By closing S1 and S3 and opening S2, the driver and the receiver are tested separately at low data rates. To test the driver and the receiver at the full data rate, the output of the receiver is connected directly to the input of the driver through S2 while S1 and S3 are opened. The test bench is shown in Fig. 13. During the high speed test, the input of the chip can be connected to the clock signal or the data signal. The clock signal is generated by a clock generator (CDCE62005), while the Pseudo Random Binary Sequence-7 (PRBS-7) is used as the data pattern. The output signal of the chip is transmitted to a 100-Ω termination resistor along 8.9-cm
Fig. 11. Picture of a MIMOSA 32 chip.
Fig. 13. Test bench of the LVDS circuits.
Printed Circuit Board (PCB) traces and 25-cm low loss cables, plus additional 30-cm PCB traces. Additional 30-cm PCB traces are used to further approach the driving length in real application. Note that the maximum transmission length on PCB traces for the LVDS signal in the upgrade of ALICE ITS is approximately 27 cm [6]. In addition, a LECROY SDA 760Zi oscilloscope with a 6-GHz differential probe is used to probe the resulting eye diagrams and jitters of the chip output signals, as measured differentially across the termination resistor. The test results indicate that the LVDS driver and receiver can operate properly with a clock input of up to 1.2 Gb/s. Fig. 14(a) and (b) shows the differential output eye diagrams with a clock input of 1.2 Gb/s and 1.0 Gb/s, respectively. The eye amplitudes of the single-ended outputs at 1.2 Gb/s and 1.0 Gb/s are 262 mV and 279 mV, respectively, while the total jitters at 1.2 Gb/s and 1.0 Gb/s are 130 ps and 76 ps, respectively. The corresponding eye openings at 1.2 Gb/s and 1.0 Gb/s are 89% and 87%, respectively. In addition, Fig. 15 shows the eye diagram of the resulting differential output signals with PRBS-7 input at 820 Mb/s. The differential output signal is measured with an eye amplitude of 604 mV, a total jitter of 281 ps, and an eye opening of 65%. The measurements presented above reveal the overall performance of the LVDS circuitry. For a particular vertex detector, a more realistic test closer to the experimental condition must be performed in the future. For the application in which the transmission distance of the LVDS output signals is longer than 38.9 cm of the PCB traces, Constant Time Linear Equalization (CTLE) in the receiver can be applied to extend the driving length without increasing the power dissipation of the sensors. In addition, for the beam test, the Xilinx Virtex Series FPGAs are recommended to receive the signals from the presented LVDS driver because the data rate of its differential I/O pairs can achieve up to 1.4 Gb/s for LVDS signals [14] and it is highly compatible with the entire DAQ system design [15].
5. Conclusion
Fig. 12. LVDS test scheme.
A high speed, low power consumption LVDS interface for CPSs implemented in 0.18 mm CMOS technology was presented. A source termination technique and a special current comparator were used to increase the maximum speed and maintain low power consumption at the same time. The driver and the receiver were fully integrated into IO cells. In addition, a power down mode was designed to further reduce the power consumption. Enclosed layout transistors were used to improve the radiation tolerance. The test results demonstrated that the LVDS driver and receiver can drive the load of 38.9-cm PCB traces at data rates if up to 1.2 Gb/s for the clock input and 820 Mb/s for the PRBS-7 input, which fulfills the elementary data transmission rate requirement
Z. Shi et al. / Nuclear Instruments and Methods in Physics Research A 769 (2015) 52–58
Fig. 14. Eye diagram of the differential output signals with a clock input of 1.2 Gb/s.
Fig. 15. Eye diagram of the differential output signals with PRBS-7 input at 820 Mb/s.
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Z. Shi et al. / Nuclear Instruments and Methods in Physics Research A 769 (2015) 52–58
Table 1 Performance summary of the LVDS driver and receiver with 1.2 Gb/s clock input. Total jitter Output amplitude Current Power consumption Cell size
130 ps 262 mV 10.9 mA 19.6 mW 0.036 mm2
of the upgraded ITS of the ALICE. Table 1 provides a performance summary of the LVDS driver and receiver with a clock input at the rate of 1.2 Gb/s.
Acknowledgments The authors thank The Duc Le for the design of the test PCB and suggestions regarding the test scheme. In particular, the support of Gilles Claus, and Mathieu Goffe during the testing is acknowledged. The authors are indebted to Christine Hu-Guo for fruitful discussions and for a review of the paper. The authors also acknowledge the support of the China Scholarship Council (Grant no. 2010606079).
References [1] Y. Degerli, et al., A digital monolithic active pixel sensor chip in a QuadrupleWell CIS process, in: Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC), 2012 IEEE, pp. 2030–2035. [2] R. Turchetta, et al., Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 458 (2001) 677. [3] C. Hu-Guo, et al., Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 623 (2010) 480. [4] L. Greiner, et al., Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 650 (2011) 68. [5] I. Valin, et al., Journal of Instrumentation 7 (2012) C01102. [6] A. Collaboration, Conceptual Design Report for the upgrade of the ALICE ITS, preparation. [7] C. Schrader, et al., Status of the CBM-MVD Prototype Readout, GSI Report, (2011). [8] S. Jamasb, et al., A 622 MHz stand-alone LVDS driver pad in 0.18-μm CMOS, circuits and systems, 2001. MWSCAS 2001, in: Proceedings of the 44th IEEE 2001 Midwest Symposium on, IEEE, 2001, pp. 610–613. [9] M. Chen, et al., IEEE Journal of Solid-State Circuits 40 (2005) 472. [10] A. Boni, et al., IEEE Journal of Solid-State Circuits 36 (2001) 706. [11] H.W. Johnson, M. Graham, High-speed Digital Design: A Handbook of Black Magic, Prentice Hall, Englewood Cliffs, NJ, 1993. [12] B. Razavi, Design of Analog CMOS Integrated Circuits, Tata McGraw-Hill Education, 2002. [13] H. Traff, Electronics Letters 28 (1992) 310. [14] Xilinx, Virtex-6 FPGA Data Sheet: DC and Switching Characteristics, 2014. [15] J. Schambach, et al., IEEE Transactions on Nuclear Science NS60 (2013) 3689.
Contents lists available at ScienceDirect
Nuclear Instruments and Methods in Physics Research A journal homepage: www.elsevier.com/locate/nima
A high speed, low power consumption LVDS interface for CMOS pixel sensors Zhan Shi a, Zhenan Tang a, Yong Tian a,n, Hung Pham b,c, Isabelle Valin b,c, Kimmo Jaaskelainen b,c a
Dalian University of Technology, No. 2 Linggong Road, 116024 Dalian, PR China IPHC, 23 rue du Loess 67037 Strasbourg, France c CNRS, UMR7178, 67037 Strasbourg, France b
art ic l e i nf o
a b s t r a c t
Article history: Received 8 April 2014 Received in revised form 3 September 2014 Accepted 15 September 2014 Available online 22 September 2014
The use of CMOS Pixel Sensors (CPSs) offers a promising approach to the design of vertex detectors in High Energy Physics (HEP) experiments. As the CPS equipping the upgraded Solenoidal Tracker at RHIC (STAR) pixel detector, ULTIMATE perfectly illustrates the potential of CPSs for HEP applications. However, further development of CPSs with respect to readout speed is required to fulfill the readout time requirement of the next generation HEP detectors, such as the upgrade of A Large Ion Collider Experiment (ALICE) Inner Tracking System (ITS), the International Linear Collider (ILC), and the Compressed Baryonic Matter (CBM) vertex detectors. One actual limitation of CPSs is related to the speed of the Low-Voltage Differential Signaling (LVDS) circuitry implementing the interface between the sensor and the Data Acquisition (DAQ) system. To improve the transmission rate while keeping the power consumption at a low level, a source termination technique and a special current comparator were adopted for the LVDS driver and receiver, respectively. Moreover, hardening techniques are used. The circuitry was designed and submitted for fabrication in a 0.18-mm CMOS Image Sensor (CIS) process at the end of 2011. The test results indicated that the LVDS driver and receiver can operate properly at the data rate of 1.2 Gb/s with power consumption of 19.6 mW. & 2014 Elsevier B.V. All rights reserved.
Keywords: CPS Particle tracking Data transmission LVDS Low power
1. Introduction As depicted in Fig. 1, a CPS exploits p–n diodes formed by the N-well/P-epitaxial layer using CMOS technologies as a sensing element for the tracking of charged particles [1,2]. By leveraging the progress of commercial CMOS technologies and the availability of high resistivity substrates, the use of CPSs has become an attractive solution for equipping future vertex detectors. Compared with other pixel technologies, CPS technology offers many advantages, such as low cost, low power, high granularity, and low material budget [2]. The feasibility of using CPS technology for charged particle tracking has been demonstrated by the development of a EUDET beam telescope [3] and the construction of the pixel detector of the STAR experiment at RHIC [4,5]. However, the forthcoming high energy physic experiments, such as the upgrade of ALICE ITS (shown in Fig. 2) or the CBM Micro Vertex Detector (MVD), require both a higher readout speed, and radiation tolerance [6,7]. Those requirements motivate the development of a new
n
Corresponding author. E-mail addresses: [email protected] (Z. Shi), [email protected] (Z. Tang).
http://dx.doi.org/10.1016/j.nima.2014.09.043 0168-9002/& 2014 Elsevier B.V. All rights reserved.
generation of high speed CPSs based on 0.18-mm 1.8-V CIS technology. In such technology, a high speed transmission circuitry using low power supply technology is necessary to guaranty the high data rate of this sensor. For transmission rates from tens of Mb/s up to 2 Gb/s, LVDS is an attractive transmission technique. LVDS offers a low power and differential signaling system that consists of a LVDS driver and a receiver, as shown in Fig. 3. The driver injects into the transmission line a small current, typically 3.5 mA, the direction of which depends on the logic level to be sent. The receiver senses the polarity of the input voltage (through a 100 Ω resistor) to determine the logic level of the transmitted signal. Due to its differential signaling and small output swing, LVDS can achieve high transmission rates with low power consumption. Its maximum transmission rate is therefore higher than that of CMOS. Furthermore, compared with other differential transmission technologies, such as Current-Mode Logic (CML) and Low-Voltage Positive-Emitter-Coupled Logic (LVPECL), LVDS is more powerefficient. This work focuses on the development of a compact, high speed, low power and radiation tolerant LVDS circuit for a CPS based on 0.18-mm CIS technology. The paper is organized as
Z. Shi et al. / Nuclear Instruments and Methods in Physics Research A 769 (2015) 52–58
follows. The design of the LVDS driver is presented in Section 2, followed by the design of the LVDS receiver in Section 3. Section 4 is dedicated to the layout and measurement of the circuit. Finally, the work is concluded in Section 5.
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voltage is positive. On the contrary, if the input is negative, then the polarity of the output current and voltage is reversed. The CMFB circuit allows for the stabilization of the driver’s output common mode voltage at the reference voltage (Vref) to keep the output signal of the driver within the input common mode range of the
2. LVDS driver design A typical LVDS driver behaves as a current source with switched polarity. As shown in Fig. 4, the driver is composed of a control block, a driver core block, and a Common Mode Feedback (CMFB) block. The control block converts the CMOS single-ended input signal to a differential signal and generates control signals for the driver. The driver core block delivers the output current, the polarity of which corresponds to the output differential signal of the control bock. A schematic of a typical driver core is shown in Fig. 5(a). This circuit is composed of four MOS switches (M2–M5) arranged in a bridged configuration. If the input is positive, switches M2 and M5 are turned on and switches M3 and M4 are turned off, forming a current path from the power supply to ground. Thus, current flows from the positive output node (Voutp) to the negative output node (Voutn) and the differential output
Fig. 3. (a) The LVDS transmission scheme, and (b) an example of the LVDS signal.
Fig. 1. Operation principle of a CPS.
Fig. 4. LVDS driver block diagram.
Fig. 2. Cutout 3D view (left) and front view (right) of the ALICE ITS inner barrel.
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Z. Shi et al. / Nuclear Instruments and Methods in Physics Research A 769 (2015) 52–58
Fig. 6. Driver’s output mode with both source and end terminators.
Fig. 5. (a) A typical architecture of driver core, (b) driver core integrated with termination resistors in series with output PADs.
receiver. This voltage is generated from a bandgap reference to be less sensitive to Process–Voltage–Temperature (PVT) variations. Several techniques for the implementation of a high-speed LVDS driver at a low power supply voltage have been presented in Refs. [8–10]. In the open-drain configuration [8], the two MOS switches (M4 and M5 in Fig. 5(a)) are replaced by two 50-Ω resistors to obtain a higher voltage drop over the transistor M6. This approach alleviates the difficulty of maintaining this transistor in its saturation region. Meanwhile, this configuration offers a better impedance matching at the driver’s output. Hence, this design can achieve a high speed at the cost of a fourfold increase in the power consumption. In Ref. [9], Chen et al. proposed to use a double current source circuit in place of the basic driver core circuit. This technique improves the maximum speed of the driver while increasing its power consumption by two times. Alternatively, source termination in parallel with the driver [10] can also increase its data rate. However, the bias current of the driver core stage must be doubled to ensure the voltage swing of the output LVDS signal. As a result, all of those techniques are not suitable for the LVDS driver in CPSs due to their high power consumption. To increase the maximum speed and maintain low power consumption, the serial source termination technique is used in this work. By providing impedance matching between the source and the transmission line, serial source termination can improve the output signal fidelity and thus achieve a higher transmission rate. Fig. 3(a) represents a conventional LVDS transmission scheme in which only end termination is deployed. The far-end reflection function Rz ðωÞ, which is the fraction of the propagating signal that reflects back toward the source, can be written as: Rz ðωÞ ¼
Z L ðωÞ Z O ðωÞ ; Z L ðωÞ þ Z O ðωÞ
ð1Þ
where Z L ðωÞ is the load impedance and Z O ðωÞ is the characteristic impedance of a transmission line [11]. When Z L ðωÞ ¼ Z O ðωÞ, the reflection coefficient Rz ðωÞ becomes zero. Unfortunately, Z L ðωÞ cannot match exactly because of the variations of the terminating resistance and the transmission line impedance. To further reduce the reflected signal, source termination can be introduced as shown in Fig. 6. The source end reflection coefficient R1 ðωÞ is given by: R1 ðωÞ ¼
Z S ðωÞ Z O ðωÞ ; Z S ðωÞ þ Z O ðωÞ
ð2Þ
where Z S ðωÞ is the source impedance and is the characteristic impedance of a transmission line [11]. The reflected signal is significantly attenuated when Z S ðωÞ is equal to Z O ðωÞ. As illustrated
Fig. 7. (a) The control bock, (b) the driver core with sensing resistors for CMFB, (c) the CMFB circuit.
in Fig. 5(b), two 50-Ω resistors were added at the driver’s output to achieve the source impedance matching. In addition, four switch transistors, M2, M3, M4, and M5 were carefully designed so that their impedances will be negligible relative to the output impedance of the driver. Different from other techniques, serial source termination will not increase the power consumption of the driver because all of the currents of the core stage are fed into the termination resistors at the receiver end. The schematic of each LVDS driver block is shown in detail in Fig. 7. In Fig. 7(a), as mentioned above, the control block is composed of a single-to-differential-ended converter and a control signal generator. The latter allows for disabling the circuit to save power when necessary. Fig. 7(c) shows the detail of the CMFB circuit, including a differential amplifier (M11–M15) and a current mirror (M16–M18). The differential amplifier senses the common mode voltage VCM of the driver core output and compares it with the reference voltage VCM_REF. The difference between those two voltages is amplified and fed back to the driver core stage (through
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the nodes Vp and Vm) to adjust the current of the core stage, maintaining VCM as close as possible to VCM_REF. Five additional switches are also implemented to power off the circuit.
3. LVDS receiver design The LVDS receiver converts the LVDS levels into CMOS levels. Fig. 8 represents a typical LVDS receiver implementation. The differential input voltage is detected by a Schmitt trigger (M1–M6) with a predefined hysteresis value to ensure the noise immunity of the circuit before being converted to single-ended CMOS levels at the output. However, this circuit can operate correctly only if the input common mode voltage is maintained within the limited range of 0 to 1.25 V. To extend the input common mode voltage range of the receiver, a rail-to-rail preamplifier was developed, as illustrated in Fig. 9. The PMOS input pair (MP1 and MP2) is turned on when the input common-mode voltage is low, while the NMOS input pair (MN1 and MN2) is turned on when the input common-mode voltage is high. As a result, a rail-to-rail input common-mode voltage range can be achieved. After being amplified by the input pairs, the differential input signal is converted to a single-ended
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signal through a cascode [12] current mirror (MP5–MP8). The NMOS pair (MN3 and MN4) forms a positive feedback loop to define the hysteresis voltage. Four switches are used to switch off the power supply in power down mode. Those switches are shown as ideal devices, and the bias network is replaced by several voltage sources to simply the amplifier schematic. Despite extending the input common mode voltage range, the preamplifier is not optimized as a high speed receiver because its propagation delay is relatively long. When a positive input is applied to the preamplifier, the cascode transistor MN8 (Fig. 9) falls out of the saturation region and the node outA is charged to the power supply voltage, with the current delivered by MP8. Subsequently, when the input of the preamplifier is negative, MN8 is recovered back to the saturation region, and then, the node outA is discharged to ground with the current delivered by MN8. However, as long as the cascode transistor MN8 still operates in the linear region, the discharging current of the node outA is restricted severely. The propagation time of the signal is therefore significantly delayed. As depicted in Fig. 10, to reduce the propagation delay, a current comparator [13] is inserted between the preamplifier stage and the output buffer stage (composed of CMOS inverters to increase the driving capability). The current comparator consists of a basic inverter (MC1 and MC2) and two source followers (MC3 and MC4). The source followers provide a feedback path to the input node (outA). If the input voltage of the current comparator VoutA is around the balance point ( VDD/2), then the following relationship is ensured V outA jV th;MC3 j o V out1 o V outA þ V th;MC4 ;
Fig. 8. Schematic diagram of a typical receiver.
Fig. 9. A rail-to-rail preamplifier for the LVDS receiver.
Fig. 10. A current comparator.
ð3Þ
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where V th;MC3 and V th;MC4 are thresholds of MC3 and MC4, respectively. The current comparator acts as a normal inverter because both of the two source follower transistors are turned off. However, if the variation of VoutA from its balance point is large enough to force V out1 rV outA jV th;MC3 j or V out1 Z V outA þ V th;MC4 , either MC3 or MC4 will be turned on. Current is thus fed back to the preamplifier’s output (outA) to balance that current being delivered. Consequently, the action of MC3 and MC4 is to provide an automatic clamp for the output of the preamplifier, thereby maintaining the cascode current mirror transistors in their normal saturation conditions; as a result, there is no significant recovery delay present for the propagation. In addition to improving the driving capability, the output buffer stage also provides two inverted signals (out1 and out2) to control the NMOS pair (MN3 and MN4) for hysteresis generation.
4. Layout and measurement The proposed LVDS driver and receiver circuits were integrated as two separated modules in the MIMOSA32 prototype submitted in November, 2011, as shown in Fig. 11. To minimize the peripheral area of the CPS, the driver and the receiver are fully integrated into IO cells with Electro-static-discharge (ESD) protection circuits and bonding pads. As a result, the cell size of the driver is the same as that of the receiver and is equal to 0.145 mm 0.25 mm. In addition, the enclosed layout technique and the P þ guard rings are adopted to be tolerant of the Total Ionizing Dose (TID) levels of over 1 mrad. Two test schemes were designed for the purpose of calibration of the driver and the receiver, as shown in Fig. 12. By closing S1 and S3 and opening S2, the driver and the receiver are tested separately at low data rates. To test the driver and the receiver at the full data rate, the output of the receiver is connected directly to the input of the driver through S2 while S1 and S3 are opened. The test bench is shown in Fig. 13. During the high speed test, the input of the chip can be connected to the clock signal or the data signal. The clock signal is generated by a clock generator (CDCE62005), while the Pseudo Random Binary Sequence-7 (PRBS-7) is used as the data pattern. The output signal of the chip is transmitted to a 100-Ω termination resistor along 8.9-cm
Fig. 11. Picture of a MIMOSA 32 chip.
Fig. 13. Test bench of the LVDS circuits.
Printed Circuit Board (PCB) traces and 25-cm low loss cables, plus additional 30-cm PCB traces. Additional 30-cm PCB traces are used to further approach the driving length in real application. Note that the maximum transmission length on PCB traces for the LVDS signal in the upgrade of ALICE ITS is approximately 27 cm [6]. In addition, a LECROY SDA 760Zi oscilloscope with a 6-GHz differential probe is used to probe the resulting eye diagrams and jitters of the chip output signals, as measured differentially across the termination resistor. The test results indicate that the LVDS driver and receiver can operate properly with a clock input of up to 1.2 Gb/s. Fig. 14(a) and (b) shows the differential output eye diagrams with a clock input of 1.2 Gb/s and 1.0 Gb/s, respectively. The eye amplitudes of the single-ended outputs at 1.2 Gb/s and 1.0 Gb/s are 262 mV and 279 mV, respectively, while the total jitters at 1.2 Gb/s and 1.0 Gb/s are 130 ps and 76 ps, respectively. The corresponding eye openings at 1.2 Gb/s and 1.0 Gb/s are 89% and 87%, respectively. In addition, Fig. 15 shows the eye diagram of the resulting differential output signals with PRBS-7 input at 820 Mb/s. The differential output signal is measured with an eye amplitude of 604 mV, a total jitter of 281 ps, and an eye opening of 65%. The measurements presented above reveal the overall performance of the LVDS circuitry. For a particular vertex detector, a more realistic test closer to the experimental condition must be performed in the future. For the application in which the transmission distance of the LVDS output signals is longer than 38.9 cm of the PCB traces, Constant Time Linear Equalization (CTLE) in the receiver can be applied to extend the driving length without increasing the power dissipation of the sensors. In addition, for the beam test, the Xilinx Virtex Series FPGAs are recommended to receive the signals from the presented LVDS driver because the data rate of its differential I/O pairs can achieve up to 1.4 Gb/s for LVDS signals [14] and it is highly compatible with the entire DAQ system design [15].
5. Conclusion
Fig. 12. LVDS test scheme.
A high speed, low power consumption LVDS interface for CPSs implemented in 0.18 mm CMOS technology was presented. A source termination technique and a special current comparator were used to increase the maximum speed and maintain low power consumption at the same time. The driver and the receiver were fully integrated into IO cells. In addition, a power down mode was designed to further reduce the power consumption. Enclosed layout transistors were used to improve the radiation tolerance. The test results demonstrated that the LVDS driver and receiver can drive the load of 38.9-cm PCB traces at data rates if up to 1.2 Gb/s for the clock input and 820 Mb/s for the PRBS-7 input, which fulfills the elementary data transmission rate requirement
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Fig. 14. Eye diagram of the differential output signals with a clock input of 1.2 Gb/s.
Fig. 15. Eye diagram of the differential output signals with PRBS-7 input at 820 Mb/s.
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Table 1 Performance summary of the LVDS driver and receiver with 1.2 Gb/s clock input. Total jitter Output amplitude Current Power consumption Cell size
130 ps 262 mV 10.9 mA 19.6 mW 0.036 mm2
of the upgraded ITS of the ALICE. Table 1 provides a performance summary of the LVDS driver and receiver with a clock input at the rate of 1.2 Gb/s.
Acknowledgments The authors thank The Duc Le for the design of the test PCB and suggestions regarding the test scheme. In particular, the support of Gilles Claus, and Mathieu Goffe during the testing is acknowledged. The authors are indebted to Christine Hu-Guo for fruitful discussions and for a review of the paper. The authors also acknowledge the support of the China Scholarship Council (Grant no. 2010606079).
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