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A high-speed multiplier using subnanosecond bipolar VLSI technologies
MICROELECTRONICS World Abstracts Papers published in 1975-1980 which are considered to be of technical merit will be abstracted by Charles E. Jowett and published in this, and subsequent issues of MicroelectronicsJournal. Abstracts in this issue comprise papers published in 1979/80. They are classified under the following headings: Integrated Circuit Technology Memories Microprocessors Optoelectronics Hybrids Discrete Devices Charged Coupled Devices Materials Production and Processing Testing Applications It is the intention, in successive issues of the Journal, to bring the paper abstracts up-to-date, presenting the reader with an easy reference to many of the important papers which have been published in journals throughout the world. 1.
I n t e g r a t e d Circuit T e c h n o l o g y 1.1 Bipolar
A high-speed multiplier using subnano~econd bipolar V131 technologies T. T A K A H A S H I , S. WAKAMATSU and K. KIMURA Fifth Solid State Circuits Conference- ESSCIRC 79, lEE Publn. 178, 110. A contemporary large scale scientific computer needs much time for executing multiplication using hardware multiplier logic. Since this type of computer has a long word length, the multiplier requires a large number of high-speed standard ICs. So it is required to develop a highly integrated multiplier LSI to improve multiplication speed and decrease the equipment cost. Although several LSIs for multiplier have been developed until recently, they were designed primarily for digital signal processing such as Fourier transform. Therefore, these multiplier LSIs are not suitable for mainframe application which requires expansible high-speed multiplier for long word length. This paper describes an expansible high-speed 8x8 bit multiplier LSI for mainframe fabricated by a newly developed advanced bipolar process technology for VLSI combined with low power CML circuit technology and logic implementation for high-speed multiplication.
1.2 LogicArrays A new ultra low power ULA and its application P. FORSHAW Microelectron. Reliab. 19,463 (1980). The ULA is a technique whereby a custom LSI circuit is produced by designing a single aluminium interconnection pattern on to a preprocessed component array. Development costs and timescales are small because only a single customising mask is required. The technique is particularly suited to the Collector Diffusion Isolation, or CDI, bipolar process, since the low resistivity N isolation diffusion and P substrate can be employed as the supply current distribution planes for all the component cells in the array. 38
Universal logic gates for custom-design IC requirements S. L. HURST Microelectron. Reliab. 19, 457 (1980). One of the fundamental problems with large-scale-integration, which clearly provides the cheapest and most reliable means of making standard digital circuit requirements, is that it is difficult to apply to special small-quantity custom requirements. It is usually completely uneconomical to undertake a unique detailed design for a silicon layout, followed by its verification, mask-making and final production without a large-quantity production run over which to spread these very high initial design costs. Attempts to overcomc this financial barrier to custom IC design and small production runs, and yet still retain the advantages of large-scaleintegration, currently involve the following: (a) the fabrication of a 'standard uncommitted' LSI chip, containing a standard array of either components or cells, the dedication of this standard chip to specific custom requirements being by the design of the final interconnect (metallisation) stage of the production processes. (b) the availability of a library of standard gates and circuits, the silicon layout design of which has been finalised, the dedication procedure being a computer-aided-design layout and interconnect of these standard gates etc. to meet the custom requirements, with the subsequent complete manufacture of the chip. It will be noted that (a) involves a single-mask interconnect design procedure only, whilst (b) involves a multiple-mask design procedure. Hence in principle method (a) should be more economical for smallquantity requirements. When consideration is given as to the most useful and versatile standard logic elements that can be proposed, the normal Boolean logic gates (AND, NAND, OR, etc.) arc found to be very inefficient basic elements. Large numbers of them frequently have to be interconnected to realise even fairly trivial logic requirements, as every digital logic designer is aware. However, recent work has suggested alternative logic elements for combinatorial design to the above Boolean family of gates, the eventual justification of which will depend upon compact circuit realisations being available in monolithic form. Among such newer elements are universal-logic-modules (ULMs) or universal-logic-gates (ULGs) [I-4], these being logic circuits which by
MICROELECTRONICS JOURNAL Vol. 12 No. 5 © 1981 Mackintosh Publications Ltd., Luton.
I n t e g r a t e d Circuit T e c h n o l o g y 1.1 Bipolar
A high-speed multiplier using subnano~econd bipolar V131 technologies T. T A K A H A S H I , S. WAKAMATSU and K. KIMURA Fifth Solid State Circuits Conference- ESSCIRC 79, lEE Publn. 178, 110. A contemporary large scale scientific computer needs much time for executing multiplication using hardware multiplier logic. Since this type of computer has a long word length, the multiplier requires a large number of high-speed standard ICs. So it is required to develop a highly integrated multiplier LSI to improve multiplication speed and decrease the equipment cost. Although several LSIs for multiplier have been developed until recently, they were designed primarily for digital signal processing such as Fourier transform. Therefore, these multiplier LSIs are not suitable for mainframe application which requires expansible high-speed multiplier for long word length. This paper describes an expansible high-speed 8x8 bit multiplier LSI for mainframe fabricated by a newly developed advanced bipolar process technology for VLSI combined with low power CML circuit technology and logic implementation for high-speed multiplication.
1.2 LogicArrays A new ultra low power ULA and its application P. FORSHAW Microelectron. Reliab. 19,463 (1980). The ULA is a technique whereby a custom LSI circuit is produced by designing a single aluminium interconnection pattern on to a preprocessed component array. Development costs and timescales are small because only a single customising mask is required. The technique is particularly suited to the Collector Diffusion Isolation, or CDI, bipolar process, since the low resistivity N isolation diffusion and P substrate can be employed as the supply current distribution planes for all the component cells in the array. 38
Universal logic gates for custom-design IC requirements S. L. HURST Microelectron. Reliab. 19, 457 (1980). One of the fundamental problems with large-scale-integration, which clearly provides the cheapest and most reliable means of making standard digital circuit requirements, is that it is difficult to apply to special small-quantity custom requirements. It is usually completely uneconomical to undertake a unique detailed design for a silicon layout, followed by its verification, mask-making and final production without a large-quantity production run over which to spread these very high initial design costs. Attempts to overcomc this financial barrier to custom IC design and small production runs, and yet still retain the advantages of large-scaleintegration, currently involve the following: (a) the fabrication of a 'standard uncommitted' LSI chip, containing a standard array of either components or cells, the dedication of this standard chip to specific custom requirements being by the design of the final interconnect (metallisation) stage of the production processes. (b) the availability of a library of standard gates and circuits, the silicon layout design of which has been finalised, the dedication procedure being a computer-aided-design layout and interconnect of these standard gates etc. to meet the custom requirements, with the subsequent complete manufacture of the chip. It will be noted that (a) involves a single-mask interconnect design procedure only, whilst (b) involves a multiple-mask design procedure. Hence in principle method (a) should be more economical for smallquantity requirements. When consideration is given as to the most useful and versatile standard logic elements that can be proposed, the normal Boolean logic gates (AND, NAND, OR, etc.) arc found to be very inefficient basic elements. Large numbers of them frequently have to be interconnected to realise even fairly trivial logic requirements, as every digital logic designer is aware. However, recent work has suggested alternative logic elements for combinatorial design to the above Boolean family of gates, the eventual justification of which will depend upon compact circuit realisations being available in monolithic form. Among such newer elements are universal-logic-modules (ULMs) or universal-logic-gates (ULGs) [I-4], these being logic circuits which by
MICROELECTRONICS JOURNAL Vol. 12 No. 5 © 1981 Mackintosh Publications Ltd., Luton.