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A highly sensitive, low-power, and wide dynamic range CMOS digital pixel sensor
Accepted Manuscript Title: A Highly Sensitive, Low-Power, and Wide Dynamic Range CMOS Digital Pixel Sensor Author: Kourosh Hassanli Sayed Masoud Sayedi Rasoul Dehghani Armin Jalili J. Jacob Wikner PII: DOI: Reference:
S0924-4247(15)30193-X http://dx.doi.org/doi:10.1016/j.sna.2015.10.032 SNA 9371
To appear in:
Sensors and Actuators A
Received date: Revised date: Accepted date:
22-7-2015 18-10-2015 19-10-2015
Please cite this article as: Kourosh Hassanli, Sayed Masoud Sayedi, Rasoul Dehghani, Armin Jalili, J.Jacob Wikner, A Highly Sensitive, Low-Power, and Wide Dynamic Range CMOS Digital Pixel Sensor, Sensors and Actuators: A Physical http://dx.doi.org/10.1016/j.sna.2015.10.032 This is a PDF file of an unedited manuscript that has been accepted for publication. As a service to our customers we are providing this early version of the manuscript. The manuscript will undergo copyediting, typesetting, and review of the resulting proof before it is published in its final form. Please note that during the production process errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.
A Highly Sensitive, Low-Power, and Wide Dynamic Range CMOS Digital Pixel Sensor Kourosh Hassanlia* [email protected], Sayed Masoud Sayedia [email protected], Rasoul Dehghania [email protected], Armin Jalilib [email protected], J Jacob Wiknerb [email protected] ac Department of Electrical and Computer Engineering, Isfahan University of Technology, Isfahan, 84156-83111, Iran d Department of Electrical Engineering, Linköping ni e i Ein ping Sweden * Corresponding author.
Highlights
We propose a new light to frequency converter to detect wide luminance range. We extract the math behind the circuit operation. The sensitivity of the circuit is higher than typical circuits in the worst case. The nonlinear characteristic of the circuit is essential to capture a clear image. There is not any distortion in the conversion because of voltage variation. Abstract
This paper proposes a new pixel-level light-to-frequency converter (LFC) that operates at a low supply voltage, and also offers low power consumption, low area, wide dynamic range, and high sensitivity. By using the proposed LFC, a digital pixel sensor (DPS) based on a pulse-frequency-modulation (PFM) scheme has been designed and fabricated. The prototype chip, including an array of 16 16 DPS with pixel size of 23×23 μm2 and 33.5% fill factor, was fabricated in a standard 180-nm CMOS technology. Experimental results show that the pixel operates with maintained output characteristics at supply voltages down to 1 V. The pixel sensor achieves an overall dynamic range of more than 142 dB and consumes 103 nW per pixel at a supply voltage of 1 V at room light intensity. The sensitivity of the LFC is very high at the lower end of the light intensity compared to the higher end which enables the ability to capture clear images.
Keywords: CMOS image sensor; digital pixel sensor; light-to-frequency conversion; pixel-level analog-to-digital converter (ADC); high speed imaging; wide dynamic range.
1. Introduction CMOS image sensors have attracted more attention compared to charge-coupled devices (CCDs) due to their superior features with respect to lower power consumption, lower voltage operation, lower cost, faster readout, higher degree of on-chip integration, excellent noise performance, and on-chip functionality [1, 2]. They have widely been used in various applications, such as wireless sensor networks, robotics, surveillance systems, mobile communication systems, industrial visions, medical, and space applications to name a few. Most existing CMOS image sensors are based on an active pixel sensor (APS) [1] in which the pixel output voltage typically drops by two threshold voltages (2V tn ) due to an nMOS reset transistor and a source-follower amplifier. The output voltage swing becomes significantly limited since, as technologies scale, the reduction of supply voltage is faster than that of the threshold voltage [1]. This fact in turns leads to a low dynamic range. Therefore, it is a challenging issue to use APSs in a high-quality CMOS image sensor implemented in a standard deep-submicron technology [1-3]. In the last decades, much effort has been spent on improving the APS in order to enhance parameters such as the sensitivity, noise, signal-to-noise ratio (SNR), imaging speed, and dynamic range. Improvements are achieved by focusing on innovations with respect to the photodetector structure, the pixel-level design itself, and technology/process modification. Example on innovations that have been introduced are new image sensors like the four-transistor APS (4TAPS), the logarithmic APS, the active column sensor (ACS) [4], and complementary APS (CAPS) [5]. In spite of these attempts, the supply voltage reduction imposes a major limit on the ability of the APS to achieve a high dynamic range. One potential solution to achieve high dynamic range and high SNR under a scaled supply voltage is to use digital pixel sensor structures, in which an ADC is included in each pixel. The DPS offers several benefits over analog image sensors such as wider dynamic range, higher SNR, lower fixed-pattern noise (FPN), and faster data readout [1]. Additionally, an important feature of the DPS is the capability to combine the on-chip image acquisition and additional processing to build more efficient image sensors [6-9]. Furthermore, new CMOS technologies enable the incorporation of an entire ADC and a memory block in each pixel. A possible drawback of the DPS is the need for more transistors in each pixel compared to that of the analog image sensors, which results in a larger pixel size. However, this issue is not a limiting factor in CMOS technologies of 180-nm and below. Many digital pixel sensors have been developed in the past few years and several in-pixel ADC architectures with a relatively small number of transistors have been proposed [610]. This paper presents a viable, fast and high dynamic range pixel-level LFC with a low power consumption to directly convert photocurrents with a high conversion gain. The converter, which can be implemented by using comparatively simple circuits, overcomes some weaknesses such as: weakness in detecting of high-light illuminations, FPN existence due to the variation in the supply voltage between distant pixels, low sensitivity of the output pulse frequency to the light intensity, and distortion in the conversion of the light intensity because of photodiode voltage variation during the exposure time that can be found in conventional in-pixel ADCs. The remaining parts of this paper are organized as follows. An overview of related work on DPS design is presented in Section 2. A pixel-level LFC and a DPS structure are presented in Section 3. Section 4 describes a VLSI implementation and the corresponding simulation results for the implemented system. Characterization and experimental results are presented in Section 5. Finally, the paper is concluded in Section 6. 2. Related work on DPS design The range that the photocurrents span under typical illumination conditions is too small to be directly converted to a digital signal. Therefore, in most digital pixel sensor structures, the photocurrent is first integrated as a voltage or charge during a pre-defined period of time. Then, the in-pixel converter converts the obtained voltage/charge to a digital signal using pulse-width modulation (PWM) or pulse-frequency modulation techniques [11]. The first PFM-based DPS was introduced in 1993 [12] while the first LFC was represented by Frohmader in 1982 [13]. The light-to-frequency converter uses an RS flip-flop where the toggling frequency is controlled by the photocurrents. These currents sequentially discharge capacitors at the flip-flop inputs to trigger a state change in the flip-flop. Most of recently proposed digital pixel sensors use an in-pixel comparator to compare the photodiode voltage with an adjustable reference voltage to convert the light intensity to a digital signal using pulse modulation techniques [14-24]. Block-level descriptions of these structures are shown in Fig. 1. The comparator output changes when the photodiode voltage drops below the reference voltage. The comparator output asserts a write signal of an in-pixel memory in the case of PWM (Fig. 1(a)) or is fed back to a reset switch in the case of PFM (Fig. 1(b)). In the case of PFM, a pixel-level counter counts the number of generated pulses during a given time period to determine the pixel illumination. The advantage of the PFM technique compared to the PWM technique is clear by its improved noise reduction. For PFM, this is due to the averaging of a number of data samples for a given period of time.
The first Nyquist-rate pixel-level ADC was proposed in 1999 [14]. The ADC performs successive comparisons using a 1-bit comparator/latch pair, which is shared between 2 2-pixel blocks to simultaneously generate one bit at a time from all pixel blocks. Bermak et al. have proposed a DPS based on the PFM scheme with a built-in light adaptation mechanism to achieve a wide dynamic range and high fill factor [15]. The reference voltage is obtained internally from the supply voltage using a voltage divider in order to reduce the reference and supply voltage variations due to losses in the interconnection over a large array. Kleinfelder et al. have demonstrated a very high frame rate imager that is based on a PWM technique [16]. An analog ramp signal is applied to the reference voltage to decrease the conversion time. A wide dynamic range and programmable-response DPS based on the PFM scheme was proposed in [17], where the performance of the conventional two-stage comparators are evaluated in the subthreshold region to design a compact, robust, wide dynamic range, and low-power DPS. Most of the previously reported results on DPS-based arrays employ circuits similar to the structures shown in Fig. 1, where the comparator should be simple, compact, robust, and consume little power. However, the reported in-pixel comparators have some problems such as: 1) Weakness in detection of high luminance lights. The reason for this weakness relates to the comparator speed. In order to reduce the comparator power consumption and maximize its gain, the transistors of the comparator operates in the weak-inversion region. This leads to a speed reduction, which results in weak detection of lights with high intensity. 2) Existence of FPN due to offset and gain variation of the comparators as well as effective supply voltage over the array. 3) Long conversion time in low-light illumination when the reference voltage is constant. 4) Low sensitivity of the output pulse frequency to the light intensity. That is because the sensitivity is inversely related to the large photodiode capacitance. 5) Large area, since transistors must have a large gate area to reduce mismatch effects in the subthreshold region. Structures that have been proposed to overcome some of these problems are described below. A DPS implementation based on PFM with an in-pixel variable reference voltage generator to increase the resolution of the pixel was presented in [18]. Their DPS reduces the integration time, especially when the level of illumination is low, by shifting the reference voltage close to the supply voltage. Thus, it can significantly improve the dynamic range. This approach reduces the complexity of the reference voltage routing in an array, and in turn also the chip area. A low-power DPS with a selfbiasing capability, input capacitance compensation, and fast ADC was proposed in [19]. Fixed-pattern noise cancellation was done by applying digital tuning (external) of both offset and gain parameters for each individual pixel without any speed penalty. Lai et al. proposed a self-offset cancellation scheme that substantially eliminates the FPN due to comparator offset [20]. A DPS based on an asynchronous self-resetting scheme that eliminates large peak currents was presented in [21]. It also offers a configurable code and spatial resolution. All above-mentioned works employed a comparator. In contrast, Yang proposed a DPS by using a light-controlled oscillator including a reset nMOS transistor and a four-stage inverter chain [22]. This design cannot detect low-light illumination levels and consumes quite much power, especially in the low-light conditions, because of short circuit paths at the inverter outputs. Andoh et al. also proposed an ADC for light conversion by employing a chain of inverters [23]; this structure is not able to detect very low light illumination either and also consumes relatively high amount of power in low light illumination. In this paper, a novel in-pixel LFC based on a multi-vibrator structure is introduced, which is able to convert a wide optical range with a higher sensitivity and lower power consumption compared to prior work. 3. The proposed digital pixel sensor In this work, a DPS structure based on pulse-frequency modulation is designed. A new multi-vibrator structure is used as an in-pixel light to frequency converter. In the following subsections, the architecture of the designed DPS, the new pixel-level LFC circuit and its operation, the mathematics supporting the LFC operation, and an employed linear feedback shift register (LFSR) block are presented. 3.1. Digital pixel sensor architecture The block diagram of the proposed DPS is shown in Fig. 2. It is composed of a photodiode, an LFC, and a digital counter/shift register. The photodiode converts the incident light to a photocurrent IPD, which is drawn from the LFC. The LFC converts the photocurrent IPD to a PFM signal, which is applied to the clock input of the counter/shift register block. The counter/shift register block counts the number of pulses generated during the integration time Tcnt to calculate the light illumination level.
3.2. The proposed in-pixel light to frequency converter A simplified circuit diagram of the proposed LFC is shown in Fig. 3. It consists of one latch, four inverters (INV1 to INV4), two current-controlled inverters (CCI1 and CCI2), four pMOS transistors (P1 to P4), and two nMOS switches (N1 and N2). The circuit structure of CCI1 and CCI2 is similar to a typical inverter, but here the source nodes of the nMOS transistors are connected to ground through a current source. The output of each CCI unit goes high very fast when its input becomes low. However, when the input becomes high, the fall time of the output is highly dependent on the strength of the current source. In this case, the nMOS transistor of the CCI is on and the current source defines the discharge time of the total output capacitance (parasitic capacitors plus gate-source capacitor) of the CCI unit. Voltages V7 and V8 are complementary thanks to the operation of the latch. Assuming voltage V8 is high and voltage V7 is low, then, voltages V1 and V5 are set to a high level and transistors N1 and P1 form a classical inverter. As a result, voltage V3 rapidly drops to a low level and pull-up transistor P4 is turned off. On the opposite end of the circuit, voltage V8 is high, voltage V6 is quickly set to low, and transistor N2 is turned off. During this time, the nMOS transistor of CCI2 is turned on and steers the current I to be able to discharge the total capacitance at node V2. In this case, transistor N2 is off and transistor P2 operates in the subthreshold region with a high trans-conductance gain. Therefore, the total capacitance at V4 is charged by the current source I. Voltage V10 becomes low when voltage V4 approaches the nMOS threshold voltage Vtn. Thus, transistor P3 is turned on and changes the state of the latch. This process alternately repeats and generates periodic pulses at the latch outputs. The frequency of the output pulse depends on the current provided by the current source.
3.3. Deriving an equation for the oscillation frequency of the proposed in-pixel light to frequency converter Figure 4 shows the circuit schematic of the proposed pixel-level LFC where the photodiode PD was previously represented by the current source I in Fig. 3. The circuit consists of four inverters (INV1 to INV4) to reduce the power dissipation, the latch circuit (the INV5 and INV6 pair), which controls the switches to generate the output pulses, and ten transistor switches (P1 to P6 and N1 to N4). Transistors N3 and P5 form CCI1, and transistors N4 and P6 form CCI2 of Fig. 3. The LFC output signal is voltage Vout which is connected to the clock input of the counter/shift register. Transistor N5 and the Start signal determine the exposure time of the pixel. The circuit of Fig. 4 operates based on what was explained above. The image capture begins when the Start signal goes from high to low. Inverters INV3 and INV4 amplifies the slowly-rising voltages V3 and V4 into sharper pulses to decrease the duration of short-circuit currents that flow in the path through the pMOS pull-up transistors and the nMOS latch transistors. Additionally, inverters INV1 and INV2 turn off the pull-down transistor N1 or N2 hen node V3 or V4 is charged. As a result, transistors N1 and P1 (or N2 and P2) are not turned on simultaneously. Therefore, these four extra inverters together eliminate the short-circuit currents, which decreases the power consumption. Moreover, with ultra-low photo diode currents, IPD, the charging procedure of nodes V3 and V4 mainly depends on the mentioned short-circuit currents flowing through transistors N1-P1 and N2-P2, respectively. This could make the conversion process almost independent of the IPD. However, in our proposed structure, by suppressing the short-circuit currents, it is assured that even for ultra-low photocurrent values, the dominant current of the circuit is the charge current injected by transistors P 1 or P2. This keeps the process still dependent on the photocurrent to a large extent. The proposed LFC can therefore detect and convert also ultra-low photocurrent values which leads to a considerably high dynamic range. The period of the output pulse is determined by the total time required to discharge the capacitances at nodes V1 (mode 1) and V2 (mode 2). Each one of these discharging modes defines one of the two bistable states of the latch. In order to extract the mathematics behind the LFC operation, the circuit is considered in mode 1 (the same holds for mode 2 and will be used later). The operational parts of the circuit in mode 1 are highlighted in Fig. 4. In mode 2, the other parts of the circuit are operational. The corresponding discharge time of the two modes is similar, so the calculated time is simply doubled to obtain the total time required. The capacitance at node V1 is discharged until pull-up transistor P4 is turned on, changing the state of the latch. Therefore, T1, the discharging time in mode 1, can be calculated as follows:
I PD C 1
dV 1 , dt
where IPD is the photocurrent and C1 is the total capacitance seen at node V1. To maintain a simple approximation, we have assumed a linear characteristics for C1. This is an assumption that is not exactly true, though we will show that the simulation and measurement results comply fairly well with each other and thus are accurate enough for our purpose. According to (1), voltage V1 can be calculated as:
V DD V 1
I PD t , C1
(2)
such that we at time T1 have:
V DD V tog
I PDT1 , C1
where Vtog is the voltage of node V1 at which the state of the latch toggles. Since transistor P1 practically operates in the subthreshold region, the V DD V tog is typically lower than the transistor threshold voltage. In the subthreshold region, the source-drain current of transistor P1 can be calculated as [25]: V SG 1 V tp nV T
W I SD 1 I 0 e L 1
V 1 e V
SD 1 T
,
where I0 is a technology-dependent scaling parameter, Vtp is the pMOS threshold voltage, n is the subthreshold gate coupling coefficient, VT is the thermal voltage, and W and L are the channel width and length of transistor P1, respectively. Since the source-drain voltage is much higher than the thermal voltage, (4) can be approximately rewritten as: V SG 1 V tp nV T
W I SD 1 I 0 e L 1
,
where VSG1=VDD – V1. Therefore, according to (2) we have: I PD t C 1 V tp nC 1V T
W I SD 1 I 0 e L 1
.
(6)
The charging process building up the voltage V3 can be modeled as (once again assuming a linear capacitance):
I SD 1 C 3
dV 3 , dt
where C3 is the total capacitance at V3. Node V3 must be charged from 0 to Vtn before it can change the state of the latch. Integration of (7) over the mentioned voltage range gives:
V tn
0
C 3dV 3 I SD 1dt . T1
0
Replacing ISD1 from (6) in (8) yields: V I PDC 3V tn L1 nV nC 1V T T1 ln 1 e nC 1V T I 0W 1 I PD
tp T
.
Assuming a 50% duty cycle, we can calculate the output pulse frequency as:
f
1 f 2T1
I PD V I CV L 2nC 1V T ln 1 PD 3 tn 1 e nV nC 1V T I 0W 1
tp T
.
According to (10), the pulse frequency is highly sensitive to the photocurrent since capacitance C1 is very small. It should be noted that the output pulse frequency is much higher than that of the conventional, reported in-pixel ADCs [1424]. The output pulse frequency of prior work is inversely related to the photodiode capacitance (which is normally large), while in the proposed LFC, the output pulse frequency is inversely proportional to the transistor capacitances (parasitics plus the effective gate-source capacitance). Moreover, the frequency is independent of the supply voltage and external signals. This feature is very remarkable for high-resolution image sensors where variations in the supply voltage of distant pixels are very likely to be high. Figure 5(a) shows the calculated output pulse frequency versus the photocurrent based on (10) for a typical design condition. As is evident, the simulated curve shows a relatively linear characteristic. The dashed line shows the ideal, linear characteristics and the deviation from this line can be exp e ed b he e m “in eg al nonlinea i ” (IN ) which is also plotted in Fig. 5(b). The maximum INL (0.066 GHz in this example) indicates the effective resolution for image capturing. It is worth mentioning that for various design conditions, i.e., different capacitance values and transistor aspect ratios, the frequency of the output pulse has nearly the same transfer characteristics. The same condition holds for different process parameters such as the threshold voltage and I0 in (10). 3.4. The counter/shift register block structure The counter/shift register block is designed using a linear-feedback shift register structure to attain an area-efficient DPS. An LFSR is normally realized using an array of shift registers in which the input bit is driven by an XNOR function taking some of the bits in the array chain. The LFSRs offer a simple structure and can be implemented with a compact and regular layout. The circuit can operate as a counter or as a shift register. As a counter, it does not count in a binary sequence format, so an offline decoder must be used to obtain valid image information. Figure 6 shows the 10-bit LFSR in a so called Fibonacci configuration. The LFSR generates pseudorandom sequences when it acts as a counter during the defined exposure time, Tcnt. After exposure time, the configuration of the circuit changes to a shift register in order to read out the pixel information. Therefore, any additional read-out circuit is not really required during the read-out period.
4. VLSI implementation and simulation results In order to verify the functionality of the proposed DPS, it has been designed and implemented in a 180-nm CMOS technology. In this design, a conventional n+/p-substrate diode is used to implement the photodiode. Transistors P 5, P6, N3, and N4 are thick-oxide devices which reduces the relatively large subthreshold leakage current which further enables circuit to detect low-light illumination and also to widen the LFC dynamic range. Based on (10), only the capacitance C1 has a significant role on the frequency characteristics of the circuit; and variations of capacitance C3 have little impact on the output pulse frequency. Transistors P1 and P2 are designed with dimensions greater than the minimum size to decrease the mismatch effect of C1. However, the sensitivity of the output pulse frequency to the photocurrent is decreased when increasing capacitance C1. All the remaining transistors of the circuit are designed with minimum-size devices, except for P3 and P4. The layout of a complete DPS is shown in Fig. 7. The circuit occupies an area of 23×23 µm2 and achieves a fill factor of 33.5%.
Capacitances C1 and C3 are considerably affected during layout: wire routing and boundary effects during physical implementation of the circuit add parasitic components to the capacitance. Discrepancies between theoretical and simulated results stem from the added parasitics and differences in the results between schematic-level and post-layout simulations show that the duty cycle deviates from the desired 50%, as evident in Fig. 8. For simulation purposes, the light intensity is modeled and simulated with a current source in parallel with the photodiode. Figure 8 illustrates the post-layout simulation results for a photocurrent of 1 nA and a supply voltage of 1 V. The output pulse frequency is 308.4 kHz. Figures from top to bottom at the left hand side show the voltages Start, V1, V2, and V3, respectively. The waveforms on the right hand side, from top to bottom, show nodes V4, V7, V8, and output Vout, respectively. The outputs from the complementary latch control the switches and steer the photocurrent alternately to discharge node V1 or V2 such that pulses can be generated at the output Vout. The output waveform has a good quality and the rise/fall times show little dependency on the switching period. The LFC output signal is a PFM signal with a frequency proportional to the photocurrent. The exposure time begins when the Start signal goes low. At this moment, the LFSR operates as a counter to count the LFC output pulses and determine the light intensity. During the exposure time, all pixels operate in parallel. After exposure time, the Start signal goes back to high and the LFSR acts as a shift register to read out digital values of the pixels stored in internal registers. In addition, during this time, the LFSR is initiated to
prepare for the next frame capture. In this scheme, no read-out circuit is needed and hence the area is fully dedicated to the photodetector array which increases the fill factor.
Figure 9 shows the LFC output pulses and the voltage across the photodiode as the photocurrent is changed. Waveforms from top to bottom correspond to photocurrent IPD, LFC output signal, and the voltage across the photodiode, respectively. As shown in the figure, the variation of the photodiode voltage is only some 30 mV when the photocurrent changes from 1 nA to 3 nA. Therefore, the voltage across the photodiode is almost constant during exposure time and the generated photocurrent just depends on the light intensity. In previous work [12-24], however, the voltage across the photodiode decreases with the exposure time. As a result, the dependency of the photocurrent on the reverse voltage across the photodiode causes distortion, to some extent, in the light conversion process. Figure 10(a) shows the output pulse frequency with respect to the photocurrent thus illustrating the theoretical, simulation, and post-layout simulation results. The discrepancies between theoretical and simulation results are due to the parasitic capacitance of the transistors connected to the nodes of V1 and V2. They were not considered in the estimation of C1 value in (10). The differences between schematic and post-layout simulation results arise from the routing parasitic capacitance. The simulation results for different supply voltages prove that the output pulse frequency has little dependency on the supply voltage. The proposed LFC detects and converts photocurrents in the range of femto- to microamperes so that the LFC can accommodate a very wide dynamic range. The effect of the process mismatch on the stability of the output pulse frequency is examined by performing a set of Monte-Carlo analyses using 500 outcomes. The results are shown in Fig. 10(b) for a nominal photocurrent of 1 nA. The circuit shows a 1-sigma variation of about 3.14% and has a mean value of 308.47 kHz.
5. Experimental results of a 16×16 array A test structure of a 16×16 array of the proposed DPS was implemented in a 180-nm CMOS technology such that we could investigate the pulse frequency response with respect to the light intensity. Figure 11 shows the microphotograph of the prototype chip. A single Start signal is used to control the timing, and no additional control circuitry is required. The chip is fully operational without any extra hardware. To evaluate the performance of the circuit, the power supply of the circuit is set to 1 V and an adjustable light source is employed. The pulse frequency of one sample LFC of the array was measured for different light intensity levels. Figure 12(a) shows the pulse frequency for seven decades of intensities. The measurements are done separately for each light intensity. In the figure, the lower limit is theoretically determined by the dark current. The maximum available intensity level used in our experimental setup could not bring the sensor to saturation and more than 142 dB operating range was achievable. The power consumption of one pixel under room light illumination and 1 V bias condition is 103 nW. In this condition, the frequency of the output pulse is about 330 kHz. According to the measured data of Fig. 12(a), the sensitivity of the output pulse frequency with respect to the light intensity is shown in Fig. 12(b). As can be seen, the proposed LFC is more sensitive to changes in the darker end of the luminance range compared to similar changes in brighter areas. The sensitivity at the lower end of the intensity is about 750 kHz/(mW/cm2) and is about 58 kHz/(mW/cm2) at the higher end. Therefore, the circuit is capable of discriminating the details in the dark areas while the resolution is high. This feature is essential for capturing details in shady parts of the scenes, and for producing a clear image. This nonlinear behavior is like the logarithmic APS characteristic that has a wide nonlinear dynamic range [26], so the proposed sensor can display clearly dark scenes too. The main drawback of the logarithmic APS is image lag at low luminance [26]. However, our proposed structure does not have any image lag when the light illumination changes and the response does not saturate in the high light illumination. In this nonlinear sensor, ten bits of resolution are sufficient to display over seven decades of luminance. However, to have the same accuracy using a linear sensor with 142 dB dynamic range, 24 bits would be required, which is not suitable for high-speed imaging, data transmission, and data storage in each pixel [27, 28].
Table 1 summarizes the performance of the presented digital pixel sensor and illustrates the comparison results between the proposed DPS and conventional DPSs. As can be seen, the proposed DPS compares very well against prior art. The dynamic range is increased to over 142 dB and the power consumption is reduced. Additionally, the sensitivity of the output pulse frequency to the light intensity is higher than that of typical DPS values. The measured fix-pattern noise of the array is approximately 3%. However, it can be further improved by storing the measured dark signal of each pixel as an initial value in the respective register. The fill factor of the proposed DPS is increased to 33.5% because of the compact LFC. In order to have a fair comparison with other reported structures, by considering the most important parameters of a DPS, the figure of merit (FOM) of the structures can be defined as:
Pdiss PP FOM DR 20log(FF ) 20log m 10log nW , 1 1
(11)
where DR is the measured dynamic range in dB, FF is the fill factor, PP is the pixel pitch in µm, and Pdiss is the DC power consumption of each pixel in nW. The area term is included in the FOM because the occupied area and fill factor of each pixel are critical parameters. The measured FOM for the proposed DPS is 138.75 dB at 1 V supply voltage. As can be seen, the proposed DPS has better performance compared to other structures. 6. Conclusion In this paper, a new pixel-level LFC based on a modified multi-vibrator structure with the aim of having a wide dynamic range image sensor with low power consumption, high sensitivity, and low area was proposed. In order to demonstrate the capability of the proposed LFC, a DPS array was designed and fabricated in a 180-nm CMOS technology. Experimental results illustrate that the dynamic range is over 142 dB, fill factor is about 33.5%, and the sensitivity of the output pulse frequency to the light intensity changes between 58 to 750 kHz/(mW/cm2) to capture a clear image from a high dynamic range scene. Therefore, building an imager with high-resolution and high frame-rate is feasible. Additionally, the circuit performance is independent of the supply voltage and external signals and the circuit is compatible with technology scaling. Moreover, in the proposed LFC, the voltage across the photodiode in the exposure time is practically constant so the distortion in the conversion of light intensity to digital signal is eliminated. These features comply with the underlying camera requirements.
Biographies Kourosh Hassanli was born in Shiraz, Iran, in 1977. He received the B.Sc. and M.Sc. degrees in electrical engineering from Shiraz University and Iran University of Science and Technology, in 2000 and 2002, respectively. He is currently working towards the Ph.D. degree in electrical engineering at Isfahan University of Technology (IUT). His interests include smart image sensor and low-power circuits design. Sayed Masoud Sayedi was born in Maragheh, Iran, in 1960. He received the B.Sc. and M.Sc. degrees in electrical engineering from Isfahan University of Technology (IUT), and the Ph.D. degree in electronics from Concordia University in 1986, 1988, and 1996, respectively. From 1988 to 1992, and then since 1997, he has been with IUT, where he is currently an associate professor in the Department of Electrical and Computer Engineering. His areas of interest include VLSI fabrication processes, low power VLSI circuits, and data converters. Rasoul Dehghani received the B.Sc., M.Sc. and PhD degrees all in electrical engineering from Sharif University of Technology, Tehran, Iran, in 1988, 1991 and 2004, respectively. From 1998 to 2004 he worked with Emad Co., Tehran, Iran, and then joined to Jaalaa Co., Kuala Lumpur, Malaysia, where worked as a senior IC design engineer. Since 2006, he has been Assistant Professor of electrical engineering at Isfahan University of Technology, I fahan I an. He i he au ho of ’De ign of CMO Ope a ional Amplifie ’ (A ech Hou e 2013). His current research interests include RF IC design for wireless communication, frequency synthesis, and low-voltage and low-power circuits. Armin Jalili was born in Behbahan, Iran, in 1982. He received the B.Sc., M.Sc., and PhD degrees in electrical engineering from Isfahan University of Technology (IUT), in 2004 and 2006, and 2012 , respectively. He is currently working as a researcher in Link Öping university. His interests include data converters, vision sensory applications, low power circuits and energy harvesting system design. J. Jacob Wikner received the M.Sc. and Ph.D. degrees from Linkoping University, in 1996 and 2001, respectively. He has been working at Ericsson Microelectronics, later Infineon Technologies, with high-speed data converters for telecommunication applications. From 2005 to 2009, he was with Sicon Semiconductor AB in Sweden developing AFEs for video applications. Since 2009, he is with the Department of Electrical Engineering at Linkoping University as an associate professor. His research interests include biologically inspired architectures, high-speed A/D and D/A converters, and mixed-signal design. He holds six patents, has published 40 scientific papers, and has co-au ho ed “CMO Da a Con e e fo Telecommunica ion”.
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A. El Gamal, and H. Eltoukhy, CMOS image sensors, IEEE circuits and devices magazine, 21 (2005) 6-20. E.R. Fossum, Digital camera system on a chip, IEEE micro journal, 18 (1998) 8-15. E.R. Fossum, J. Hynecek, J. Tower, N. Teranishi, J. Nakamura, P. Magnan, and A.J.P. Theuwissen, Special issue on solid-state image sensors, IEEE transactions on electron devices, 56 (2009) 2376-2379. S. Diller, A. Fish, and O. Yadid-Pecht, Advanced output chains for CMOS image sensors based on an active column sensor approach - a detailed comparison, Journal of sensors and actuators A, 116 (2004) 304-311. M. Bigas, E. Cabruja, J. Forest, and J. Salvi, Review of CMOS image sensors, Microelectronics journal, 37 (2006) 433-451. K. Ito, B. Tongprasit, and T. Shibata, A computational digital pixel sensor featuring block-readout architecture for on-chip image processing, IEEE transactions on circuits and systems I: regular papers, 56 (2009) 114-123. X. Xie, G. Li, X. Chen, X. Li, and Z. Wang, A low-power digital IC design inside the wireless endoscopic capsule, IEEE journal of solid-state circuits, 41 (2006) 2390-2400. M. Sarkar, D.S.S. Bello, C. Van Hoof, and A.J.P. Theuwissen, Biologically inspired CMOS image sensor for fast motion and polarization detection, IEEE sensors journal, 13 (2013) 1065-1073. H. Zhu, and T. Shibata, A real-time motion-feature-extraction image processor employing digital-pixel-sensor-based parallel architecture, Proceedings of IEEE international symposium on circuits and systems, Seoul, Korea, (20-23 May) (2012) 1612-1615. T. Chen, P. Catrysse, A. El Gamal, and B. Wandell, How small should pixel size be?, Proceedings of SPIE, 3965 (2000) 451–461. D.G. Chen, D. Matolin, A. Bermak, and C. Posch, Pulse-modulation imaging - review and performance analysis, IEEE transactions on biomedical circuits and systems, 5 (2011) 64-82. K. Tanaka, F. Ando, K. Taketoshi, I. Ohishi, and G. Asari, Novel digital photosensor cell in GaAs IC using conversion of light intensity to pulse frequency, Japanese journal of applied physics, 32 (1993) 5002–5007. K.P. Frohmader, A novel MOS compatible light intensity-to-frequency converter suited for monolithic integration, IEEE journal of solid-state circuits, 17 (1982) 588-591. D.X.D. Yang, B. Fowler, and A. El Gamal, A nyquist-rate pixel-level ADC for CMOS image sensors, IEEE journal of solid-state circuits, 34 (1999) 348-356. A. Bermak, A. Bouzerdoum, and K. Eshraghian, A vision sensor with on-pixel ADC and in-built light adaptation mechanism, Microelectronics journal, 33 (2002) 1091–1096. S. Kleinfelder, S. Lim, X. Liu, and A. El Gamal, A 10000 frames/s CMOS digital pixel sensor, IEEE journal of solid-state circuits, 36 (2001) 2049-2059. X. Wang, W. Wong, and R. Hornsey, A high dynamic range CMOS image sensor with inpixel light-to-frequency conversion, IEEE transations on electron devices, 53 (2006) 2988-2992. Y. Chen, F. Yuan, and G. Khan, A new wide dynamic range CMOS pulse-frequency-modulation digital image sensor with in-pixel variable reference voltage, Proceedings of 51st midwest symposium on circuits and systems, Knoxville, USA, (10-13 August) (2008) 129-132. J.M. Margarit, L. Terés, and F. Serra-Graells, A sub-µW fully tunable CMOS DPS for uncooled infrared fast imaging, IEEE transactions on circuits and systems I: regular papers, 56 (2009) 987-996. C.H. Lai, Y.C. King, and S.Y. Huang, A 1.2-V 0.25-µm clock output pixel architecture with wide dynamic range and self-offset cancellation, IEEE sensors journal, 6 (2006) 398-405. A. Bermak, and Y.F. Yung, A DPS array with programmable resolution and reconfigurable conversion time, IEEE transactions on very large scale integration (VLSI) systems, 14 (2006) 15-22. W. Yang, A wide-dynamic-range, low-power photosensor array, Proceedings of 41st IEEE international solid-state circuits conference, San Francisco, USA, (16-18 February) (1994) 230-231. F. Andoh, H. Shimamoto, and Y. Fujita, A digital pixel image sensor for real-time readout, IEEE transactions on electron devices, 47 (2000) 2123-2127. C. Shoushun, F. Boussaid, and A. Bermak, Robust intermediate read-out for deep submicron technology cmos image sensors, IEEE sensors journal, 8 (2008) 286–294. Y. Tsividis, C. McAndrew, Operation and modeling of the MOS transistor, third edition, Oxford university press, New York, ISBN 9780195170153, (2011). W.F. Chou, S.F. Yeh, C.F. Chiu, and C.C. Hsieh, A linear-logarithmic CMOS image sensor with pixel-FPN reduction and tunable response curve, IEEE sensors journal, 14 (2014) 1625-1632. A. Darmont, Methods to extend the dynamic range of snapshot active pixels sensors, Proceedings of SPIE, 6816 (2008) 1-11. D. Joseph, and S. Collins, Modeling, calibration and correction of nonlinear illumination-dependent fixed pattern noise in logarithmic CMOS image sensor, IEEE transactions on instrumentation and measurement, 51 (2001) 996-1001.
Figure Captions VDD
VDD
Vrese t
Feedback
Vref
CPD
Vout
Write
Memory
Counter
Comparator Data bus
(a)
CPD Vref Comparator
(b)
Figure 1.Digital pixel sensor circuit architectures based on a) pulse-width-modulation scheme and b) pulse-frequencymodulation scheme.
Sel_Tcnt
IPD
Enable
LFC
Counter/shift register
Photodiode
Figure 2. Block diagram of the designed digital pixel sensor.
Digital readout
VDD
P3
P4
V10
V9 VDD
VDD
V1
P1
VDD
VDD
V7
Latch
CCI1
V8
V2
V3 INV3
N1
P2
CCI2
V4 V5
V6 INV1
I
INV4
N2
INV2
Figure 3. The block diagram of the proposed pixel-level light to frequency converter.
VDD P3 P4 P5
P6 INV5
V7
V1 V3
N3
V8
P1
P2
INV6
INV4
INV3
Vout
N1 INV1
Start
V2 V4
N2
N4
INV2
N5
PD
IPD
Figure 4. The circuit schematic diagram of the proposed light to frequency converter. The operational part of the circuit in mode 1 is highlighted and the light part indicates the off transistors during this mode.
0.07
Frequency vs. photocurrent based on equation (10) Ideal linear characteristic
Integral Nonlinearity (GHz)
Output Pulse Frequency (GHz)
3.5 3 2.5 2 1.5 1
0.06 0.05 0.04 0.03 0.02 0.01
0.5 2
4 6 Photocurrent, I PD (A)
8
10
0
2
4 6 Photocurrent, I PD (A)
8
10
(b) (a) Figure 5. a) The LFC output pulse frequency versus the photocurrent according to (10) in a typical design condition (solid curve) and the ideal linear characteristic (dashed line). b) The corresponding INL curve with respect to the photocurrent value.
Sel-Tcnt Y
1
Serial-In
0 MUX
Q7
Q10
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
clk
clk
clk
clk
clk
clk
clk
clk
clk
clk
clk
Figure 6. The 10-bit LFSR structure.
Pixel-out
10-bit LFSR
Control circuits Photodiode + (n /p-substrate)
Figure 7. The layout of the proposed DPS.
LFC
Figure 8. Post-layout simulation results of the pixel-level LFC for a photocurrent of 1 nA. Waveforms from top to bottom at the left hand side correspond to the Start signal, and nodes V1, V2, and V3. The waveforms at the right hand side from top to bottom correspond to nodes V4, V7, V8, and output Vout.
Figure 9. Simulation results of the in-pixel LFC when the photocurrent changes. Waveforms from top to bottom corresponding to photocurrent IPD, LFC output pulses, and the voltage across the photodiode over a time span.
10
10
10
10
4
60 Based on equation (10) Simulation results Post-layout simulation results
2
Number of iterations=500
50 =308.474 kHz Number of Iteration
Output Pulse-Frequency (MHz)
10
0
-2
30 20 10
-4
10
=9.70914 kHz
40
-4
10
-2
0
10 10 Photocurrent, I PD (nA)
(a)
2
10
4
0 260
280 300 320 340 Output Pulse Frequency (kHz)
360
(b)
Figure 10. a) The calculated output pulse frequency with respect to the photocurrent compare to the simulation and postlayout simulation results at 1.8 V supply voltage. b) The histogram of the pulse frequency of the proposed LFC for a Monte-Carlo analyses with 500 outcomes when the photocurrent is 1 nA.
A 16×16 DPS Array
Figure 11. Microphotograph of the 16×16 fabricated pixel array.
800
Sensitivity (kHz/(mW/cm2))
700
DR=142 dB
600 500 400 300 200 100 0 -4 10
10
-2
10
0
10
2
10
4
2
Light Intensity (mW/cm )
(a)
(b)
Figure 12. Pixel response as a function of light intensity. a) The sensor exhibits over 142 dB optical dynamic range. b) The sensitivity variation with respect to the light intensity.
Table Table 1. The prototype chip specifications and performance comparison between the proposed design and other works. Estimated numbers are indicated by (EST). Specifications
Bermak et al. [15]
Kleinfelder et al. [16]
Wang et al. [17]
Lai et al. [20]
Bermak et al. [21]
Shoushun et al. [24]
This work
CMOS technology
0. 25 µm
180 nm
180 nm
0.25 µm
0.35 µm
0.35 µm
180 nm
Technique
PFM
PWM
PFM
PFM
PWM
PFM
PFM
64×64
16×16
Resolution
32×32
352×288
28×28
640×480
Reconfigurable 32×64/64×64
Supply voltage (V)
2.5
1.8
1.2
1.2~2.5
3.3
3.3
1
Pixel pitch (µm)
45
9.4
23
9.4
50
50
23
ADC type
In-pixel
In-pixel
In-pixel
In-column
In-pixel
In-pixel
In-pixel
Fill factor (%)
23
15
25
24
20
20
33.5
Photo detector type
n+/p-sub
nMOS photogate
n+/p-sub
n+/p-sub
N/A
n+/p-sub
n+/p-sub
Optical Dynamic range (dB)
Programmable
N/A
130
76
90
>90
>142
Power consumption/ pixel
80 µW (EST)
400 nW (EST)
250 nW
11~81 µW
4500 nW (EST)
2000 nW
103 nW
Sensitivity
N/A
N/A
kHz/(mW/cm2)
N/A
N/A
kHz/(mW/cm2)
kHz/(mW/cm2)
FPN (%)
N/A
0.027
5
1.6
0.8
0.71
3
FOM (dB)
N/A
N/A
120.4
47.4
62.5
66.02
138.75
6.9
34 (EST)
58~750
S0924-4247(15)30193-X http://dx.doi.org/doi:10.1016/j.sna.2015.10.032 SNA 9371
To appear in:
Sensors and Actuators A
Received date: Revised date: Accepted date:
22-7-2015 18-10-2015 19-10-2015
Please cite this article as: Kourosh Hassanli, Sayed Masoud Sayedi, Rasoul Dehghani, Armin Jalili, J.Jacob Wikner, A Highly Sensitive, Low-Power, and Wide Dynamic Range CMOS Digital Pixel Sensor, Sensors and Actuators: A Physical http://dx.doi.org/10.1016/j.sna.2015.10.032 This is a PDF file of an unedited manuscript that has been accepted for publication. As a service to our customers we are providing this early version of the manuscript. The manuscript will undergo copyediting, typesetting, and review of the resulting proof before it is published in its final form. Please note that during the production process errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.
A Highly Sensitive, Low-Power, and Wide Dynamic Range CMOS Digital Pixel Sensor Kourosh Hassanlia* [email protected], Sayed Masoud Sayedia [email protected], Rasoul Dehghania [email protected], Armin Jalilib [email protected], J Jacob Wiknerb [email protected] ac Department of Electrical and Computer Engineering, Isfahan University of Technology, Isfahan, 84156-83111, Iran d Department of Electrical Engineering, Linköping ni e i Ein ping Sweden * Corresponding author.
Highlights
We propose a new light to frequency converter to detect wide luminance range. We extract the math behind the circuit operation. The sensitivity of the circuit is higher than typical circuits in the worst case. The nonlinear characteristic of the circuit is essential to capture a clear image. There is not any distortion in the conversion because of voltage variation. Abstract
This paper proposes a new pixel-level light-to-frequency converter (LFC) that operates at a low supply voltage, and also offers low power consumption, low area, wide dynamic range, and high sensitivity. By using the proposed LFC, a digital pixel sensor (DPS) based on a pulse-frequency-modulation (PFM) scheme has been designed and fabricated. The prototype chip, including an array of 16 16 DPS with pixel size of 23×23 μm2 and 33.5% fill factor, was fabricated in a standard 180-nm CMOS technology. Experimental results show that the pixel operates with maintained output characteristics at supply voltages down to 1 V. The pixel sensor achieves an overall dynamic range of more than 142 dB and consumes 103 nW per pixel at a supply voltage of 1 V at room light intensity. The sensitivity of the LFC is very high at the lower end of the light intensity compared to the higher end which enables the ability to capture clear images.
Keywords: CMOS image sensor; digital pixel sensor; light-to-frequency conversion; pixel-level analog-to-digital converter (ADC); high speed imaging; wide dynamic range.
1. Introduction CMOS image sensors have attracted more attention compared to charge-coupled devices (CCDs) due to their superior features with respect to lower power consumption, lower voltage operation, lower cost, faster readout, higher degree of on-chip integration, excellent noise performance, and on-chip functionality [1, 2]. They have widely been used in various applications, such as wireless sensor networks, robotics, surveillance systems, mobile communication systems, industrial visions, medical, and space applications to name a few. Most existing CMOS image sensors are based on an active pixel sensor (APS) [1] in which the pixel output voltage typically drops by two threshold voltages (2V tn ) due to an nMOS reset transistor and a source-follower amplifier. The output voltage swing becomes significantly limited since, as technologies scale, the reduction of supply voltage is faster than that of the threshold voltage [1]. This fact in turns leads to a low dynamic range. Therefore, it is a challenging issue to use APSs in a high-quality CMOS image sensor implemented in a standard deep-submicron technology [1-3]. In the last decades, much effort has been spent on improving the APS in order to enhance parameters such as the sensitivity, noise, signal-to-noise ratio (SNR), imaging speed, and dynamic range. Improvements are achieved by focusing on innovations with respect to the photodetector structure, the pixel-level design itself, and technology/process modification. Example on innovations that have been introduced are new image sensors like the four-transistor APS (4TAPS), the logarithmic APS, the active column sensor (ACS) [4], and complementary APS (CAPS) [5]. In spite of these attempts, the supply voltage reduction imposes a major limit on the ability of the APS to achieve a high dynamic range. One potential solution to achieve high dynamic range and high SNR under a scaled supply voltage is to use digital pixel sensor structures, in which an ADC is included in each pixel. The DPS offers several benefits over analog image sensors such as wider dynamic range, higher SNR, lower fixed-pattern noise (FPN), and faster data readout [1]. Additionally, an important feature of the DPS is the capability to combine the on-chip image acquisition and additional processing to build more efficient image sensors [6-9]. Furthermore, new CMOS technologies enable the incorporation of an entire ADC and a memory block in each pixel. A possible drawback of the DPS is the need for more transistors in each pixel compared to that of the analog image sensors, which results in a larger pixel size. However, this issue is not a limiting factor in CMOS technologies of 180-nm and below. Many digital pixel sensors have been developed in the past few years and several in-pixel ADC architectures with a relatively small number of transistors have been proposed [610]. This paper presents a viable, fast and high dynamic range pixel-level LFC with a low power consumption to directly convert photocurrents with a high conversion gain. The converter, which can be implemented by using comparatively simple circuits, overcomes some weaknesses such as: weakness in detecting of high-light illuminations, FPN existence due to the variation in the supply voltage between distant pixels, low sensitivity of the output pulse frequency to the light intensity, and distortion in the conversion of the light intensity because of photodiode voltage variation during the exposure time that can be found in conventional in-pixel ADCs. The remaining parts of this paper are organized as follows. An overview of related work on DPS design is presented in Section 2. A pixel-level LFC and a DPS structure are presented in Section 3. Section 4 describes a VLSI implementation and the corresponding simulation results for the implemented system. Characterization and experimental results are presented in Section 5. Finally, the paper is concluded in Section 6. 2. Related work on DPS design The range that the photocurrents span under typical illumination conditions is too small to be directly converted to a digital signal. Therefore, in most digital pixel sensor structures, the photocurrent is first integrated as a voltage or charge during a pre-defined period of time. Then, the in-pixel converter converts the obtained voltage/charge to a digital signal using pulse-width modulation (PWM) or pulse-frequency modulation techniques [11]. The first PFM-based DPS was introduced in 1993 [12] while the first LFC was represented by Frohmader in 1982 [13]. The light-to-frequency converter uses an RS flip-flop where the toggling frequency is controlled by the photocurrents. These currents sequentially discharge capacitors at the flip-flop inputs to trigger a state change in the flip-flop. Most of recently proposed digital pixel sensors use an in-pixel comparator to compare the photodiode voltage with an adjustable reference voltage to convert the light intensity to a digital signal using pulse modulation techniques [14-24]. Block-level descriptions of these structures are shown in Fig. 1. The comparator output changes when the photodiode voltage drops below the reference voltage. The comparator output asserts a write signal of an in-pixel memory in the case of PWM (Fig. 1(a)) or is fed back to a reset switch in the case of PFM (Fig. 1(b)). In the case of PFM, a pixel-level counter counts the number of generated pulses during a given time period to determine the pixel illumination. The advantage of the PFM technique compared to the PWM technique is clear by its improved noise reduction. For PFM, this is due to the averaging of a number of data samples for a given period of time.
The first Nyquist-rate pixel-level ADC was proposed in 1999 [14]. The ADC performs successive comparisons using a 1-bit comparator/latch pair, which is shared between 2 2-pixel blocks to simultaneously generate one bit at a time from all pixel blocks. Bermak et al. have proposed a DPS based on the PFM scheme with a built-in light adaptation mechanism to achieve a wide dynamic range and high fill factor [15]. The reference voltage is obtained internally from the supply voltage using a voltage divider in order to reduce the reference and supply voltage variations due to losses in the interconnection over a large array. Kleinfelder et al. have demonstrated a very high frame rate imager that is based on a PWM technique [16]. An analog ramp signal is applied to the reference voltage to decrease the conversion time. A wide dynamic range and programmable-response DPS based on the PFM scheme was proposed in [17], where the performance of the conventional two-stage comparators are evaluated in the subthreshold region to design a compact, robust, wide dynamic range, and low-power DPS. Most of the previously reported results on DPS-based arrays employ circuits similar to the structures shown in Fig. 1, where the comparator should be simple, compact, robust, and consume little power. However, the reported in-pixel comparators have some problems such as: 1) Weakness in detection of high luminance lights. The reason for this weakness relates to the comparator speed. In order to reduce the comparator power consumption and maximize its gain, the transistors of the comparator operates in the weak-inversion region. This leads to a speed reduction, which results in weak detection of lights with high intensity. 2) Existence of FPN due to offset and gain variation of the comparators as well as effective supply voltage over the array. 3) Long conversion time in low-light illumination when the reference voltage is constant. 4) Low sensitivity of the output pulse frequency to the light intensity. That is because the sensitivity is inversely related to the large photodiode capacitance. 5) Large area, since transistors must have a large gate area to reduce mismatch effects in the subthreshold region. Structures that have been proposed to overcome some of these problems are described below. A DPS implementation based on PFM with an in-pixel variable reference voltage generator to increase the resolution of the pixel was presented in [18]. Their DPS reduces the integration time, especially when the level of illumination is low, by shifting the reference voltage close to the supply voltage. Thus, it can significantly improve the dynamic range. This approach reduces the complexity of the reference voltage routing in an array, and in turn also the chip area. A low-power DPS with a selfbiasing capability, input capacitance compensation, and fast ADC was proposed in [19]. Fixed-pattern noise cancellation was done by applying digital tuning (external) of both offset and gain parameters for each individual pixel without any speed penalty. Lai et al. proposed a self-offset cancellation scheme that substantially eliminates the FPN due to comparator offset [20]. A DPS based on an asynchronous self-resetting scheme that eliminates large peak currents was presented in [21]. It also offers a configurable code and spatial resolution. All above-mentioned works employed a comparator. In contrast, Yang proposed a DPS by using a light-controlled oscillator including a reset nMOS transistor and a four-stage inverter chain [22]. This design cannot detect low-light illumination levels and consumes quite much power, especially in the low-light conditions, because of short circuit paths at the inverter outputs. Andoh et al. also proposed an ADC for light conversion by employing a chain of inverters [23]; this structure is not able to detect very low light illumination either and also consumes relatively high amount of power in low light illumination. In this paper, a novel in-pixel LFC based on a multi-vibrator structure is introduced, which is able to convert a wide optical range with a higher sensitivity and lower power consumption compared to prior work. 3. The proposed digital pixel sensor In this work, a DPS structure based on pulse-frequency modulation is designed. A new multi-vibrator structure is used as an in-pixel light to frequency converter. In the following subsections, the architecture of the designed DPS, the new pixel-level LFC circuit and its operation, the mathematics supporting the LFC operation, and an employed linear feedback shift register (LFSR) block are presented. 3.1. Digital pixel sensor architecture The block diagram of the proposed DPS is shown in Fig. 2. It is composed of a photodiode, an LFC, and a digital counter/shift register. The photodiode converts the incident light to a photocurrent IPD, which is drawn from the LFC. The LFC converts the photocurrent IPD to a PFM signal, which is applied to the clock input of the counter/shift register block. The counter/shift register block counts the number of pulses generated during the integration time Tcnt to calculate the light illumination level.
3.2. The proposed in-pixel light to frequency converter A simplified circuit diagram of the proposed LFC is shown in Fig. 3. It consists of one latch, four inverters (INV1 to INV4), two current-controlled inverters (CCI1 and CCI2), four pMOS transistors (P1 to P4), and two nMOS switches (N1 and N2). The circuit structure of CCI1 and CCI2 is similar to a typical inverter, but here the source nodes of the nMOS transistors are connected to ground through a current source. The output of each CCI unit goes high very fast when its input becomes low. However, when the input becomes high, the fall time of the output is highly dependent on the strength of the current source. In this case, the nMOS transistor of the CCI is on and the current source defines the discharge time of the total output capacitance (parasitic capacitors plus gate-source capacitor) of the CCI unit. Voltages V7 and V8 are complementary thanks to the operation of the latch. Assuming voltage V8 is high and voltage V7 is low, then, voltages V1 and V5 are set to a high level and transistors N1 and P1 form a classical inverter. As a result, voltage V3 rapidly drops to a low level and pull-up transistor P4 is turned off. On the opposite end of the circuit, voltage V8 is high, voltage V6 is quickly set to low, and transistor N2 is turned off. During this time, the nMOS transistor of CCI2 is turned on and steers the current I to be able to discharge the total capacitance at node V2. In this case, transistor N2 is off and transistor P2 operates in the subthreshold region with a high trans-conductance gain. Therefore, the total capacitance at V4 is charged by the current source I. Voltage V10 becomes low when voltage V4 approaches the nMOS threshold voltage Vtn. Thus, transistor P3 is turned on and changes the state of the latch. This process alternately repeats and generates periodic pulses at the latch outputs. The frequency of the output pulse depends on the current provided by the current source.
3.3. Deriving an equation for the oscillation frequency of the proposed in-pixel light to frequency converter Figure 4 shows the circuit schematic of the proposed pixel-level LFC where the photodiode PD was previously represented by the current source I in Fig. 3. The circuit consists of four inverters (INV1 to INV4) to reduce the power dissipation, the latch circuit (the INV5 and INV6 pair), which controls the switches to generate the output pulses, and ten transistor switches (P1 to P6 and N1 to N4). Transistors N3 and P5 form CCI1, and transistors N4 and P6 form CCI2 of Fig. 3. The LFC output signal is voltage Vout which is connected to the clock input of the counter/shift register. Transistor N5 and the Start signal determine the exposure time of the pixel. The circuit of Fig. 4 operates based on what was explained above. The image capture begins when the Start signal goes from high to low. Inverters INV3 and INV4 amplifies the slowly-rising voltages V3 and V4 into sharper pulses to decrease the duration of short-circuit currents that flow in the path through the pMOS pull-up transistors and the nMOS latch transistors. Additionally, inverters INV1 and INV2 turn off the pull-down transistor N1 or N2 hen node V3 or V4 is charged. As a result, transistors N1 and P1 (or N2 and P2) are not turned on simultaneously. Therefore, these four extra inverters together eliminate the short-circuit currents, which decreases the power consumption. Moreover, with ultra-low photo diode currents, IPD, the charging procedure of nodes V3 and V4 mainly depends on the mentioned short-circuit currents flowing through transistors N1-P1 and N2-P2, respectively. This could make the conversion process almost independent of the IPD. However, in our proposed structure, by suppressing the short-circuit currents, it is assured that even for ultra-low photocurrent values, the dominant current of the circuit is the charge current injected by transistors P 1 or P2. This keeps the process still dependent on the photocurrent to a large extent. The proposed LFC can therefore detect and convert also ultra-low photocurrent values which leads to a considerably high dynamic range. The period of the output pulse is determined by the total time required to discharge the capacitances at nodes V1 (mode 1) and V2 (mode 2). Each one of these discharging modes defines one of the two bistable states of the latch. In order to extract the mathematics behind the LFC operation, the circuit is considered in mode 1 (the same holds for mode 2 and will be used later). The operational parts of the circuit in mode 1 are highlighted in Fig. 4. In mode 2, the other parts of the circuit are operational. The corresponding discharge time of the two modes is similar, so the calculated time is simply doubled to obtain the total time required. The capacitance at node V1 is discharged until pull-up transistor P4 is turned on, changing the state of the latch. Therefore, T1, the discharging time in mode 1, can be calculated as follows:
I PD C 1
dV 1 , dt
where IPD is the photocurrent and C1 is the total capacitance seen at node V1. To maintain a simple approximation, we have assumed a linear characteristics for C1. This is an assumption that is not exactly true, though we will show that the simulation and measurement results comply fairly well with each other and thus are accurate enough for our purpose. According to (1), voltage V1 can be calculated as:
V DD V 1
I PD t , C1
(2)
such that we at time T1 have:
V DD V tog
I PDT1 , C1
where Vtog is the voltage of node V1 at which the state of the latch toggles. Since transistor P1 practically operates in the subthreshold region, the V DD V tog is typically lower than the transistor threshold voltage. In the subthreshold region, the source-drain current of transistor P1 can be calculated as [25]: V SG 1 V tp nV T
W I SD 1 I 0 e L 1
V 1 e V
SD 1 T
,
where I0 is a technology-dependent scaling parameter, Vtp is the pMOS threshold voltage, n is the subthreshold gate coupling coefficient, VT is the thermal voltage, and W and L are the channel width and length of transistor P1, respectively. Since the source-drain voltage is much higher than the thermal voltage, (4) can be approximately rewritten as: V SG 1 V tp nV T
W I SD 1 I 0 e L 1
,
where VSG1=VDD – V1. Therefore, according to (2) we have: I PD t C 1 V tp nC 1V T
W I SD 1 I 0 e L 1
.
(6)
The charging process building up the voltage V3 can be modeled as (once again assuming a linear capacitance):
I SD 1 C 3
dV 3 , dt
where C3 is the total capacitance at V3. Node V3 must be charged from 0 to Vtn before it can change the state of the latch. Integration of (7) over the mentioned voltage range gives:
V tn
0
C 3dV 3 I SD 1dt . T1
0
Replacing ISD1 from (6) in (8) yields: V I PDC 3V tn L1 nV nC 1V T T1 ln 1 e nC 1V T I 0W 1 I PD
tp T
.
Assuming a 50% duty cycle, we can calculate the output pulse frequency as:
f
1 f 2T1
I PD V I CV L 2nC 1V T ln 1 PD 3 tn 1 e nV nC 1V T I 0W 1
tp T
.
According to (10), the pulse frequency is highly sensitive to the photocurrent since capacitance C1 is very small. It should be noted that the output pulse frequency is much higher than that of the conventional, reported in-pixel ADCs [1424]. The output pulse frequency of prior work is inversely related to the photodiode capacitance (which is normally large), while in the proposed LFC, the output pulse frequency is inversely proportional to the transistor capacitances (parasitics plus the effective gate-source capacitance). Moreover, the frequency is independent of the supply voltage and external signals. This feature is very remarkable for high-resolution image sensors where variations in the supply voltage of distant pixels are very likely to be high. Figure 5(a) shows the calculated output pulse frequency versus the photocurrent based on (10) for a typical design condition. As is evident, the simulated curve shows a relatively linear characteristic. The dashed line shows the ideal, linear characteristics and the deviation from this line can be exp e ed b he e m “in eg al nonlinea i ” (IN ) which is also plotted in Fig. 5(b). The maximum INL (0.066 GHz in this example) indicates the effective resolution for image capturing. It is worth mentioning that for various design conditions, i.e., different capacitance values and transistor aspect ratios, the frequency of the output pulse has nearly the same transfer characteristics. The same condition holds for different process parameters such as the threshold voltage and I0 in (10). 3.4. The counter/shift register block structure The counter/shift register block is designed using a linear-feedback shift register structure to attain an area-efficient DPS. An LFSR is normally realized using an array of shift registers in which the input bit is driven by an XNOR function taking some of the bits in the array chain. The LFSRs offer a simple structure and can be implemented with a compact and regular layout. The circuit can operate as a counter or as a shift register. As a counter, it does not count in a binary sequence format, so an offline decoder must be used to obtain valid image information. Figure 6 shows the 10-bit LFSR in a so called Fibonacci configuration. The LFSR generates pseudorandom sequences when it acts as a counter during the defined exposure time, Tcnt. After exposure time, the configuration of the circuit changes to a shift register in order to read out the pixel information. Therefore, any additional read-out circuit is not really required during the read-out period.
4. VLSI implementation and simulation results In order to verify the functionality of the proposed DPS, it has been designed and implemented in a 180-nm CMOS technology. In this design, a conventional n+/p-substrate diode is used to implement the photodiode. Transistors P 5, P6, N3, and N4 are thick-oxide devices which reduces the relatively large subthreshold leakage current which further enables circuit to detect low-light illumination and also to widen the LFC dynamic range. Based on (10), only the capacitance C1 has a significant role on the frequency characteristics of the circuit; and variations of capacitance C3 have little impact on the output pulse frequency. Transistors P1 and P2 are designed with dimensions greater than the minimum size to decrease the mismatch effect of C1. However, the sensitivity of the output pulse frequency to the photocurrent is decreased when increasing capacitance C1. All the remaining transistors of the circuit are designed with minimum-size devices, except for P3 and P4. The layout of a complete DPS is shown in Fig. 7. The circuit occupies an area of 23×23 µm2 and achieves a fill factor of 33.5%.
Capacitances C1 and C3 are considerably affected during layout: wire routing and boundary effects during physical implementation of the circuit add parasitic components to the capacitance. Discrepancies between theoretical and simulated results stem from the added parasitics and differences in the results between schematic-level and post-layout simulations show that the duty cycle deviates from the desired 50%, as evident in Fig. 8. For simulation purposes, the light intensity is modeled and simulated with a current source in parallel with the photodiode. Figure 8 illustrates the post-layout simulation results for a photocurrent of 1 nA and a supply voltage of 1 V. The output pulse frequency is 308.4 kHz. Figures from top to bottom at the left hand side show the voltages Start, V1, V2, and V3, respectively. The waveforms on the right hand side, from top to bottom, show nodes V4, V7, V8, and output Vout, respectively. The outputs from the complementary latch control the switches and steer the photocurrent alternately to discharge node V1 or V2 such that pulses can be generated at the output Vout. The output waveform has a good quality and the rise/fall times show little dependency on the switching period. The LFC output signal is a PFM signal with a frequency proportional to the photocurrent. The exposure time begins when the Start signal goes low. At this moment, the LFSR operates as a counter to count the LFC output pulses and determine the light intensity. During the exposure time, all pixels operate in parallel. After exposure time, the Start signal goes back to high and the LFSR acts as a shift register to read out digital values of the pixels stored in internal registers. In addition, during this time, the LFSR is initiated to
prepare for the next frame capture. In this scheme, no read-out circuit is needed and hence the area is fully dedicated to the photodetector array which increases the fill factor.
Figure 9 shows the LFC output pulses and the voltage across the photodiode as the photocurrent is changed. Waveforms from top to bottom correspond to photocurrent IPD, LFC output signal, and the voltage across the photodiode, respectively. As shown in the figure, the variation of the photodiode voltage is only some 30 mV when the photocurrent changes from 1 nA to 3 nA. Therefore, the voltage across the photodiode is almost constant during exposure time and the generated photocurrent just depends on the light intensity. In previous work [12-24], however, the voltage across the photodiode decreases with the exposure time. As a result, the dependency of the photocurrent on the reverse voltage across the photodiode causes distortion, to some extent, in the light conversion process. Figure 10(a) shows the output pulse frequency with respect to the photocurrent thus illustrating the theoretical, simulation, and post-layout simulation results. The discrepancies between theoretical and simulation results are due to the parasitic capacitance of the transistors connected to the nodes of V1 and V2. They were not considered in the estimation of C1 value in (10). The differences between schematic and post-layout simulation results arise from the routing parasitic capacitance. The simulation results for different supply voltages prove that the output pulse frequency has little dependency on the supply voltage. The proposed LFC detects and converts photocurrents in the range of femto- to microamperes so that the LFC can accommodate a very wide dynamic range. The effect of the process mismatch on the stability of the output pulse frequency is examined by performing a set of Monte-Carlo analyses using 500 outcomes. The results are shown in Fig. 10(b) for a nominal photocurrent of 1 nA. The circuit shows a 1-sigma variation of about 3.14% and has a mean value of 308.47 kHz.
5. Experimental results of a 16×16 array A test structure of a 16×16 array of the proposed DPS was implemented in a 180-nm CMOS technology such that we could investigate the pulse frequency response with respect to the light intensity. Figure 11 shows the microphotograph of the prototype chip. A single Start signal is used to control the timing, and no additional control circuitry is required. The chip is fully operational without any extra hardware. To evaluate the performance of the circuit, the power supply of the circuit is set to 1 V and an adjustable light source is employed. The pulse frequency of one sample LFC of the array was measured for different light intensity levels. Figure 12(a) shows the pulse frequency for seven decades of intensities. The measurements are done separately for each light intensity. In the figure, the lower limit is theoretically determined by the dark current. The maximum available intensity level used in our experimental setup could not bring the sensor to saturation and more than 142 dB operating range was achievable. The power consumption of one pixel under room light illumination and 1 V bias condition is 103 nW. In this condition, the frequency of the output pulse is about 330 kHz. According to the measured data of Fig. 12(a), the sensitivity of the output pulse frequency with respect to the light intensity is shown in Fig. 12(b). As can be seen, the proposed LFC is more sensitive to changes in the darker end of the luminance range compared to similar changes in brighter areas. The sensitivity at the lower end of the intensity is about 750 kHz/(mW/cm2) and is about 58 kHz/(mW/cm2) at the higher end. Therefore, the circuit is capable of discriminating the details in the dark areas while the resolution is high. This feature is essential for capturing details in shady parts of the scenes, and for producing a clear image. This nonlinear behavior is like the logarithmic APS characteristic that has a wide nonlinear dynamic range [26], so the proposed sensor can display clearly dark scenes too. The main drawback of the logarithmic APS is image lag at low luminance [26]. However, our proposed structure does not have any image lag when the light illumination changes and the response does not saturate in the high light illumination. In this nonlinear sensor, ten bits of resolution are sufficient to display over seven decades of luminance. However, to have the same accuracy using a linear sensor with 142 dB dynamic range, 24 bits would be required, which is not suitable for high-speed imaging, data transmission, and data storage in each pixel [27, 28].
Table 1 summarizes the performance of the presented digital pixel sensor and illustrates the comparison results between the proposed DPS and conventional DPSs. As can be seen, the proposed DPS compares very well against prior art. The dynamic range is increased to over 142 dB and the power consumption is reduced. Additionally, the sensitivity of the output pulse frequency to the light intensity is higher than that of typical DPS values. The measured fix-pattern noise of the array is approximately 3%. However, it can be further improved by storing the measured dark signal of each pixel as an initial value in the respective register. The fill factor of the proposed DPS is increased to 33.5% because of the compact LFC. In order to have a fair comparison with other reported structures, by considering the most important parameters of a DPS, the figure of merit (FOM) of the structures can be defined as:
Pdiss PP FOM DR 20log(FF ) 20log m 10log nW , 1 1
(11)
where DR is the measured dynamic range in dB, FF is the fill factor, PP is the pixel pitch in µm, and Pdiss is the DC power consumption of each pixel in nW. The area term is included in the FOM because the occupied area and fill factor of each pixel are critical parameters. The measured FOM for the proposed DPS is 138.75 dB at 1 V supply voltage. As can be seen, the proposed DPS has better performance compared to other structures. 6. Conclusion In this paper, a new pixel-level LFC based on a modified multi-vibrator structure with the aim of having a wide dynamic range image sensor with low power consumption, high sensitivity, and low area was proposed. In order to demonstrate the capability of the proposed LFC, a DPS array was designed and fabricated in a 180-nm CMOS technology. Experimental results illustrate that the dynamic range is over 142 dB, fill factor is about 33.5%, and the sensitivity of the output pulse frequency to the light intensity changes between 58 to 750 kHz/(mW/cm2) to capture a clear image from a high dynamic range scene. Therefore, building an imager with high-resolution and high frame-rate is feasible. Additionally, the circuit performance is independent of the supply voltage and external signals and the circuit is compatible with technology scaling. Moreover, in the proposed LFC, the voltage across the photodiode in the exposure time is practically constant so the distortion in the conversion of light intensity to digital signal is eliminated. These features comply with the underlying camera requirements.
Biographies Kourosh Hassanli was born in Shiraz, Iran, in 1977. He received the B.Sc. and M.Sc. degrees in electrical engineering from Shiraz University and Iran University of Science and Technology, in 2000 and 2002, respectively. He is currently working towards the Ph.D. degree in electrical engineering at Isfahan University of Technology (IUT). His interests include smart image sensor and low-power circuits design. Sayed Masoud Sayedi was born in Maragheh, Iran, in 1960. He received the B.Sc. and M.Sc. degrees in electrical engineering from Isfahan University of Technology (IUT), and the Ph.D. degree in electronics from Concordia University in 1986, 1988, and 1996, respectively. From 1988 to 1992, and then since 1997, he has been with IUT, where he is currently an associate professor in the Department of Electrical and Computer Engineering. His areas of interest include VLSI fabrication processes, low power VLSI circuits, and data converters. Rasoul Dehghani received the B.Sc., M.Sc. and PhD degrees all in electrical engineering from Sharif University of Technology, Tehran, Iran, in 1988, 1991 and 2004, respectively. From 1998 to 2004 he worked with Emad Co., Tehran, Iran, and then joined to Jaalaa Co., Kuala Lumpur, Malaysia, where worked as a senior IC design engineer. Since 2006, he has been Assistant Professor of electrical engineering at Isfahan University of Technology, I fahan I an. He i he au ho of ’De ign of CMO Ope a ional Amplifie ’ (A ech Hou e 2013). His current research interests include RF IC design for wireless communication, frequency synthesis, and low-voltage and low-power circuits. Armin Jalili was born in Behbahan, Iran, in 1982. He received the B.Sc., M.Sc., and PhD degrees in electrical engineering from Isfahan University of Technology (IUT), in 2004 and 2006, and 2012 , respectively. He is currently working as a researcher in Link Öping university. His interests include data converters, vision sensory applications, low power circuits and energy harvesting system design. J. Jacob Wikner received the M.Sc. and Ph.D. degrees from Linkoping University, in 1996 and 2001, respectively. He has been working at Ericsson Microelectronics, later Infineon Technologies, with high-speed data converters for telecommunication applications. From 2005 to 2009, he was with Sicon Semiconductor AB in Sweden developing AFEs for video applications. Since 2009, he is with the Department of Electrical Engineering at Linkoping University as an associate professor. His research interests include biologically inspired architectures, high-speed A/D and D/A converters, and mixed-signal design. He holds six patents, has published 40 scientific papers, and has co-au ho ed “CMO Da a Con e e fo Telecommunica ion”.
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Figure Captions VDD
VDD
Vrese t
Feedback
Vref
CPD
Vout
Write
Memory
Counter
Comparator Data bus
(a)
CPD Vref Comparator
(b)
Figure 1.Digital pixel sensor circuit architectures based on a) pulse-width-modulation scheme and b) pulse-frequencymodulation scheme.
Sel_Tcnt
IPD
Enable
LFC
Counter/shift register
Photodiode
Figure 2. Block diagram of the designed digital pixel sensor.
Digital readout
VDD
P3
P4
V10
V9 VDD
VDD
V1
P1
VDD
VDD
V7
Latch
CCI1
V8
V2
V3 INV3
N1
P2
CCI2
V4 V5
V6 INV1
I
INV4
N2
INV2
Figure 3. The block diagram of the proposed pixel-level light to frequency converter.
VDD P3 P4 P5
P6 INV5
V7
V1 V3
N3
V8
P1
P2
INV6
INV4
INV3
Vout
N1 INV1
Start
V2 V4
N2
N4
INV2
N5
PD
IPD
Figure 4. The circuit schematic diagram of the proposed light to frequency converter. The operational part of the circuit in mode 1 is highlighted and the light part indicates the off transistors during this mode.
0.07
Frequency vs. photocurrent based on equation (10) Ideal linear characteristic
Integral Nonlinearity (GHz)
Output Pulse Frequency (GHz)
3.5 3 2.5 2 1.5 1
0.06 0.05 0.04 0.03 0.02 0.01
0.5 2
4 6 Photocurrent, I PD (A)
8
10
0
2
4 6 Photocurrent, I PD (A)
8
10
(b) (a) Figure 5. a) The LFC output pulse frequency versus the photocurrent according to (10) in a typical design condition (solid curve) and the ideal linear characteristic (dashed line). b) The corresponding INL curve with respect to the photocurrent value.
Sel-Tcnt Y
1
Serial-In
0 MUX
Q7
Q10
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
clk
clk
clk
clk
clk
clk
clk
clk
clk
clk
clk
Figure 6. The 10-bit LFSR structure.
Pixel-out
10-bit LFSR
Control circuits Photodiode + (n /p-substrate)
Figure 7. The layout of the proposed DPS.
LFC
Figure 8. Post-layout simulation results of the pixel-level LFC for a photocurrent of 1 nA. Waveforms from top to bottom at the left hand side correspond to the Start signal, and nodes V1, V2, and V3. The waveforms at the right hand side from top to bottom correspond to nodes V4, V7, V8, and output Vout.
Figure 9. Simulation results of the in-pixel LFC when the photocurrent changes. Waveforms from top to bottom corresponding to photocurrent IPD, LFC output pulses, and the voltage across the photodiode over a time span.
10
10
10
10
4
60 Based on equation (10) Simulation results Post-layout simulation results
2
Number of iterations=500
50 =308.474 kHz Number of Iteration
Output Pulse-Frequency (MHz)
10
0
-2
30 20 10
-4
10
=9.70914 kHz
40
-4
10
-2
0
10 10 Photocurrent, I PD (nA)
(a)
2
10
4
0 260
280 300 320 340 Output Pulse Frequency (kHz)
360
(b)
Figure 10. a) The calculated output pulse frequency with respect to the photocurrent compare to the simulation and postlayout simulation results at 1.8 V supply voltage. b) The histogram of the pulse frequency of the proposed LFC for a Monte-Carlo analyses with 500 outcomes when the photocurrent is 1 nA.
A 16×16 DPS Array
Figure 11. Microphotograph of the 16×16 fabricated pixel array.
800
Sensitivity (kHz/(mW/cm2))
700
DR=142 dB
600 500 400 300 200 100 0 -4 10
10
-2
10
0
10
2
10
4
2
Light Intensity (mW/cm )
(a)
(b)
Figure 12. Pixel response as a function of light intensity. a) The sensor exhibits over 142 dB optical dynamic range. b) The sensitivity variation with respect to the light intensity.
Table Table 1. The prototype chip specifications and performance comparison between the proposed design and other works. Estimated numbers are indicated by (EST). Specifications
Bermak et al. [15]
Kleinfelder et al. [16]
Wang et al. [17]
Lai et al. [20]
Bermak et al. [21]
Shoushun et al. [24]
This work
CMOS technology
0. 25 µm
180 nm
180 nm
0.25 µm
0.35 µm
0.35 µm
180 nm
Technique
PFM
PWM
PFM
PFM
PWM
PFM
PFM
64×64
16×16
Resolution
32×32
352×288
28×28
640×480
Reconfigurable 32×64/64×64
Supply voltage (V)
2.5
1.8
1.2
1.2~2.5
3.3
3.3
1
Pixel pitch (µm)
45
9.4
23
9.4
50
50
23
ADC type
In-pixel
In-pixel
In-pixel
In-column
In-pixel
In-pixel
In-pixel
Fill factor (%)
23
15
25
24
20
20
33.5
Photo detector type
n+/p-sub
nMOS photogate
n+/p-sub
n+/p-sub
N/A
n+/p-sub
n+/p-sub
Optical Dynamic range (dB)
Programmable
N/A
130
76
90
>90
>142
Power consumption/ pixel
80 µW (EST)
400 nW (EST)
250 nW
11~81 µW
4500 nW (EST)
2000 nW
103 nW
Sensitivity
N/A
N/A
kHz/(mW/cm2)
N/A
N/A
kHz/(mW/cm2)
kHz/(mW/cm2)
FPN (%)
N/A
0.027
5
1.6
0.8
0.71
3
FOM (dB)
N/A
N/A
120.4
47.4
62.5
66.02
138.75
6.9
34 (EST)
58~750