A hybrid reader tranceiver design for industrial internet of things

Journal of Industrial Information Integration 2 (2016) 19–29

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Journal of Industrial Information Integration journal homepage: www.elsevier.com/locate/jii

A hybrid reader tranceiver design for industrial internet of things J. Mao b, Q. Zhou b, M.D. Sarmiento b, J. Chen b, P. Wang b, F. Jonsson b, L.D. Xu c,d,∗, L.R. Zheng a,b,∗, Z. Zou a,b,∗ a

State Key Laboratory of ASICs and Systems, Fudan University, 200433, Shanghai, China School of Information and Communication Technology, KTH Royal Institute of Technology Isafjordsgatan 22, 16440 Kista, Sweden c Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China d Old Dominion University, Norfolk, VA 23529, USA b

a r t i c l e

i n f o

Article history: Received 18 April 2016 Revised 9 May 2016 Accepted 10 May 2016 Available online 30 May 2016 Keywords:

Internet-of-Things Industrial integration Wireless sensor network Impulse radio Ultra-wideband Transceiver architecture

a b s t r a c t This paper presents an integrated asymmetric UHF/UWB reader transceiver in 90 nm CMOS technology for industrial enterprise IoT applications. The reader uses UHF transmitter to power up and inventory the tags. Instead of backscattering, tag replies the reader using Ultra-wideband (UWB) pulses, allowing high throughput transmission and precise positioning. Therefore, a UWB receiver is deployed in the proposed reader for data reception and Time-of-Arrival (ToA) estimation using energy detection schemes. The transmitter delivers 160 kb/s ASK modulated data by an integrated modulator and a Digital Controlled Oscillator (DCO). The DCO has 11% tuning range ability to cover different UHF signal channels. On the UWB receiver side, the 3–5 GHz energy detection receiver supports maximum 33 Mb/s data rate in both OOK and PPM modulations. The receiver front-end provides 59 dB voltage gain and 8.5 dB noise figure (NF). Measurement results shows that the receiver achieves an input sensitivity of -79 dBm at 10 Mb/s, and the power consumption of transceiver is 21.5 mW. © 2016 Elsevier Inc. All rights reserved.

1. Introduction Radio frequency Identification (RFID) technology play important role in the industrial enterprise Internet-of-Things (IoTs) applications, such as intelligence logistic, system control, inventory management, machines-to-machines (M2M) communication, and human-to-machines interaction [1–3,31–33]. The related commercial market of RFID systems has been increased to 9.5 billion US dollars in the end of 2015, and will keep 10% increasing rate annually in the further years. According to IDTechEx, the market size will exceed 15 billion US dollars [4]. In the context of the industrial enterprise IoT, all objectives such as tools, materials, machines and people are networked by radio links with not only sensing, processing, communication and control capabilities, but also location information [5–8]. In order to satisfy these requirements, the future RFID systems are expected to provide both reliable identification and high-precision positioning with low power, low cost and low latency. Unfortunately, current passive RFID systems, such as UHF RFIDs can only achieve meters level positioning accuracy within 10 m range. On the other hand, ∗

Corresponding authors. E-mail addresses: [email protected] (Z. Zou), [email protected] (L.R. Zheng), [email protected] (L.D. Xu). http://dx.doi.org/10.1016/j.jii.2016.05.001 2452-414X/© 2016 Elsevier Inc. All rights reserved.

active RFID systems using fully Ultra-wideband (UWB) radio (e.g., Ubisense system) can provide efficient performance, but at the expense of system complexity and high cost (the system consists of 4 readers and 6 tags and cost 1400 US dollars). To address these problems, an UHF/UWB hybrid system has been proposed. It uses conventional UHF signal to power up and inventory the tag, while the tag responds the reader using an active UWB transmitter. Such solution allows UWB transmissions in a passive RFID system [9]. Based on this architecture, a remotepowered RFID tag with 10Mb/s UWB uplink and -18.5 dBm sensitivity UHF downlink has been developed [10]. Still, an UHF/UWB reader is to be developed to pair the tag. In this work, an asymmetric UHF/UWB reader transceiver is designed and implemented. It contains a UHF transmitter and an energy detection (ED) IR-UWB receiver. The UHF transmitter with 160 kb/s data rate is implemented by using Amplitude-Shift-Keying (ASK) modulation. The IR-UWB receiver supports On-Off-Keying (OOK) and Pulse Position modulation (PPM) with data rate up to 33 Mb/s. The transceiver is fabricated in 90 nm CMOS technology. The chip area is 1.72 mm2 with power consumption of 21.5 mW. In the entire signal band from 3–5 GHz, the front-end of the receiver exhibits a noise figure of 8.5 dB and S11<−9.6 dB is measured. Providing 59 dB voltage gain, the receiver achieves an input sensitivity of −79 dBm with 10−3 BER at 10 Mb/s data rate.

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Fig. 1. Asymmetric UHF/UWB wireless link architecture for RFID and WSN.

The paper is organized as follows. Section 2 describes the system characteristics, proposed link architecture and reader operation principles. Circuit-level transceiver architecture and critical blocks of the prototype are explained and analyzed in Section 3. Section 4 summarizes the experimental measurement results which includes the link test with asymmetric RFID tag. Finally, conclusion is given in Section 5. 2. UHF/UWB hybrid RFID 2.1. System characteristic of passive RFID Different from peer to peer network, the tag-based passive RFID system exhibits a number of inherent features which should be considered in the system level. First, compared with the number of the reader, large amounts of tags are deployed in a reading zone simultaneously. As a consequence, a large system capacity is needed in the massive tags environment. Second, traffic loads between the uplink and downlink are also lopsided. In the downlink, the reader only needs to send and broadcast small amount of data to tags (e.g., synchronization, control command). But, in the uplink, large loaded sensor data on tags should be transmitted back to the reader. If considering the multi-access conditions, even higher communication data rate (tens of Mb/s) is required. Finally, on the hardware perspective, the tags are strictly constrained by cost and power. Thus, tags have very limited resource such as power supply, memory, computational ability and circuitry complexity, while a reader can be a more powerful device. 2.2. Asymmetric UHF/UWB wireless link The tag-based passive RFID system shows asymmetric characteristic in terms of the system capacity, the traffic load and the hardware complexity. On the other hand, IR-UWB also exhibits an asymmetry: the receiver needs relatively complex hardware implementation, but the transmitter can be extremely low power and low complexity. On the bias of the consideration above, we have proposed an asymmetric UHF/UWB wireless link architecture illustrated in Fig. 1 [9]. Instead of full-UWB or full-UHF wireless link, IR-UWB is introduced for uplink communication from reader to tags, while conventional UHF is applied to power up and correspond the tags for downlink communication. In the downlink, the reader powers-up the tags using UHF continuous wave (CW) signal. This signal can be also used as a

carrier to send commands and clock to the tags, as conventional passive UHF RFIDs. Since the communication is dominated by the uplink, there is no need to apply a high data rate UWB in downlink. Moreover, due to the regulatory constraints, the UWB is aggressively duty-cycled with less than 0 dBm power radiated [11]. It is infeasible to remotely power up the tag at significant distance. Besides, the power consumption and complexity of UWB receiver is too high to implement in passive tags. As a result, a low data rate narrowband radio like UHF is preferred for the downlink communication. In the uplink, the IR-UWB transmitter uses the scavenged energy to send data for a short time at high data rate. Compared with backscattering UHF RFIDs, ultra-short UWB pulses provide a higher positioning accuracy and wider signal band with high throughput. Baseband-like architecture and low duty-cycled signal promises extremely low power and low complexity transmitter, allowing UWB transmissions in a passive RFID systems. By adapting this approach, tags take full benefits of the UWB technology avoiding complex UWB receiver, but shifts the burden to the reader side, which will be addressed in next section. Table 1 summarizes the characteristic of UHF downlink and UWB uplink. 3. Reader design The primary task of an RFID reader is to perform identification and positioning, including energy transmission, command dispatch and data reception. As shown in Fig. 2, the asymmetric reader transceiver consists of an UHF transmitter and an IR-UWB receiver. The UHF transmitter includes a fractional-N frequency synthesizer and a modulator which mix the baseband signal to the carrier frequency. The IR-UWB receiver is implemented using energy detectors (ED) for low power and low complexity. Following are some design considerations for the UHF/UWB hybrid reader. 3.1. UHF energy and data transmission The reader radiates RF energy to power up tags for data receiving and responding. The operation distance usually depends on the energy link, which is limited by reader output power and tags sensitivity. A tunable external power amplifier is preferred to provide flexible and reconfigurable solutions for different standards [12]. For example, 4 W Equivalent Isotropic Radiated Power (EIRP) is allowed to be transmitted in North America regulations, hence the

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Table 1 Characteristics of UHF downlink and UWB uplink. UHF downlink

UWB uplink

• • • • •

• • • • •

Low data rate Continuous wave signaling (clock) Wireless power transfer Simple signal processing and synchronization Simplified receiver

High data rate Duty-cycled pulse wave signaling Ranging and Positioning Capability Low power and low complexity transmitter Complicated synchronization

Fig. 2. Block diagram of proposed asymmetric IR-UWB/UHF transceiver.

operating range can be calculated using Friis free-space formula:



d=

EIRP · Ga Pa



λ



4π

(1)

where Pa is the minimum threshold power to power up the tag, Ga the receiving antenna gain (i.e. 0 dBi) and λ is the wave length. Considering that the state of the art of tags sensitivity is as low as −15 dBm, the maximum operating range of the downlink can be estimated to be over 10 m [10,13]. Besides the energy, downlink data is also provided from the reader by UHF signals using ASK modulation. Binary data are encoded as pulse width modulation, namely pulse interval encoding (PIE). Time intervals of high amplitude pulse is chosen 3.125 μs and 9.375 μs to represent bit “0” and bit “1”, respectively. Fig. 3 (bottom) illustrates the modulation and data encoding parameters for the downlink. 3.2. Transmitter leakage One of the main challenges in conventional UHF RFID reader is to handle large transmitting power leakage during tag reception (self-jammer), which may saturate the UHF receiver and block the backscattered signal [14,15]. In our proposed UHF/UWB reader, the communication between the reader and tags are no longer half duplex, since the tags do not respond by backscattering the readers CW. Separated UHF transmitting and UWB receiving signal band naturally prevent transmission leakage into the receiver chain, without any additional directional coupler. Due to the different signal band, the receiver sensitivity will also not be affected by the transmitter noise and local oscillator (LO) phase noise leakage. 3.3. UWB Receiver for data reception As illustrated in Fig. 2, an UWB receiver is deployed for the uplink to receive pulses from the UHF/UWB tag. It consists of a front-end amplifier and a two-interleaved-channel baseband. The front-end amplifier provides significant gain to increase the swing

of received signal and to compress the noise. The two-interleavedchannel baseband architecture is composed by a squarer and two-channel windowed integrator bank to accumulate the signal energy within specific time windows. Non-coherent energy detection scheme is preferred for its low power and low complexity implementation. Avoiding RF correlation, the ED non-coherent receiver simply collect the signal energy and sample it by a symbol rate ADC. Such scheme relaxes high speed Nyquist ADC and eliminates the precise synchronization requirement. Relaxed synchronization and estimation thus reduces the transmission overheads, improving the system energy efficiency. The uplink transmission distance is determined by the UWB transmitter power and receiver sensitivity. Considering a balanced distance for both downlink and uplink, 10 m is targeted, as the downlink power-up distance is more than 10 m. The maximum transmit power Ptx for 3–5 GHz UWB is limited to −8.3 dBm, due to the FCC regulations. The channel noise Pn in the pulse bandwidth is −81 dBm. Based on IEEE 802.15.4a channel model, the path loss (PL) under residential line-of-sight (LOS) is estimated to be 61 dB at 10 m distance [17]. Given a bit error rate (BER) requirement of 10−3 , the required SNR of system using OOK modulation is derived to be −10.5 dB for a data rate of 10Mbps [16]. According to the assumptions above, the link budget can be calculated as follows:

LM + NF + IL = Ptx + P L − Pn − SNR = 22.2 dB

(2)

As a result, the link margin LM is left to be 12.2 dB if the UWB receiver noise figure NF and implementation loss IL can be as high as 10 dB. This ensures the maximum operation distance will not suffer from the large uplink data rate, which limits the transmitted pulse energy and leads to degradation of the SNR. 3.4. Timing issue and ToA estimation Conventional passive UHF RFID usually use ring oscillator for tag clock generation. However, UWB transmitter requires precise

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four sources of noise: the source resistor RS which is the first term in Eq. (3); the thermal noise from the input transistor M1 which is depicted by the second term; the noise generated from the current source Mb1 which corresponds to the third term; and the noise of the serial parasitic resistor of the load which is presented in the last term.

F =1+

Fig. 3. Reader to tag signaling (Bottom) and tag to reader signaling (Top).

high frequency clock to generate the pulse. Due to large variation across the process, temperature and voltage, ring oscillator based clock inevitability causes clock drift, which make the uplink synchronization more complex and time consuming. Aiming to fast synchronize the UWB pulses, same LO is applied for signal transmitting and receiving in this design. On one hand, a digital controlled pulse wave oscillator is designed as a LO for UHF transmitting. It also provides specific phased and duty cycled time window for UWB receiving, based on prescaler and programmable timing circuit. On the other hand, through the UHF link, the local oscillator can also be employed for UWB transmitting. As illustrated in Fig. 3, both UHF data envelop and CW carrier, provided by the local oscillator, is utilized for the tag clocking. The low frequency clock, captured from envelop detector, is used for baseband control. The high frequency clock, extracted from the UHF carrier by harmonic injection-locked frequency divider (HILD), is used for UWB pulse generator. Consequently, all the timing signal and clock are manipulated from one local oscillator, promising fast acquisition and synchronization. In addition to demodulating the tags response, time of arrival (TOA) estimation is also considered in the reader design to enable the tag localization. In this work, an energy detection based ToA estimator is implemented with IR-UWB ED receiver [18,19]. As key enablers for TOA estimation, a timing circuit and a high speed digital block are integrated for generating the required integration windows. The high speed digital block coarse tunes the window phase and length while the timing circuit yields the fine tuning trigger clock. Referenced from the UHF carrier, the integration window can be provided with 1.1 ns phase resolution. So, combined with flexible back-end, the IR-UWB ED receiver is compatible with different TOA estimation algorithms, such as Max energy selection (MES), normalized threshold comparison (TC), and MES-searchback (MES-SB), potentially ensuring sub-meter ranging accuracy. 4. Circuit implementation 4.1. Front-end amplifier The frond-end amplifier consists of a Low Noise Amplifier (LNA) and a series-connected Variable Gain Amplifier (VGA). As the first block in the UWB receiver chain, the noise performance of the LNA dominates the overall performance of the receiver. The wideband LNA (Fig. 4(a)) in this work consists of a capacitive cross-coupled gm-boosting common gate stage. It gives the area-efficient design by using Mb1 and Mb2 as the current sources instead of the highQ source inductor, and stack inductor as the load to replace the shunt peaking load. The NF is expressed in Eq. (3), where there are

γ1

2 α × 2 gm1 RS

+ γb1 gmb1 Rs +



RS RL 1 1+ 2 gm1 RS ZL2

2

(3)

In Eq. (3), α and γ are bias-dependent parameters [20]; ZL is the load impedance and RS is the source resistor which 2gm1 × RS = 1; RL is the serial parasitic resistor of the load. Assuming γ1 = γb1 = γ , input transistor M1 as the main noise source decreases the noise by 2. If gmb1 is chosen to be one third of gm1 ; and the last term in Eq. (3) is neglected due to RS RL = ZL2 , we get the optimum NF in Eq. (3) by differentiating Eq. (4). It is clear that CG-LNA can realize NF as low as the common source LNA.

Fmin

√ 3 =1+ γ 3



1 gm1 RS = 2

when

  3 4

(4)

Bonding wire and dual-diode ESD protection are considered for the complete input matching network. As a trade-off between return loss and the protected voltage of human body mode (HBM), finger length of each diode is 30 μm, and two fingers are used in parallel with the width 1 μm for each diode. The post-layout simulation results in Fig. 5 displays a NFmin of 3.1 dB and voltage gain >15 dB in our target band with 1.3 mW power consumption. For further increasing the swing of the signal, a wideband VGA following the LNA is provided. The VGA is composed by four identical cascaded amplifiers illustrated inFig. 4(b), where the gain is controlled by modifying the operation of the transconductance of M1-M4. It provides a voltage gain ranging from −10 dB and 44 dB with a good linearity. Increasing the control voltage increases the bias current of M2-M3, which reduces the transconductance of M1-M4. But the bias current of M5-M6 is unchanged. With this method, the input impedance can be kept constant and the amplification band can be also preserved from the gain variations. Since the DC offset is produced in a differential pair circuit, the input of each stage is AC coupled to avoid offset-voltages amplification. Therefore, the extra DC biasing is needed to keep proper DC voltage that will increase the complexity of band-gap reference circuit. A 4 bits logarithmic Digital to Analog Converter (DAC) is designed to provide 16 steps of linear gains from −2.5 dB to 11 dB in each stage. Simulations show that the VGA has a −3 dB bandwidth of 1.7 GHz centered at 3.9 GHz. The 1 dB compression point is −52 dBm and −18 dBm with maximum and minimum gain respectively. Fig. 6 shows the single stage VGA response with different control voltages. 4.2. Squarer The role of the squarer is to self-mix the received RF signal to baseband and square the signal amplitude. Passive squarer may be a low power solution since no dc bias current is consumed in the circuit [21]. However, the passive squarer cannot provide high conversion gain for further signal integration. In this work, a four quadrant active multiplier is employed as the square law device as shown in Fig. 7(a) [22]. The transconductor multiplier structure contains four cross coupled current branches. In each branch, two pipelined transistors are biased to the different region. M1-M4 operate in the triode region while M5-M8 operate in saturation region with proper dc bias voltage X. The drain current flowing through each branch can be expressed as



Ii = k X + x − Vth −



Vdsi Vdsi 2

(5)

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Fig. 4. (a) Schematic of LNA and (b) Schematic of single stage of VGA.

Fig. 5. Voltage gain, NF and S11 simulation of LNA with different bonding wire length, LB represents the inductance of bonding wire. Fig. 6. Voltage gain simulation of VGA, V_Control represents the digital code for gain controlling.

where k = μCoxW/2L is the transconductance parameter, Vth is the threshold voltage, x is the ac input signal and Vdsi is drain source voltage of M1-M4. If the transconductance of upper transistors (M5-M8) is much larger than lower transistors (M1-M4), then the upper transistors behave as a source follower and Vds of lower transistors are controlled by the gate voltage of M1-M4. Thus, the output current Io1 and Io2 can be written as

Io1 = I1 + I3 = k(X − Vth_sat )(X − 2Vth + Vth_sat ) + kx2

(6)

Io2 = I2 + I4 = k(X − Vth_sat )(X − 2Vth + Vth_sat ) − 3kx2

(7)

The difference of (6) and (7) yields the required output current. Assuming all transistors are matched, the output voltage of the squarer is

Vo = −RL (Io1 − Io2 ) = −4kRL x2

(8)

Since the output signal Vo has a wide bandwidth from dc to 2 GHz, the high frequency effect of output node must be taken into account. To calculate the output bandwidth, we can obtain an expression for Vo /Io at output node in terms of ideal current source and simplified small signal model. Note that the ideal current source is modeled for the transconductor and the capacitances associated with the devices are considered in the small signal model.

As shown in Fig. 7(b), the transfer function can be written as

Vo (s ) = io ( s )

C1C2 RL rds 2 s 1+gm rds

RL 2 + (1+gm rds )C1 RL + (rds +RL )C1+ s+1 gm r

(9)

ds

Where C1 and C2 represent the total parasitic capacitors at drain node and source node, respectively. Using the dominant pole approximation, the dominant pole ωp1 is estimated to be

ω p1 =

1 + gm rds

(rds + RL )C2 + (1 + gm rds )C1 RL

(10)

Taking a closer look at the behavior of the ωp1 with regards to the dimensions of upper transistors (M5-M8), it illustrates that gm ∝ID ∝W and C1 , C2 ∝W while rds ∝1/(ID )∝1/W. gm and rds cancel each other which make numerator of the transfer function (10) being independent of the W. At the denominator part, all terms are proportional to W expect C2 rds , gm rds and RL . Therefore, ωp1 is inversely proportional to the width of the upper transistors (W5, 6, 7, 8 ). Decreasing the width of the upper transistors can effectively improve the output bandwidth. But, on the other side, the W/L ratio of the upper transistors (the source followers) also influences the linearity of the squarer. Higher linearity requires the source follower using larger W/L ratio [22]. Considering this tradeoff, the dimensions of the upper transistors are firstly designed to

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Fig. 7. (a) Schematic of the squarer and (b) Simplified small signal at output node of the squarer.

Fig. 8. (a) Integrator and S/H capacitors. (b) Simplified schematic of Gm cell. (c) Timing sequence in interleaving mode.

satisfy the output bandwidth requirement and keep the Total Harmonic Distortion (THD) into a tolerated level, because the BER performance of receiver is more sensitive to squarers bandwidth than linearity based on the system level simulation. As a result, without any peaking inductors, ωp1 /2π exceed 2 GHz which reach the upper limit of the signal bandwidth. The THD is controlled to lower than 5% in the complete input range. The squarer occupies an area of 141 μm by 141 μm, and has a power consumption of 2.4 mW. 4.3. Integrator bank To collect signal energy for the demodulation, an integrator bank is designed as shown in Fig. 8(a). It is implemented with a Gm cell and a set of switches that controls the charging and discharging cycles to sample and hold the load capacitors. The Gm

cell injects a current to the S/H capacitor (Cint1 or Cint2) that is going to be proportional to the input voltage. In practical, nonideal integrator cannot hold the integrated signal precisely due to finite DC gain and finite unity bandwidth. In order to improve these non-idealities and the low power consuming constraint, the Gm Cell is implemented with a telescopic amplifier. By this topology, DC gain can be easily improved by biasing all transistors in the saturation region. The proposed amplifier is loaded with a cascode current source to increase the output impedance, and also decrease the leakage current when the S/H capacitor and the Gm Cell are connected. A programmable timing circuit controls the integration window, S/H cycles and reset cycles. To relax the sample and hold time for the bit settling in ADC, two branch S/H switches are operated in interleaving mode. In each integration phase, the window switches

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allel as an alternative current path. The Ctail attenuates high frequency noise from the tail and provides the extra current over the bias current Itail for M1 and M2 [25]. Since Ctail will absorb the parasitic capacitance at the node Vtail , a tail transistor with a large size can be used to further attenuate its flicker noise. Moreover, the power supply noise rejection can be also improved by connecting tail capacitor toVdd . Compared to the conventional LC-tank oscillator under the same bias condition, the pulse wave oscillator produces 2.2–3.9 dB higher oscillation amplitude and hence illustrates better phase noise performance. 5. Measurement results

Fig. 9. Schematic of digital controlled oscillator.

of one branch are closed for integrating, while the S/H switches of the other branch are closed for holding the integration value from previous phase. In this case, the S/H capacitor has almost one symbol period to hold the final integration value. When the holding phase is finished, a reset signal immediately discharges the S/H capacitor to the ground for next integration. In high data rate PPM modulation, two integrators can be driven separately by independent timing signals [19]. The baseband VGA (BBVGA) uses source follower to isolate the resistive feedback amplifier (the second stage of the BBVGA) and the integrator, avoiding the leakage of the signal on the integrating capacitor during sample/hold cycles. Because the maximum data rate is 33.3 Mb/s, the BBVGA is designed to have 3-dB bandwidth 40 MHz with four-step gain control. Each step gain variation is 5 dB and the maximum gain is 20 dB. 4.4. Digital control oscillator An on-chip Digital Controlled Oscillator (DCO) is the key block to generate the RF carrier signal for UHF Transmitter. In this work, a pulse-wave drain current LC oscillator is proposed as shown in Fig. 9 [23]. By the extra biasing circuit, DC voltage Vbias of M1 and M2 is set to be lower than Vdd in order to make the devices working in class C. From the simulation, it illustrates that drain current can be more close to a pulse wave by setting lower Vbias . However, the biasing voltage is also limited by the tail transistor. A low Vbias will decrease the drain-source voltage of tail transistor, reducing the tail current and resulting in small output swing. Thereby, the phase noise performance will be degraded. Besides, if Vbias is too low, it is inevitable for the tail transistor operating in deep triode region and the oscillator failing to start-up. Since Vbias is quite critical, it is suggested to use a voltage control loop to set the proper biasing voltage [24]. The biasing capacitor and resistor, Rbias and Cbias , are sized to be larger than the parasitic gate capacitance and the parasitic resistor of inductor L, respectively. This will minimize the loading effects on the LC-tank. To achieve better performance on phase noise and power consumption, tail current pulse shaping technique is applied in this design. A capacitor (Ctail ) is placed with the tail transistor in par-

The transceiver prototype has been fabricated in 90nm CMOS technology with 9 metal layers [23]. It occupies an area of 1800 μm × 900 μm with ESD protected pads. Besides the transceiver area, rest of the die is filled with test structures and I/O buffers. Timing circuitry and high speed baseband controller is also integrated in the prototype for the measurements, providing a wide range of programmability and configurability, such as data/pulse rate, gain controls, phase and length of the analog integration window, etc. The transceiver is packaged in a 32-lead package (QFN 32) and mounted on an FR4 PCB. The microphotograph of the chip is shown in Fig. 11. Fig. 10 and Fig. 12 show the overview of the measurement setup and test environment, respectively. The reader test board contains the transceiver front-end prototype and two 8-bit 40Mps ADCs [26]. A Field-Programmable Gate Array (FPGA) is utilized as an external back-end for baseband processing. It is able to configure and execute different algorithms, taking care of baseband signal generation, data reception, pulse/code level synchronization, and real-time-control, to accommodate different operation modes. In order to realize run-time configurability, a set of control signals in parallel are to be programmed by the FPGA back-end at maximum frequency 33 MHz (maximum pulse frequency). However, due to the limitation of IO numbers, a serial-in parallel-out (SIPO) high speed control interface is needed to update the backend control signals to ASIC. As a result, a 225 MHz with 8-bit synchronized data bus is connected between the FPGA and reader test board by the High Speed Mezzanine Card (HSMC), offering 48 bits real time control signals [27]. Moreover, another 85-bit SIPO registers are deployed for analog trimming and operation mode selection. All the high speed control signal paths are applied in ground layer to minimize the jitter and the skew. Considering that the analog and RF power supplies will suffer from the noisy digital power supply, parallel passive low pass filters were used to keep the stability of those sensitive power supplies. Time domain result of the UHF transmitter is illustrated in Fig. 13. Using an on-chip modulator, the ASK modulated data can be achieved up to 160 kb/s data rate. The measurement shows that the DCO can be fine-tuned from 830 MHz with 11% tuning range. As shown in Fig. 14, the measured phase noise is –100 dBc/Hz and –120 dBc/Hz at 40 kHz and 1 MHz offset, respectively. Operating in the low power mode, the DCO consumes less than 6 mW with 0.12 mm2 area. The input of UWB receiver is arranged close to the RF pad in order to minimize the input parasitic capacitance. The measured input return loss S11 is plotted in Fig. 15. In most cases, the S11 is lower than −10 dB inside the targeting band with the worst case of −9.6 dB at 3.27 GHz. The whole IR-UWB receiver frontend consumes 15.5 mW for the single channel OOK modulation and 21.5 mW for two channels. Although up to 59 dB voltage gain is offered in the front-end amplifier, 0.5 nJ/bit energy per bit can be achieved at 33 Mb/s data rate. Noise figure measurements are conducted by hot-cold method with the NC346B noise source connected to the Rhode–Schwarz FSQ26 spectrum analyzer. The

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Fig. 10. Measurement setup of the UHF/UWB reader transceiver.

Fig. 11. Die photograph of the UHF/UWB transciver front-end.

Fig. 12. UHF/UWB reader test environment.

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Fig. 13. Time domain waveform of UHF transmitter.

Table 2 Power consumption for individual blocks in transceiver.

Power consumption

LNA

1.5 mW

Wideband VGA Multiplier Integrator Baseband amplifier Digital control oscillator

8.0 mW 2.4 mW 3.1 mW 0.5 mW 6 mW

Fig. 14. Measured phase noise of the DCO.

Fig. 16. Mearsured receiver BER versus input signal power.

Fig. 15. S11 measurement of UWB receiver.

minimum NF of the front-end is 8.5 dB. The power consumption for each block is summarized in Table 2. In order to evaluating the BER performance, the IR-UWB receiver has been tested together with the asymmetric RFID tag [10], which includes an IR-UWB transmitter. As shown in Fig. 10, ran-

dom baseband data pattern as well as pulse control signal is generated from FPGA to tag, where the pulse bandwidth and power level can be easily adjusted. In this test, the IR-UWB signal at a pulse repetition frequency (PRF) of 10 MHz is modulated and transmitted to the reader. The spectrum analyzer shows that the transmitted pulse spectrum satisfies the FCC regulation. Fig. 16 presents the BER of receiver as a function of input received power. It illustrates that the proposed receiver has −79 dBm sensitivity at 10 Mb/s data rate if targeting the BER as 10−3 , corresponding to an operation distance over 10 m. The measured performance of the UWB receiver is summarized and compared with other works from the literature in Table 3. A normalized sensitivity metric is provided to compare the entire

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J. Mao et al. / Journal of Industrial Information Integration 2 (2016) 19–29 Table 3 Measured performance summary of the UWB receiver in comparison with other related works.

Technology Active area Power supply Modulation Bandwidth Max. data rate Energy/Bit Power consumption Normalized sensitivitya a b c d e

This work

[21]

[28]

[29]

[30]

[8]

90 nm 1.6˜mm2 1V OOK/PPM 2 GHz 33 Mb/s 0.5 nJ/bit 15.5 mWb −99 dBm

90 nm 2.25˜mm2 1.2 V OOK/PPM 500 MHz 16 Mb/s 1.4 nJ/bit 22.5 mW −98 dBm

90 nm 1.5˜mm2 1.25 V OOK 500 MHz 100 Mb/s N.A. 156 mW −80 dBm

180 nm 17.2˜mm2 1.8 V OOK/BPSK 2 GHz 20 Mb/s 5.3 nJ/bit 23.6 mWc −82 dBm

90 nm 0.96˜mm2 1V OOK/S-OOK 700 MHz 1 Mb/s 3.9 nJ/bit 3.9 mW −73 dBmd

65 nm 0.3˜mm2 1.2 V PPM 1.5 GHz 1 Mb/s 0.29 nJ/bit 3.6 mWe −62.5 dBm

The sensitivity is normalized at data rate of 100 kb/s. ADC and digital baseband is not included. Power consumption of LNA and squarer. Packet error rate is measured. Peak power consumption.

receiver performance fairly. As shown in the table, the proposed receiver achieves highest normalized sensitivity and second highest data rate while the energy per bit still can be kept at a relatively low level. 6. Conclusion UWB radio technology is a promising solution for the industrial IoTs to overcome most of limitations of the current narrowband RFID radio systems. In this work, we integrate the active UWB radio into conventional narrowband UHF system to obtain the abilities of large throughput, high ranging resolution and good interference robustness. Thanks to unique characteristic of asymmetric UWB/UHF system, advanced identification, sensing and localization applications become feasible in the industrial IoTs, such as s logistic, automotive, surveillance, and automation systems. To prove this concept, an integrated asymmetric UWB/UHF transceiver analog front-end for RFID reader in 90nm CMOS technology is presented. In the UHF transmitter, clock and data are modulated using ASK modulation with a data rate up to 160 kb/s. In the UWB receiver, a two-channel energy detection IR-UWB receiver is designed to be compliant with both OOK and PPM modulation. The energy efficiency is 0.5 nJ/bit at 33 Mb/s and the total noise figure is 8.5 dB. The measurement result demonstrates that the power consumption of the transceiver is 21.5 mW. The proposed UWB receiver sensitivity can be reached as −79 dBm with 10−3 BER at 10 Mb/s data rate. For the future work, we will focus on the backend design on the UWB receiver, because comparing to the conventional narrowband receiver, the UWB system require relatively complex synchronization and backend processing for data reception. Moreover, hardware integration and miniaturization is also a direction for the next step. Partly of the UWB radio building blocks can be shared for narrowband radio system. Acknowledgment This work was supported in part by the Swedish Research Council through VR program, and the NFSC (61571137)/SSTDF (14510711500)/JSSF (BK20150164) of China. References [1] L.D. Xu, W. He, S. Li, Internet of things in industries: a survey, in: IEEE Transactions on Industrial Informatics, 10, 2014, pp. 2233–2243. [2] F. Tao, Internet of things in product life-cycle energy management, J. Indus. Inf. Integrat. (2016). [3] Y.I.N. Yuehong, The internet of things in healthcare: an overview, J. Indus. Inf. Integrat. (2016). [4] Internet of Things (IoT), Business Opportunities, 2015, pp. 2015–2025.

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