A large system of Flash ADCs for a neutrino detector

542

Nuclear Instruments and Methods m Physics Research A300 (1991) 542-551 North-Holland

A large system of Flash ADCs for a neutrino detector M. Atiya 1 , C.Y. Chi, H. Cunitz, N . Kondakis 2, W. Lee, B. Rubin, R. Seto, W . Sippach, C. Stoughton 3 and G. Tzanakos 4 Physics Department, Columbia University, New York, NY 10027, USA

E. O'Brien', T. O'Halloran, K. Reardon 5 and S. Salman Physics Department, University of Illinois, Urbana, IL 61801, USA

B. Blumenfeld, L. Chichura, C.Y. Chien, J. Krizmanic, E. Lincke 6 , L. Lueking 3, W. Lyle, L. Madansky and A . Pevsner Department of Physics and Astronomy, The Johns Hopkins University, Baltimore, MD 21218, USA

Received 17 August 1990

A large system of 5760 Flash ADCs was used to instrument proportional drift tubes in a neutrino detector . The system uses a common clock source, is data driven, and builds the data stream in hardware. The design, construction, operation, and performance of this system is described.

1. Introduction The Flash analog-to-digital Converter (FADC) is a circuit that can sample and digitize a fast signal at a high frequency rate . If the sampling frequency is at least twice the highest frequency Fourier component in the signal, then the sampling theorem [1] guarantees that the resulting digital representation is sufficient to uniquely reproduce the original waveform. Digitizing a fast signal waveform offers several advantages over traditional methods of signal processing with TDCs and ADCs . It makes available to the experimenter the maximum possible waveform information. The drift time and pulse area information can be easily extracted from Present address: Brookhaven National Laboratory, Physics Department, Upton, NY 11973, USA . Present address: Princeton University, Physics Department, Princeton, NJ 08544, USA. Present address: Fermilab, Batavia, IL 60510, USA. Present address: University of Athens, Physics Department, Nuclear and Particle Physics Division, 15771 Athens, Greece. Present address: Hughes Aircraft Corporation, Los Angeles, CA 90024, USA. Present address: University of Rochester, Physics Department, Rochester, NY 14627, USA.

the digitized waveform . In addition, detailed pulse structure is extremely useful in particle identification, particularly in separating showers from muons and hadrons. The use of FADCs on a large scale m high energy physics experiments was pioneered by the UAI experiment, which used FADCs to instrument the imaging drift chambers [2]. Since then several groups have reported the utilization of FADCs to instrument drift chambers [3] for the OPAL detector at LEP and the ZEUS detector at HERA, the vertex time projection chamber (VTPC) of the CDF [4], and the DELPHI detector EM calorimeter [5]. In addition, FADCs have been used for e/ir separation with transition radiation detectors [6], and for pulse shape discrimination in nuclear physics [7]. In this work we describe a large system of FADCs designed to digitize signals from proportional drift tubes (PDT). These PDTs were used to instrument the E776 neutrino detector at BNL, shown in fig. 1, designed to search for neutrino oscillations [8]. The PDTs were made of aluminum extrusion, four PDTs per extrusion, operated with a 80/20 argonethane mixture. The sense wire, 50 l.Lm in diameter, was held at 2250 V. The signal preamplifiers were mounted on the chamber in groups of four per card . Each preamplifier produces a pair of symmetric signals driving a

0168-9002/91/$03 .50 © 1991 - Elsevier Science Publishers B.V . (North-Holland)

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2. System overview The organization of the FADC system is shown schematically in fig . 4 . The system was designed with three key characteristics : to use a central clock source, to be data driven, and to have the necessary hardware to build the data stream without computer intervention . The system is hierarchically organized into modules and crates . A module has 8 FADC channels . A crate contains 32 modules, serving 4 PDT planes (256 wires) . In addition, each crate uses one module for data compression and readout (Data Link), and one module for control (Control Link) . The computer sends control information to the Control Link and reads out data from the Data Link . Fig . 5 shows a photograph of an FADC crate, showing the backplane bus, the Data Link, the Control Link, and one FADC module . The recording devices (FADCs) digitize the analog input pulses and store the digital information into local memories . The Data Link regroups this information, formats the data and transmits it to the computer, via the Nevis Transport Bus [9] . Computer commands are interpreted and executed by the Control Link . All Control Links and Data Links are daisy chained . The clock is generated by an external Trigger Source (fig. 4), and is distributed to all crates via the Control Link, which in turn distributes it to the FADC channels via the backplane bus in each crate . The overall system consists of 23 FADC crates . Each FADC crate was equipped with a 200 A, - 5 V do power supply . Four crates were

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Fig. 5. Photo of an FADC crate. Shown are the backplane bus, the Data Link, Control Link, and one FADC module

lines (DO-D5), 8 ADDRESS lines (AO-A7), SPAN and PEDESTAL lines, power, and ground reference. The READ/WRITE signal, generated by the Data Link, controls every recorder, and is always in read or write mode . The 8 address lines provide a 3-bit channel address and 5-bit module address. The lowest bit in the module address appears on the backplane bus, while the other four bits are set on the recorder module via a microswitch . The total system was implemented using ECL 10000 technology. Table 1 Layout of backplane bus for the FADC system Line number 1 2 3 4 5 6 7

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3. The Flash Recorder The Flash Recorder consists of four sections : the receiver amplifier, a fast sampling ADC, memory, and data control. The recorder receives differentially a 5 times amplified signal from the detector . The circuit schematic of the receiver is shown in fig. 6. The FADC circuit schematic is shown in fig. 7. When the WRITE clock is on, a 6-bit fast sampling ADC (Analog Devices AD6020KD) samples the amplifier output voltage pulse once every 22 .4 ns for a duration of 100 ps . The samples are then written to a 6 X 256 random access memory (Hitachi HM100422). The memory IC has 4 data and 8 address lines. Thus, each channel of flash recorder requires one and a half memory ICs. Two 4-bit address counters (Motorola 1OHO16) provide an 8-bit memory address. These counters are driven by the same clock that generates the memory READ/WRITE signals. The counter runs continuously and is reset to zero, on overflow, providing in this way the data addresses of the most recent 256 samples that correspond to a signal history of 256 X 22.4 ns = 5.7 lts. The span and pedestal of the ADC are in the range of 0-2 V and are set by the Control Link module via the SPAN and PEDESTAL lines in the backplane bus . During the experiment the span was set to 2 V and the

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pedestal to 0 V . Eight FADC channels are organized into a module card as shown in fig . 7 and also in the photo of fig. 8 .

4. The Data Link The function of the Data Link is twofold : i) to identify those recorder modules that contain nonzero data and ii) to perform zero data suppression, data formatting and readout . A schematic diagram is shown in fig . 9 . The Data Link is provided with an 8-bit address counter and an 8-bit time counter. The module is located at the one end of each crate (fig. 5), and receives the WRITE clock signal as well as a fanout from each recorder module through the backplane bus . When the WRITE clock stops, the Data Link switches to read mode . A 100 ns read clock signal is sent to each recorder module while the READ/WRITE line in the backplane bus is switched from write to read mode . To identify those recorder modules containing nonzero data, the Data Link, after having been switched into read mode by an external trigger, sends out 256 READ clocks to each recorder module . This enables the recorder modules to loop through their memory contents and find any nonzero data . A module with nonzero data will turn its MODULE TAG on . Later, when

the Data Link addresses this module, the TAG appears on the bus, signaling that it contains nonzero data. This method saves data processing time, since every PDT plane is read out by 8 flash recorders, and neutrino interactions in the detector usually deposit data in only one of the 8 modules . Now that the modules containing valid information have been identified, the Data Link starts another 256 step cycle to clock the time counter . After 256 clock signals, the time counter overflows and the OVERFLOW signal is used to clock the 8-bit address counter, which generates the FADC address . In this way, the Data Link addresses each channel and reads the 256 6-bit data in the memory of each channel . The data read into the Data Link module is tagged with counts from the time counter . Unless the READ-ALLDATA flag is set, the current recorder module, which has valid data, advances the address counter in the Data Link by 8 counts and resets the Data Link time counter. The second function of the Data Link is to compress and format the data before transmission to the computer . It forms the data stream corresponding to each FADC channel . The first word in the stream is an address word. This is signified by setting bit 14 on . Bits 13-8 give the crate address, bits 7-3 give the module address within the crate, and bits 2-0 give the FADC channel address . The crate address is set via a 6-bit DIP switch in the Data Link module . The rest of the words in the stream are packed data words, each containing the FADC memory contents (pulse height) in bits 13-6, and the time (time counter) in bits 5-0 . Bit 14 is set to 0 for all data words . If the Control Link has set the READ-ALL-DATA flag, then all data, including zeros, are packed and read out (this option is very useful in the debugging phase) . Otherwise, only the data above a preset 5-bit threshold are read out . The Data Links from different crates are daisy chained . The last Data Link in the daisy chain is the first to transmit data to the computer . When this Data Link is finished transmitting data, it signals the next one to begin transmission. The process continues until all data in the system is read out .

5. The Control Link The Control Link, shown in fig . 10, sets the running parameters in each crate . These are the PEDESTAL (labeled REF in fig. 7) and SPAN for the recorder modules, CRATE ON/OFF, READ-ALL-DATA, and TEST FLAG for the Data Link . The SPAN is set by a 6-bit DAC, and the PEDESTAL by a 10-bit DAC. Both span and pedestal are in the range 0-2 V, dc. An external pedestal can also be infected with a pulse generator ; a sine wave input was used as an external pedestal when testing the FADC modules. The CRATE ON/OFF command controls whether or not the Data

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Fig. 8. Photo showing the component arrangement in an 8-channel FADC card. Link is allowed to read the recorded ADC data . Setting the READ-ALL-DATA flag causes the Data Link to ignore the MODULE TAG, read the full contents of the memories and transmit them to the computer without zero suppression . To read a specified ADC channel of a certain module, the computer sends a command to the Control Link . This command contains an 8-bit module-channel address and a single bit to set the TEST FLAG . The 8-bit address is stored in a register in the Control Link and appears on the backplane address lines. When the Data Link senses the TEST FLAG to be on, it reads only the data of that channel. A 4-signal (8-wire) ribbon cable connects the Control Link with the Data Link at the front end. This cable carries the CRATE ON/OFF, TEST FLAG, and READ-ALL-DATA command signals. 6. Performance Prior to each run period the system was automatically checked by using a sinusoidal pulse as the input to each channel and examining the digitized output . The system performed remarkably well during the data acquisition periods of experiment 776 at BNL. The failure rate associated with the FADCs was less than one channel per week . The quality of the digitized

signals was monitored with cosmic ray muons during data taking on a channel-to-channel basis by keeping track of the maximum pulse height, pulse area, and pulse length . Figs . lla and l1b show the digitized waveforms corresponding to a muon and an electromagnetic shower . The muon pulse shows a single peak, in contrast to the electron pulse which has multiple peaks corresponding to several shower particles crossing the drift chamber. In fig. 12 we compare the digitized pulses from a muon track going through several planes with those of an electromagnetic shower . The striking differences between the digitized electron and muon pulses have been exploited in separating muons from electrons as was necessary in the neutrino oscillation experiment [8]. This reflects the power of the FADC system in separating showers from minimum ionizing particles as compared to older methods. Acknowledgements We would like to thank the staff of the Electronics Shop at Nevis Laboratories for their invaluable assistance in the construction of the FADC system . This work was supported in part by the National Science Foundation Grants PHY86-10898 and PHY86-19556, and by the U.S . Department of Energy under Contract No . DE-AC02-76ER01195.

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References [1] E.C . Jordan (ed.), Reference Data for Engineers Radio. Electronics, Computer, and Communications, 7th ed. (Sains, 1985) pp . 25-17 [2] M. Calvetti et al ., Nucl . Instr. and Meth . 176 (1980) 255, S. Centro et a] ., Nucl Instr. and Meth 224 (1984) 153. [3] P. Bock et al ., Nucl . Instr and Meth . A242 (1986) 237; D. Schaile et al ., Nucl . Instr and Meth . A242 (1986) 247; S.M . Tkaczyk et al, Nucl . Instr. and Meth A270 (1988) 373. [4] M. Holder and H. Suhr, Nucl . Instr. and Meth . A263 (1988) 319.

[5] F. Abe et al ., Nucl Instr. and Meth. A259 (1987) 466. [6] H.B . Crawley et al, IEEE Trans. Nucl Sci. NS-34 (1987) 261. [7] R. Aleksan et al ., Nucl . Instr. and Meth. A273 (1988) 303 . [8] B. Blumenfeld et al ., Phys. Rev. Lett . 62 (1989) 2237 . [9] J.A Crittenden et al ., IEEE Trans Nucl . Sci. NS-31 (1984) 1028 .