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A low temperature (Tdep ⩽800 °C ) chemical vapor deposition process for the deposition of device-quality epitaxial silicon
Materials Science and Engineering, BI (1988) 131- 134
131
A Low Temperature (Td p 800 °C) Chemical Vapor Deposition Process for the Deposition of Device-quality Epitaxial Silicon w. R. BURGER and R. REIF
D~7)artmentof ElectricalEngineeringand ('ornputerScience, MassachusettsInstitute of Technology, 77 Massachusetts4 ~enue, Room 39-567, Cambridge, MA 02139(U.S.A.)
(ReceivedFebruary 26, 1988: in revisedform March 16.1988)
Abstract
A system has been developed that permits the deposition of device quality epitaxial silicon films at low temperatures. Using this system, epitaxial layers" have been grown that have a minoritycarrier lifetime of about 0.5 ms; the highest vahw reported for any low temperature silicon epitaxial process. 1. Introduction
The evolution of high speed bipolar and metal/ oxide/semiconductor transistor technology requires the development of a low temperature process for the deposition of high quality epitaxial silicon. We have developed a system and procedure using standard high vacuum chemical vapor deposition (CVD) technology for the low temperature ( 7~1¢p< 800 °C) deposition of devicequality epitaxial silicon films. We have successfully fabricated, for the first time, bulk-quality bipolar transistors in low temperature epitaxial silicon [1]. Optimized deposition conditions will also be reported which yield epitaxial layers with a minority-carrier lifetime of about 0.5 ms for a deposition temperature of only 775 °C [2]. 2. E x p e r i m e n t a l details
The details of the deposition system and procedure used have been reported elsewhere [3-5]. Briefly, the deposition system is a singlewafer reactor that employs radiant heating, a 13.56 MHz r.f. generator to excite the plasma, a d.c. power supply to bias the susceptor, and a turbomolecular pump to obtain a hydrocarbonfree environment of low base pressure. A novel in situ pre-deposition argon sputter clean is employed to prepare the silicon surface 0921-5107/88/$3.50
for the deposition of high quality epitaxial layers. The sputter uses a d.c. bias to accelerate argon ions generated by an r.f. plasma towards the substrate thereby physically removing surface contaminants. The sputter occurs at the deposition temperature, facilitating the overlap of the sputter with the deposition to prevent the recontamination of the surface in a standard high vacuum system. Typical sputter conditions would be an r.f. power of 5 W, a d.c. bias of - 100 V, a sputter duration of 15 min and a pressure of 4.2 mTorr. The deposition commences immediately after the conclusion of the argon sputter clean. The electrical characteristics reported in this paper are for devices fabricated in thermally deposited undoped epitaxial silicon layers. Maintaining the plasma during the deposition permits plasmaenhanced chemical vapor depositions (PECVD), which are expected to facilitate the deposition of in situ doped epitaxial layers (experiments to determine the electrical quality of the in situ doped films are in progress). Unless otherwise indicated, the depositions reported in this paper were in pure silane at a pressure of 6.4 mTorr for 30-60 rain. The resulting films were 1.5-2,5/~m thick, n type, and with a typical carrier concentration of ( 1 - 2 ) x 1015 c m -~. Bipolar transistors and p-n diodes were fabricated in the low temperature epilayers and in identically processed bulk-silicon control substrates to establish the quality of the epitaxial films. The control substrates and the substrates used for the epitaxial depositions are n type, ( 100 ) oriented and with resistivities of 10-20 Q cm. The transistor structure is a vertical npn bipolar structure with topside base and emitter contacts and a backside collector contact. The base and emitter regions were formed by the following ion implantation and/or annealing © Elsevier Sequoia/Printed m The Netherlands
132
steps: (1) base implant: B +, d o s e = 5 x 10 ~3 cm 2, energy=30 keV; (2) base drive-in: 30 min at 950 °C with a CVD oxide cap 4000 A thick; (3) emitter implant: As ~, d o s e = 5 x 10 ~5 cm--~, energy= 90 keV; (4) emitter drive-in: 30 min at 950 °C with a CVD oxide cap 2000 A thick. The CVD oxide was deposited at 400 °C whilst all other processing temperatures were 950°C or less. The contact metallization was an A1-Si-Cu alloy. The processing schedule was designed to yield an emitter junction depth of 2500 A and an active base width of 1500 A for a collector-emitter voltage VcE of 5.0 V and a base-emitter voltage VBE of 0.6 V. The vertical carrier concentration profile is representative of the profiles used in modern high speed bipolar integrated circuits. 3. Results and discussion
Four sputter parameters have a direct effect on the epitaxial film quality: the ion energy (controlled by the d.c. bias), the ion flux (controlled by the r.f. power), the total ion dose (controlled by the product of the flux and the sputter duration) and the sputter temperature. The d.c. bias has the strongest effect on the quality of the epitaxial layer. Using d.c. bias voltages of - 200 or - 300 V results in the generation of greater than l0 s dislocation cm-2 (by cross-sectional transmission electron microscopy). Decreasing the d.c. bias (and thus the ion energy) to - 100 V permits the deposition of essentially dislocation-free epitaxial layers at temperatures at least as low as 750 °C. The effect of the d.c. bias on the electrical parameters extracted from base-collector (B-C) diodes (emitter open) fabricated in epitaxial layers deposited at 750 °C is illustrated in Table 1. Decreasing the d.c. bias to - 100V decreased the leakage current by four orders of magnitude
and increased the minority-carrier lifetime by three orders of magnitude. The optimum ion flux and dose for the subsequent deposition of dislocation-free epitaxial layers are also functions of temperature (see ref. 3 for details). Figure 1 presents the flo t',s. 1( characteristics of bipolar transistors fabricated in 750, 775 and 800 °C epitaxial layers. We can observe that the electrical quality of the epitaxial layers is a strong function of the deposition temperature. Figure 2 compares the flo vs. 1C characteristic for an 800 °C epitaxial layer with that for bulk silicon. This curve suggests, and a more detailed investigation verifies, that the electrical quality of the 800°C epitaxial layer is comparable with or superior to that of bulk silicon [1, 6]. The second experiment was designed to determine if annealing at the deposition temperature has an effect on the formation of complexes which could possibly degrade the electrical quality of the epitaxial films [6 ]. The experiment consisted of depositing an epitaxial layer at 800 °C and annealing one quarter of this film at 750 °C in N 2 for 2 h before commencing with the transistor fabrication procedure. The tow voltage and reverse bias current-voltage (I-V) characteristics for B - C diodes fabricated in epitaxial layers deposited at 750, 775 and 800 °C, as well as the 800 °C film annealed for 2 h at 750 °C, are shown in Figs. 3 and 4 respectively. These 1- V characteristics indicate that annealing at the deposition temperature has no effect on the electrical properties of the epitaxial layers; the electrical quality appears to be determined by the instantaneous deposition conditions (e.g. vacuum
60.0
--
,,5"c
.....
~ 1
¢~ 40,0
TABLE 1 S u m m a r y of diode ideality factors, life times and reverse-bias diode leakage currents for argon sputter d.c. bias voltages of - 1 0 0 , - 2 0 0 and - 3 0 0 V
E o (-9
./ ///
Sputter conditions
20.0
Diode parameter
/ / Leakage at - 10 V
ldeality n
Lifetime r I,
/
/
/
//
-/
* ~J
VCE : 5 . O r
!
. / -
- 300 V, 2.5 W, 5 rain - 200 V, 5 W, 10 min - 100 V, 5 W, 15 rain
5.7#A 2.3#A 255pA
1.68 1.66 1.52
" T h e deposition t e m p e r a t u r e was 750 °C.
9.1 ns 13ns 1.3#s
I0 "9
10 8
I 0 -7
10 - 6
10 5
I 0 -4
I 0 ]*
iO 2
Collector Current r A m p s ]
Fig. 1. /3,, vs. I c for transistors fabricated in epitaxial layers deposited at 750, 775 and 800 °C.
133
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10 .7
"~.:
l
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,
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Fig. 4. Reverse-bias 1 V characteristics for the same diodes as in Fig, 3.
,
7
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.
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600
at 800°C
_
-
and subsequently
quality, deposition rate and deposition temperature). The final experiment investigated the effect of varying the deposition rate (which is proportional to the flow rate of SiH~) on the electrical properties of epitaxial layers deposited at 775 °C [2]. The low voltage and reverse-bias I - V characteristics for the B-C diodes fabricated in epitaxial layers with the flow rate of S i l l 4 varying from 5 to 80 standard cm s rain-l (which varies the deposition rate from about 50 to 800 A rain ]) are shown in Figs. 5 and 6 respectively. The I - V characteristics indicate that, contrary to expectations, reducing the growth rate actually degrades the electrical quality of the epitaxial layers. Reducing the deposition rate increases the relative contaminant flux from the vacuum system to the growing surface (carbon species, 02 etc.),
/I
,o-t-
Fig. 3. L o w voltage 1 V characteristics o f B - C diodes fabricated in 750, 775 and 800 °C epitaxial layers, and in an
epitaxial layer deposited annealed at 750 °C for 2 h.
_
, ~ I ,
-
1.0
7
O
-0.5
Bose-Collector
0.5
Voltoge
1.0
[Volts]
Fig. 5. L o w voltage 1- V characteristics of B - C diodes fabricated in epitaxial layers deposited with the flow rate of Sill 4 varied from 5 to 80 standard cm ~ rain ~ (which c o r r e s p o n d s to deposition rates of 50 to 800 A rain ' respectively). The deposition temperature was 775 °C.
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,
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,
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Fig. 6. Reverse-bias 1- V characteristics for the same diodes as in Fig. 5.
134 TABLE 2 Summary of diode ideality factors, lifetimes and reverse-bias leakage currents from diodes wtih the I- V characteristics in Figs. 5 and 6.
SiHa flow
Lifetirne rl,
(standard cm 3 min ~'
(/~s)
ldeality n
Leakage at - 5 l
80 40 20 10 5
480 62 0.17 0.33 0.015
1.01 1.05 1.62 1.53 1.44
(1.8 1.0 3.4x 1() ~ 4.3 x 111~ 6 . 9 x 104
Bulk Si
120
1.02
1.3
(pA)
which degrades the surface mobility of silicon adatoms and results in the incorporation of point defects into the epitaxial layer. Table 2 summarizes the device parameters extracted from the forward-bias regime of these B-C diodes and also from a bulk-silicon control. The epitaxial layer deposited with an Sill4 flow rate of 80 standard cm 3 min- ~ had a better ideality factor, a lower leakage current and a superior minoritycarrier lifetime (about 0.5 ms) in comparison with that of the bulk-silicon control.
growth rate during the deposition. Depositi~m conditions have been identified which produce epitaxial layers with a minority-carrier lifetime ot about 0.5 ms for a deposition temperature of only 775 °C [2]; this is the longest minority-carrier lifetime reported for any low temperature silicon epitaxy process.
5. Future work
Our group is presently investigating PECVDs of both intrinsic and in situ doped low temperature epitaxial silicon [7, 8]. Preliminary work indicates that the addition of a plasma to the CVD of in situ arsenic-doped epitaxial layers improves the morphology of the epitaxial layer, prevents the degradation of the deposition rate at high doping levels, and improves the incorporation rate by one order of magnitude An evaluation of the electrical characteristics of these films is in progress. We are also investigating the deposition of SiGe alloys, polysilicon-emitter transistors and novel in situ doped device structures in low temperature epitaxial layers.
4. Conclusions
A system and procedure have been developed using standard high vacuum CVD technology for the low temperature ( Tdep "~ 800 °C) deposition of device-quality epitaxial silicon films. The deposition procedure combines a novel in situ argon sputter clean with an ultra-low pressure silane deposition to permit the deposition of high quality epitaxial silicon at temperatures in the range 750-800 °C. Results have been presented illustrating the strong dependence of the film quality on the ion energy during the sputter, on the temperature during the deposition, and on the
References l W. R. Burger and R. Reif, Appl. l'hys. Lett., 50 (19871 1447. 2 W. R. Burger and R. Reif, J. Appl. Phys., 63 {1988) 383. 3 W.R. Burger and R. Reif, J. AppLPhys., 62 (1987) 4255. 4 J. H. Comfort, L. M. Garverick and R. Reif, J. Appl. Physl, 62 (1987) 3388. 5 L. M. Garverick, J. H. Comfort, T. R. Yew, F. A. Baiocchi, H. S. Luftman and R. Reif, J. Appl. Ph):s, 62 (1987) 3398. 6 W. R. Burger and R. Reif, J. AppL Phys, 63(19881 368: 7 J. H. Comfort and R. Reif, AppL Phys. Lett., 5l (1987) 1536. 8 J. H. Comfort and R. Reif, Appl. Phys~ Lett., 5l (19871 2(t16.
131
A Low Temperature (Td p 800 °C) Chemical Vapor Deposition Process for the Deposition of Device-quality Epitaxial Silicon w. R. BURGER and R. REIF
D~7)artmentof ElectricalEngineeringand ('ornputerScience, MassachusettsInstitute of Technology, 77 Massachusetts4 ~enue, Room 39-567, Cambridge, MA 02139(U.S.A.)
(ReceivedFebruary 26, 1988: in revisedform March 16.1988)
Abstract
A system has been developed that permits the deposition of device quality epitaxial silicon films at low temperatures. Using this system, epitaxial layers" have been grown that have a minoritycarrier lifetime of about 0.5 ms; the highest vahw reported for any low temperature silicon epitaxial process. 1. Introduction
The evolution of high speed bipolar and metal/ oxide/semiconductor transistor technology requires the development of a low temperature process for the deposition of high quality epitaxial silicon. We have developed a system and procedure using standard high vacuum chemical vapor deposition (CVD) technology for the low temperature ( 7~1¢p< 800 °C) deposition of devicequality epitaxial silicon films. We have successfully fabricated, for the first time, bulk-quality bipolar transistors in low temperature epitaxial silicon [1]. Optimized deposition conditions will also be reported which yield epitaxial layers with a minority-carrier lifetime of about 0.5 ms for a deposition temperature of only 775 °C [2]. 2. E x p e r i m e n t a l details
The details of the deposition system and procedure used have been reported elsewhere [3-5]. Briefly, the deposition system is a singlewafer reactor that employs radiant heating, a 13.56 MHz r.f. generator to excite the plasma, a d.c. power supply to bias the susceptor, and a turbomolecular pump to obtain a hydrocarbonfree environment of low base pressure. A novel in situ pre-deposition argon sputter clean is employed to prepare the silicon surface 0921-5107/88/$3.50
for the deposition of high quality epitaxial layers. The sputter uses a d.c. bias to accelerate argon ions generated by an r.f. plasma towards the substrate thereby physically removing surface contaminants. The sputter occurs at the deposition temperature, facilitating the overlap of the sputter with the deposition to prevent the recontamination of the surface in a standard high vacuum system. Typical sputter conditions would be an r.f. power of 5 W, a d.c. bias of - 100 V, a sputter duration of 15 min and a pressure of 4.2 mTorr. The deposition commences immediately after the conclusion of the argon sputter clean. The electrical characteristics reported in this paper are for devices fabricated in thermally deposited undoped epitaxial silicon layers. Maintaining the plasma during the deposition permits plasmaenhanced chemical vapor depositions (PECVD), which are expected to facilitate the deposition of in situ doped epitaxial layers (experiments to determine the electrical quality of the in situ doped films are in progress). Unless otherwise indicated, the depositions reported in this paper were in pure silane at a pressure of 6.4 mTorr for 30-60 rain. The resulting films were 1.5-2,5/~m thick, n type, and with a typical carrier concentration of ( 1 - 2 ) x 1015 c m -~. Bipolar transistors and p-n diodes were fabricated in the low temperature epilayers and in identically processed bulk-silicon control substrates to establish the quality of the epitaxial films. The control substrates and the substrates used for the epitaxial depositions are n type, ( 100 ) oriented and with resistivities of 10-20 Q cm. The transistor structure is a vertical npn bipolar structure with topside base and emitter contacts and a backside collector contact. The base and emitter regions were formed by the following ion implantation and/or annealing © Elsevier Sequoia/Printed m The Netherlands
132
steps: (1) base implant: B +, d o s e = 5 x 10 ~3 cm 2, energy=30 keV; (2) base drive-in: 30 min at 950 °C with a CVD oxide cap 4000 A thick; (3) emitter implant: As ~, d o s e = 5 x 10 ~5 cm--~, energy= 90 keV; (4) emitter drive-in: 30 min at 950 °C with a CVD oxide cap 2000 A thick. The CVD oxide was deposited at 400 °C whilst all other processing temperatures were 950°C or less. The contact metallization was an A1-Si-Cu alloy. The processing schedule was designed to yield an emitter junction depth of 2500 A and an active base width of 1500 A for a collector-emitter voltage VcE of 5.0 V and a base-emitter voltage VBE of 0.6 V. The vertical carrier concentration profile is representative of the profiles used in modern high speed bipolar integrated circuits. 3. Results and discussion
Four sputter parameters have a direct effect on the epitaxial film quality: the ion energy (controlled by the d.c. bias), the ion flux (controlled by the r.f. power), the total ion dose (controlled by the product of the flux and the sputter duration) and the sputter temperature. The d.c. bias has the strongest effect on the quality of the epitaxial layer. Using d.c. bias voltages of - 200 or - 300 V results in the generation of greater than l0 s dislocation cm-2 (by cross-sectional transmission electron microscopy). Decreasing the d.c. bias (and thus the ion energy) to - 100 V permits the deposition of essentially dislocation-free epitaxial layers at temperatures at least as low as 750 °C. The effect of the d.c. bias on the electrical parameters extracted from base-collector (B-C) diodes (emitter open) fabricated in epitaxial layers deposited at 750 °C is illustrated in Table 1. Decreasing the d.c. bias to - 100V decreased the leakage current by four orders of magnitude
and increased the minority-carrier lifetime by three orders of magnitude. The optimum ion flux and dose for the subsequent deposition of dislocation-free epitaxial layers are also functions of temperature (see ref. 3 for details). Figure 1 presents the flo t',s. 1( characteristics of bipolar transistors fabricated in 750, 775 and 800 °C epitaxial layers. We can observe that the electrical quality of the epitaxial layers is a strong function of the deposition temperature. Figure 2 compares the flo vs. 1C characteristic for an 800 °C epitaxial layer with that for bulk silicon. This curve suggests, and a more detailed investigation verifies, that the electrical quality of the 800°C epitaxial layer is comparable with or superior to that of bulk silicon [1, 6]. The second experiment was designed to determine if annealing at the deposition temperature has an effect on the formation of complexes which could possibly degrade the electrical quality of the epitaxial films [6 ]. The experiment consisted of depositing an epitaxial layer at 800 °C and annealing one quarter of this film at 750 °C in N 2 for 2 h before commencing with the transistor fabrication procedure. The tow voltage and reverse bias current-voltage (I-V) characteristics for B - C diodes fabricated in epitaxial layers deposited at 750, 775 and 800 °C, as well as the 800 °C film annealed for 2 h at 750 °C, are shown in Figs. 3 and 4 respectively. These 1- V characteristics indicate that annealing at the deposition temperature has no effect on the electrical properties of the epitaxial layers; the electrical quality appears to be determined by the instantaneous deposition conditions (e.g. vacuum
60.0
--
,,5"c
.....
~ 1
¢~ 40,0
TABLE 1 S u m m a r y of diode ideality factors, life times and reverse-bias diode leakage currents for argon sputter d.c. bias voltages of - 1 0 0 , - 2 0 0 and - 3 0 0 V
E o (-9
./ ///
Sputter conditions
20.0
Diode parameter
/ / Leakage at - 10 V
ldeality n
Lifetime r I,
/
/
/
//
-/
* ~J
VCE : 5 . O r
!
. / -
- 300 V, 2.5 W, 5 rain - 200 V, 5 W, 10 min - 100 V, 5 W, 15 rain
5.7#A 2.3#A 255pA
1.68 1.66 1.52
" T h e deposition t e m p e r a t u r e was 750 °C.
9.1 ns 13ns 1.3#s
I0 "9
10 8
I 0 -7
10 - 6
10 5
I 0 -4
I 0 ]*
iO 2
Collector Current r A m p s ]
Fig. 1. /3,, vs. I c for transistors fabricated in epitaxial layers deposited at 750, 775 and 800 °C.
133
60.0
__TTTT
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I
,
,~r~-T
,,,i
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,
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750oc
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OOO°C + 2 h , ~
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775"C gO0-C
750"C
~
~ - -
BOO*C B u l k S,
~u
20.Q VCE
5.0 V
,d 3 tO 9
10 B
I0 7
I0 6
Colleclor
i0-5
Currenl
I0 4
i0-3
7-
I
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l
I
I
l
{
l
I
t
l
'
- 5.0
10"2
- 3.0 Bose-Colleclor
4.0
[Amps]
Fig. 2. fl~, vs. i( f o r transistors f a b r i c a t e d b o t h in an 8l)0 °C epitaxia] layer and in a b u l k - s i l i c o n c o n t r o l .
10 .7
"~.:
l
l
I
'
,ffm
'
,
,
2.0 Volloge
- 1.0 [Veils]
0
Fig. 4. Reverse-bias 1 V characteristics for the same diodes as in Fig, 3.
,
7
- ....
.
lO'B
-----_
~ I O -9 E •~ i04C
_
~ lo-'l
i
-----
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.... ......
40 sccm 20 sccm
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-----
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///
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./,#/
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-
lO - l ] iO-14 .
i 0 i~ - 600
,
, I , k~-I - 400
, , ,Ill,
,~2_,
- 200 O 200 400 Bose - Colleclor Volloge [mVoll ]
600
at 800°C
_
-
and subsequently
quality, deposition rate and deposition temperature). The final experiment investigated the effect of varying the deposition rate (which is proportional to the flow rate of SiH~) on the electrical properties of epitaxial layers deposited at 775 °C [2]. The low voltage and reverse-bias I - V characteristics for the B-C diodes fabricated in epitaxial layers with the flow rate of S i l l 4 varying from 5 to 80 standard cm s rain-l (which varies the deposition rate from about 50 to 800 A rain ]) are shown in Figs. 5 and 6 respectively. The I - V characteristics indicate that, contrary to expectations, reducing the growth rate actually degrades the electrical quality of the epitaxial layers. Reducing the deposition rate increases the relative contaminant flux from the vacuum system to the growing surface (carbon species, 02 etc.),
/I
,o-t-
Fig. 3. L o w voltage 1 V characteristics o f B - C diodes fabricated in 750, 775 and 800 °C epitaxial layers, and in an
epitaxial layer deposited annealed at 750 °C for 2 h.
_
, ~ I ,
-
1.0
7
O
-0.5
Bose-Collector
0.5
Voltoge
1.0
[Volts]
Fig. 5. L o w voltage 1- V characteristics of B - C diodes fabricated in epitaxial layers deposited with the flow rate of Sill 4 varied from 5 to 80 standard cm ~ rain ~ (which c o r r e s p o n d s to deposition rates of 50 to 800 A rain ' respectively). The deposition temperature was 775 °C.
IO-E
~
,
,
,
l
,
,
,
,
1 ,
,
, TI
,
,
,-7
1 ,
,
,
,
i0 "7
~lo e
-
°
" •i0-9
-
- ~ io-tO ....... ---o co
io -H
BO 40 20 I0 .5
~
_
sccm sccm sccm $ccm sccm
°
.
..
lO-I ,~ i0-*~ -5.0
-4.0 -3~) Bose-Colleclor
-2.0 Volloqe
-I.0 [Volts]
Fig. 6. Reverse-bias 1- V characteristics for the same diodes as in Fig. 5.
134 TABLE 2 Summary of diode ideality factors, lifetimes and reverse-bias leakage currents from diodes wtih the I- V characteristics in Figs. 5 and 6.
SiHa flow
Lifetirne rl,
(standard cm 3 min ~'
(/~s)
ldeality n
Leakage at - 5 l
80 40 20 10 5
480 62 0.17 0.33 0.015
1.01 1.05 1.62 1.53 1.44
(1.8 1.0 3.4x 1() ~ 4.3 x 111~ 6 . 9 x 104
Bulk Si
120
1.02
1.3
(pA)
which degrades the surface mobility of silicon adatoms and results in the incorporation of point defects into the epitaxial layer. Table 2 summarizes the device parameters extracted from the forward-bias regime of these B-C diodes and also from a bulk-silicon control. The epitaxial layer deposited with an Sill4 flow rate of 80 standard cm 3 min- ~ had a better ideality factor, a lower leakage current and a superior minoritycarrier lifetime (about 0.5 ms) in comparison with that of the bulk-silicon control.
growth rate during the deposition. Depositi~m conditions have been identified which produce epitaxial layers with a minority-carrier lifetime ot about 0.5 ms for a deposition temperature of only 775 °C [2]; this is the longest minority-carrier lifetime reported for any low temperature silicon epitaxy process.
5. Future work
Our group is presently investigating PECVDs of both intrinsic and in situ doped low temperature epitaxial silicon [7, 8]. Preliminary work indicates that the addition of a plasma to the CVD of in situ arsenic-doped epitaxial layers improves the morphology of the epitaxial layer, prevents the degradation of the deposition rate at high doping levels, and improves the incorporation rate by one order of magnitude An evaluation of the electrical characteristics of these films is in progress. We are also investigating the deposition of SiGe alloys, polysilicon-emitter transistors and novel in situ doped device structures in low temperature epitaxial layers.
4. Conclusions
A system and procedure have been developed using standard high vacuum CVD technology for the low temperature ( Tdep "~ 800 °C) deposition of device-quality epitaxial silicon films. The deposition procedure combines a novel in situ argon sputter clean with an ultra-low pressure silane deposition to permit the deposition of high quality epitaxial silicon at temperatures in the range 750-800 °C. Results have been presented illustrating the strong dependence of the film quality on the ion energy during the sputter, on the temperature during the deposition, and on the
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