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A method for hybrid lithography
Microelectronic North-Holland
Engineering
93
8 (1988) 93-103
A method for hybrid lithography Geraint Owen Hewlett Packard Laboratories, Palo Alto, CA94303-0867,
U.S. A.
Received 2 February 1987 Revised 10 December 1987
Abstract. A mathematical technique is described which allows direct-write electron lithography to be used in conjunction with optical lithography to pattern integrated circuits. The method is sufficiently general to cope with chips which are larger than the scan field of the electron lithography instrument, distorted patterns, and nonplanar substrates. Substantial latitude in the number and placement of the registration marks is permitted, and redundant marks may be used to increase the accuracy of the registration procedure.
Keywords. Electron lithography, tortion, integrated circuits.
optical
lithography,
hybrid
lithography,
pattern
dis-
Geraint Owen was born in Bangor, Wales in 1949. He received his B.A. and Ph.D. degrees in electrical engineering from Cambridge University in 1971 and 1975. He has worked at the Hewlett Packard Company since 1979, and his present activities include advanced optical lithography and integrated circuit metrology.
1. Introduction
Two important advantages of direct-write electron lithography are its high resolution (well under 1 km), and its flexibility (due to the fact that masks or retitles are not required for pattern replication). However, a major disadvantage is its low speed. Because of this mix of properties, the use of direct-write electron lithography is confined almost exclusively to research laboratories or low-volume production of specialized devices. Full-scale mass production of semiconductor devices, on the other hand, is carried out using light optical projection printers. These are considerably 0167-9317/88/$3.50
@ 1988, Elsevier Science Publishers B.V. (North-Holland)
G. Owen / A method for hybrid lithography
94
faster than electron lithography instruments, being capable of patterning tens of wafers per hour. However, they are not capable of such high resolution, and, since they rely on the use of masks or retitles, they are relatively inflexible. It would be attractive to combine the merits of optical and direct-write electron lithography: such a technique is termed “hybrid” lithography. Using it, most of the levels of an integrated circuit would be patterned optically, but the remaining levels (which might demand high resolution or be subject to frequent modifications) would be patterned using direct-write electron lithography [l]. In this paper, a general mathematical technique is described which allows an electron beam exposure to be accurately mapped onto a pattern previously exposed on the wafer.
2. The nature of the problem In Fig. 1, the square ABCD depicts a chip on a wafer which has been exposed optically. For a modern chip, the dimensions might be as large as 20 x 20 mm’. Imagine that part of the pattern is a small dot at the point P. The wafer has been placed on the stage of an electron lithography instrument, and the undeflected beam strikes it at Q. The square abed depicts the region over which the electron beam may be scanned. Its size depends on the type of machine, but is unlikely to be greater than 5 X 5 mm2. If the point P is to be accessed by the electron beam, the stage must be moved so as to position P within the square &cd, and the beam must then be deflected to P. Thus, the fundamental problem that has to be solved in order to carry out hybrid lithography is to determine the way in which the stage motion and beam deflection of the electron lithography instrument map onto the optically exposed chip. This mapping depends on three factors: the characteristics of the electron 11 n
I
‘I I-! ii
-t
P.
_)
hh
d
C
a
b
I3
Fig. 1. Diagram illustrating the nature of the hybrid lithography problem. ABCD chip to be patterned, and abed the scan field of the electron lithography instrument. depict the chip registration marks.
depicts the I, m, and n
G. Owen
I A method for hybrid lithography
95
lithography machine’s stage, the characteristics of its deflection system (which, in general, are affected by the height of the substrate), and the shape, position, and orientation of the pattern previously exposed on the chip. The mapping function is determined by using the electron lithography instrument to access registration marks. These will have been printed around the periphery of each chip as part of a preceeding optical exposure (and are depicted as I, m, and II in Fig. 1). The mapping function is calculated from the discrepancy between the stage and beam positions at which the marks are actually found and the positions at which they should have been found, according to the pattern data. The characteristics of various existing types of scheme for carrying out this operation are summarized in Table 1. Historically, the first problem to be solved was that of matching the deflector to the substrate [2-81. This level of matching works well as long as the dimensions of the chip are no greater than those of the deflection field. Under these conditions, the stage does not have to be repositioned during the patterning of a chip, and so its calibration is unnecessary. Because the deflector is matched directly to the substrate, this type of scheme can compensate for variations in chip height, and for magnification errors and distortions in the optically exposed pattern. Although, in general, multifield chips cannot be patterned without stitching errors, Ozdemir et al. devised a variation of this type of scheme which allowed chips containing four fields to be patterned accurately without calibrating the stage [5]. The need for this was circumvented by placing registration marks within the chip itself, a measure which worked, but which presumably restricted the freedom available to circuit designers. Another group of schemes consists of those which match the stage to the deflector. (A precursor to these is the work of Cahen and Trotel, who first reported the use of a laser interferometer to measure stage position [9].) The
Table
1
Properties
of various
types of schemes
for hybrid lithography Compensation chip height variation
for
Compensation and distortion exposed chip
Type of scheme
Multifield capability
Deflector matched to substrate
no (in general)
yes
yes
Stage matched to deflector
yes
possible
no
Scheme of Wilson et al. [14]
yes
no
yes
Scheme here
yes
yes
yes
described
for magnification errors in optically
96
G. Owen / A method for hybrid lithography
scheme described by Alles et al. [lo] is important because the type of machine in which it was used (the EBES) has since been widely used for mask and reticle making. However, it had two limitations. Firstly, it did not take into account the distortions produced by the beam deflector (and consequently could be used only with a deflection field of 0.5 x 0.5 mm* or less, in which the distortions were negligible). Secondly, it did not take into account variations in substrate height. The first limitation was removed by Asai et al. [ 111, and the second by Takamoto et al. [12]. Because machines of the EBES type are primarily designed for mask and reticle making, they are in general, incapable of direct writing using chip-by-chip registration. Yau and Thibault reported using such a machine for direct-writing, registration being carried out using a single set of global registration marks on the periphery of the wafer [13]. Such a scheme has the serious disadvantage that it can not compensate for the significant variations that occur from chip to chip. Wilson et al. described a scheme used in an electron lithography machine intended for writing multifield chips [14]. It involved matching the substrate to the stage (by using it to find registration marks). In a separate calibration, the stage was matched to the deflector by a method similar to that of Alles et al. Because the deflector was not directly calibrated to the substrate, this scheme was satisfactory only if the substrate was reasonably flat. A similar technique is to match the substrate to the deflector, and then match the deflector to the stage. Again, this technique works well only with flat substrates. An additional disadvantage is that the registration marks must all lie within range of the deflector, and are therefore confined to one corner of a multifield chip (as is illustrated in Fig. 1). The scheme described here overcomes these limitations, since it calibrates both the deflector and the stage directly to the chip being written. It also has the following useful properties: (i) A least-squares error technique is employed, which allows registration errors to be reduced by using redundant marks. (ii) Compensation for nonlinear distortions is straightforward. 3. Mathematical model The pattern data describing a chip can be regarded as a set of instructions which would describe how to get to locations in the chip if no geometrical misalignments or errors were present. Thus, in Fig. 2, the point P would be accessed by a combination of a stage move and a beam deflection. The stage move, of magnitude (X,, Y,), would bring the point P’ directly under the undeflected beam. The deflection, of magnitude (Xdr Y,), would move the beam to the point P. Thus, if the pattern data coordinates corresponding to P are (X, Y), then
97
G. Owen / A method for hybrid lithography
ov
11
,X
-xs-
Fig. 2. Coordinate
system
to define
pattern position deflections.
data
in terms
of stage
moves
and beam
In practice, the point P will correspond to a precise physical location (such as the gate electrode of a particular MOSFET). Because of the effects of geometrical misalignments and errors, the actual stage move and beam deflection parameters required to access P will be (x,, yJ and (xd, yd). The model that is assumed here is that
(2) and (3) Substituting
(2) and (3) into (1) gives the result on which this scheme is based:
(4)
Note that both stage and deflector terms are combined in one equation. As a result, both are calibrated simultaneously, and it is therefore unnecessary to confine the registration marks to lie within an area no bigger than the deflection field. The objective of the registration process is to calculate values for the unknown coefficients in the 2 x 5 matrix in (4). This is done by comparing the positions of the registration marks specified in the registration data with the positions at which the lithography instrument actually finds them on the wafer
G. Owen I A method for hybrid lithography
98
to be patterned. Having found the values of these coefficients, appropriate stage move and beam deflection parameters for exposing the pattern are computed from the inverted forms of (2) and (3). As it stands, the model will not account for nonlinear effects, such as lens or deflector distortions. Simple extensions which allow such effects to be taken into account are described in Section 6. 4. The registration scheme The chip to be written is surrounded by N registration marks, which may be placed anywhere in the vicinity of the chip. If each mark is to be measured once only, it is necessary that Na 5. (Each mark yields two pieces of information, in the form of a pair of measured coordinates: the values of 10 unknown coefficients are to be found.) Let the pattern data coordinates corresponding to the center of the ith mark be (Xi, Yi). Assume that, in order to position the beam over the center of the mark, the required stage parameters are (Xsi, ysi) and the required deflector parameters are (Xdi, ydi). The values of the registration coefficients a,, b,, ad, bd, and Ax are found in the following manner. Using (l), the quantity Xi can be formed, where Xl = G&i +
b,ysi + &l&i + bdydi + AX.
If there are N registration E = f
(xi
-
(-3
marks, a total squared error can be defined as
x:)‘.
(6)
i=l
The required values of the unknown i.e. they fulfill the condition
aE =_-_=_--~__~___~ aE aE aE a& db, au, dbd Combining
coefficients are those which minimize E,
aE
o
dAx
(7)
’
(5), (6), and (7) gives the result
C C
I 1 c
Xi-%
Xiysi
XiXdi
(8)
9
where
C Xii c
E
1
YsiXst
2
Xdi&i
2
ydixsi
1
c
Xdiysi
1
ydiysi
c
hi
z
“y”i
&ixdi
c
ysixdi
c
xii
1
y$&ii
&;ydi
$
f;ydi
$
XdlYdi
E
;di
&l
SI
Xdr
dr
&i
Nd’
.
(9)
G. Owen I A method for hybrid lithography
99
In these equations, the summations are made over the range 1 G i s N. The values of the remaining unknown coefficients are calculated in an analagous way by forming the error quantity (Yi - Y:), giving the result
.
(10)
5. An example
Figure 3 illustrates the pattern data of a chip measuring 3000 X 2000 pm’. It is surrounded by eight registration marks, labelled u-h. Beam deflections that could be used to find the marks are depicted as arrows and the corresponding stage positions are shown as dots. The measurement of the ten registration coefficients is carried out by accessing each registration mark in turn. To access mark a, the stage parameter are set to (xs = -354, y, = -354) and the beam is deflected to look for a mark in the vicinity of (& = 354, yd = 354). Thus, for this mark, x=0, x, = -354, &, = 354,
Y=O, ys = -354, yd = 354.
Similar sets of values apply for the remaining 7 marks. After all eight marks have been found, the vectors on the right-hand sides of (8) and (10) are calculated, as is the matrix [M] in (9). [M] is then inverted, and a,, b,, c,, d,, ad, bd, cd, dd, Ax, and Ay calculated.
(-3547354)
Fig. 3. A chip, measuring 3000 x 2000 pm’, surrounded by eight registration marks, shown as circles, and denoted by a, 6, c, d, e, f, g, and h. The arrows represent the beam deflections used to access each mark, and the dots labeled with coordinate pairs represent corresponding stage positions (i.e. the positions on the wafer at which the beam would land when undeflected).
G. Owen / A method for hybrid lithography
100
(1500,2500)
(lSOO,-500)
(-500,400)
Fig. 4. A symmetrical
arrangement
(3500,-500)
of registration
conditions
for the chip of Fig. 3.
A restriction exists on the allowable configurations of the registration marks. If it is assumed that the electron lithography instrument and the wafer to be patterned are both perfect, it can be shown that [M] is singular if, for all the registration marks, the values of X,, YS, X,,, and Yd satisfy the same linear equation (see Appendix A). If the instrument or the wafer are not perfect, the matrix is not singular, but it is still ill conditioned. For the symmetrical case of Fig. 4, the linear relationship is tx, + f Y, + 9x,
+ Yd = 1000.
(11)
For the case of Fig. 3, no such relationship exists, and the scheme is well conditioned. An arrangement of marks may be tested by taking any four and deriving an equation of the form of (11) which satisfies their coordinates. If all of the remaining marks also satisfy this equation, then the arrangement is ill conditioned. 6. Extensions of the scheme In practice, the optically printed pattern, the stage of the electron lithography instrument, or its deflection system may suffer from nonlinear distortions. As an example, assume that trapezoidal distortion must be corrected. It is then necessary to modify (4) to
US
b,
f?,
ad
bd
ed
AX
G
d,
fs
cd
dd
fd
Ay
1 . “;,’
yd
Xd yd ‘l-
(12)
G. Owen / A method for hybrid lithography
101
The trapezoidal distortion is accounted for by the additional terms in x,y, and &yd, and the additional coefficients e,, fs, e& and fd. The values of the registration coefficients are given by expressions similar to (8)-(lo), although, because of the greater number of unknowns, additional terms are added to the matrix [M] which increase its order to 7. For the same reason, the minimum allowable number of registration measurements also increase to 7. Further terms may be added in the same way if necessary. For example, to account for isotropic cubic and barrel distortions, these would have the form 3 xs, y,“, x,yz, and xfys for the stage and xi, y& xdy& and xiyd for the deflector. Terms which mix stage and deflector parameters, such as &Xd, &yd, y&, and ysyd can also be added: these particular terms would account for the effect of chip tilt on the characteristics of the deflector. In all these cases, the structure of the scheme remains unchanged, although the order of the matrix [M] increases by one for each pair of additional coefficients. Another straightforward extension of the scheme would allow it to be applied to electron lithography instruments with both magnetic and electrostatic deflection systems (see e.g. [15]). If the subscripts m and e refer to the magnetic and electrostatic systems respectively, then (4) is modified to
b, a,
b,
a,
be
ds
dn,
c,
de_
c,,,
Ay 1 AX
(13)
The determination of the unknown registration coefficients now involves making 7 registration mark measurements and inverting a matrix of order 7. 7. Conclusions The method for hybrid lithography described here is capable of patterning multifield chips onto distorted patterns which have been previously fabricated on nonplanar substrates. Substantial latitude in the number and positioning of the registration marks is permitted, and redundant marks may be used to increase the accuracy of the registration procedure. In its simplest form, the scheme uses a linear registration model: however, it is not difficult to incorporate more complex polynomial models. Appendix A For the matrix [M] to be singular, its determinant must be equal to zero. A general condition that forces this to be the case is that the values of (xsi, ysi,
102 xdi,
G. Owen / A method for hybrid lithography
and ydi) at each registration &i
=
pysi
+
axdi
+
mark all obey a linear relationship
Pydi
+
of the form
ET
(A.11
where CL, (Y, p, and E are constants. consequence of (A.l),
This may be proved
as follows. As a
(A.21 c
Xsiydr
=
p
1
1
xsi
/-b
c
ysi
Substituting (9) gives
=
ysiydi +
a
+ c
ac Xdi
Xdiydi +
p
1
+
p
ydi
cyii
+
+
E 1
Ydir
EN.
(A.2) into the first column of the matrix on the right-hand
side of
det[M] d
E xd, xdiYdi I I
1
ydixsi
1
ydiysi
E C &i
+
’
lC l l
ysi
0
(A-3)
CXdi Cydi
EN
0
&Ydi
In (A.3), only the columns of direct interest have been written out in full-the others are represented by dashed lines. The first determinant on the right-hand side of (A.3) must be equal to zero, since each term in the first column is a factor of Al. greater than the corresponding term in the second column. Similar arguments can be made for the three remaining determinants, and so it follows that de$M] = 0 if (A.l) is obeyed. Under these circumstances,
[M] will be singular.
G. Owen I A method for hybrid lithography
103
References [l] 0. C. Wells, T. E. Everhart and R. K. Matta, Automatic positioning of device electrodes using the scanning electron microscope, IEEE Trans. Election Devices ED-12 (1965) 556-563. [2] E. D. Wolf, W. E. Perkins and P. J. Coane, Device fabrication with the Stereoscan, in: Proc. 3rd Annual Stereoscan SEM Colloquium (Kent, Boston, MA., 1970) 99-107. [3] S. Miyauchi, K. Tanaka and J. C. Russ, Automatic pattern positioning of scanning electron beam exposure, IEEE Trans. Electron Devices ED-17 (1970) 450-457. [4] S. Magdo, M. Hatzakis and C. H. Ting, Electron beam fabrication of micron transistors, IBM J. Res. Develop. 15 (1971) 446-451. [5] F. S. Ozdemir, E. D. Wolf and C. .R. Buckey, Computer-controlled scanning electron microscope for high-resolution microelectronic pattern fabrication, IEEE Trans. Electron Devices ED-19 (1972) 624-628. [6] G. L. Varnell, D. F. Spicer and A. C. Rodger, E-beam writing techniques for semiconductor device fabrication, J. Vat. Sci. Technol. 10 (1973) 1048-1051. [7] N. Saitou, C. Munakata, Y. Miura and Y. Honda, Computer-controlled electron-beam microfabrication machine with a new registration system, J. Phys. E 7 (1974) 441-444. [8] D. E. Davis, R. D. Moore, M. C. Williams and 0. C. Woodard, Automatic registration in an electron-beam lithographic system, IBM J. Res. Develop. 21 (1977) 498-505. [9] 0. Cahen and J. Trotel, High performance step and repeat machine using an electron beam and laser interferometers, in: R. Bakish, ed., Electron and Zon Beam Science and Technology 4th International Conference (The Electrochemical Society, Princeton, NJ, 1970) 581-587. [lo] D. S. AIles, F. R. Ashley, A. M. Johnson and R. L. Townsend, Control system design and alignment methods for electron lithography, J. Vat. Sci. Technol. 12 (1975) 1252-1256. [ll] S. Asai, H. Inomata, A. Yanagisawa, E. Takeda and I. Miwa, Distortion correction and deflection calibration by means of laser interferometry in an electron-beam exposure system, J. Vat. Sci. Technol. 16 (1979) 1710-1714. [12] K. Takamoto, T. Okubo and T. Matsuda, Distortion correction and overlay accuracies achieved by the registration method using two-stage standard mark system, J. VW. Sci. Technol. B 4 (1986) 675-681. [13] L. D. Yau and L. R. Thibault, Direct electron lithographic and circuits, J. Vat. Sci. Technol. 15 (1978) 960-964.
fabrication
of silicon devices
[14] A. D. Wilson, A. Kern, J. Kirk and C. Dooly, Stitching with overlay in direct wafer writing using scanning electron beam, in: R. Bakish, ed., Electron and Zon Beam Science and Technology, 9th Zn~emational Conference (The Electrochemical Society, Princeton, NJ, 1980) 144-151. [15] C. T. Ho, M. S. Michail, W. Stickel and 0. C. Woodard, The high-performance beam deflection system of EL3, J. Vat. Sci. Technol. 19 (1981) 1069-1073.
Engineering
93
8 (1988) 93-103
A method for hybrid lithography Geraint Owen Hewlett Packard Laboratories, Palo Alto, CA94303-0867,
U.S. A.
Received 2 February 1987 Revised 10 December 1987
Abstract. A mathematical technique is described which allows direct-write electron lithography to be used in conjunction with optical lithography to pattern integrated circuits. The method is sufficiently general to cope with chips which are larger than the scan field of the electron lithography instrument, distorted patterns, and nonplanar substrates. Substantial latitude in the number and placement of the registration marks is permitted, and redundant marks may be used to increase the accuracy of the registration procedure.
Keywords. Electron lithography, tortion, integrated circuits.
optical
lithography,
hybrid
lithography,
pattern
dis-
Geraint Owen was born in Bangor, Wales in 1949. He received his B.A. and Ph.D. degrees in electrical engineering from Cambridge University in 1971 and 1975. He has worked at the Hewlett Packard Company since 1979, and his present activities include advanced optical lithography and integrated circuit metrology.
1. Introduction
Two important advantages of direct-write electron lithography are its high resolution (well under 1 km), and its flexibility (due to the fact that masks or retitles are not required for pattern replication). However, a major disadvantage is its low speed. Because of this mix of properties, the use of direct-write electron lithography is confined almost exclusively to research laboratories or low-volume production of specialized devices. Full-scale mass production of semiconductor devices, on the other hand, is carried out using light optical projection printers. These are considerably 0167-9317/88/$3.50
@ 1988, Elsevier Science Publishers B.V. (North-Holland)
G. Owen / A method for hybrid lithography
94
faster than electron lithography instruments, being capable of patterning tens of wafers per hour. However, they are not capable of such high resolution, and, since they rely on the use of masks or retitles, they are relatively inflexible. It would be attractive to combine the merits of optical and direct-write electron lithography: such a technique is termed “hybrid” lithography. Using it, most of the levels of an integrated circuit would be patterned optically, but the remaining levels (which might demand high resolution or be subject to frequent modifications) would be patterned using direct-write electron lithography [l]. In this paper, a general mathematical technique is described which allows an electron beam exposure to be accurately mapped onto a pattern previously exposed on the wafer.
2. The nature of the problem In Fig. 1, the square ABCD depicts a chip on a wafer which has been exposed optically. For a modern chip, the dimensions might be as large as 20 x 20 mm’. Imagine that part of the pattern is a small dot at the point P. The wafer has been placed on the stage of an electron lithography instrument, and the undeflected beam strikes it at Q. The square abed depicts the region over which the electron beam may be scanned. Its size depends on the type of machine, but is unlikely to be greater than 5 X 5 mm2. If the point P is to be accessed by the electron beam, the stage must be moved so as to position P within the square &cd, and the beam must then be deflected to P. Thus, the fundamental problem that has to be solved in order to carry out hybrid lithography is to determine the way in which the stage motion and beam deflection of the electron lithography instrument map onto the optically exposed chip. This mapping depends on three factors: the characteristics of the electron 11 n
I
‘I I-! ii
-t
P.
_)
hh
d
C
a
b
I3
Fig. 1. Diagram illustrating the nature of the hybrid lithography problem. ABCD chip to be patterned, and abed the scan field of the electron lithography instrument. depict the chip registration marks.
depicts the I, m, and n
G. Owen
I A method for hybrid lithography
95
lithography machine’s stage, the characteristics of its deflection system (which, in general, are affected by the height of the substrate), and the shape, position, and orientation of the pattern previously exposed on the chip. The mapping function is determined by using the electron lithography instrument to access registration marks. These will have been printed around the periphery of each chip as part of a preceeding optical exposure (and are depicted as I, m, and II in Fig. 1). The mapping function is calculated from the discrepancy between the stage and beam positions at which the marks are actually found and the positions at which they should have been found, according to the pattern data. The characteristics of various existing types of scheme for carrying out this operation are summarized in Table 1. Historically, the first problem to be solved was that of matching the deflector to the substrate [2-81. This level of matching works well as long as the dimensions of the chip are no greater than those of the deflection field. Under these conditions, the stage does not have to be repositioned during the patterning of a chip, and so its calibration is unnecessary. Because the deflector is matched directly to the substrate, this type of scheme can compensate for variations in chip height, and for magnification errors and distortions in the optically exposed pattern. Although, in general, multifield chips cannot be patterned without stitching errors, Ozdemir et al. devised a variation of this type of scheme which allowed chips containing four fields to be patterned accurately without calibrating the stage [5]. The need for this was circumvented by placing registration marks within the chip itself, a measure which worked, but which presumably restricted the freedom available to circuit designers. Another group of schemes consists of those which match the stage to the deflector. (A precursor to these is the work of Cahen and Trotel, who first reported the use of a laser interferometer to measure stage position [9].) The
Table
1
Properties
of various
types of schemes
for hybrid lithography Compensation chip height variation
for
Compensation and distortion exposed chip
Type of scheme
Multifield capability
Deflector matched to substrate
no (in general)
yes
yes
Stage matched to deflector
yes
possible
no
Scheme of Wilson et al. [14]
yes
no
yes
Scheme here
yes
yes
yes
described
for magnification errors in optically
96
G. Owen / A method for hybrid lithography
scheme described by Alles et al. [lo] is important because the type of machine in which it was used (the EBES) has since been widely used for mask and reticle making. However, it had two limitations. Firstly, it did not take into account the distortions produced by the beam deflector (and consequently could be used only with a deflection field of 0.5 x 0.5 mm* or less, in which the distortions were negligible). Secondly, it did not take into account variations in substrate height. The first limitation was removed by Asai et al. [ 111, and the second by Takamoto et al. [12]. Because machines of the EBES type are primarily designed for mask and reticle making, they are in general, incapable of direct writing using chip-by-chip registration. Yau and Thibault reported using such a machine for direct-writing, registration being carried out using a single set of global registration marks on the periphery of the wafer [13]. Such a scheme has the serious disadvantage that it can not compensate for the significant variations that occur from chip to chip. Wilson et al. described a scheme used in an electron lithography machine intended for writing multifield chips [14]. It involved matching the substrate to the stage (by using it to find registration marks). In a separate calibration, the stage was matched to the deflector by a method similar to that of Alles et al. Because the deflector was not directly calibrated to the substrate, this scheme was satisfactory only if the substrate was reasonably flat. A similar technique is to match the substrate to the deflector, and then match the deflector to the stage. Again, this technique works well only with flat substrates. An additional disadvantage is that the registration marks must all lie within range of the deflector, and are therefore confined to one corner of a multifield chip (as is illustrated in Fig. 1). The scheme described here overcomes these limitations, since it calibrates both the deflector and the stage directly to the chip being written. It also has the following useful properties: (i) A least-squares error technique is employed, which allows registration errors to be reduced by using redundant marks. (ii) Compensation for nonlinear distortions is straightforward. 3. Mathematical model The pattern data describing a chip can be regarded as a set of instructions which would describe how to get to locations in the chip if no geometrical misalignments or errors were present. Thus, in Fig. 2, the point P would be accessed by a combination of a stage move and a beam deflection. The stage move, of magnitude (X,, Y,), would bring the point P’ directly under the undeflected beam. The deflection, of magnitude (Xdr Y,), would move the beam to the point P. Thus, if the pattern data coordinates corresponding to P are (X, Y), then
97
G. Owen / A method for hybrid lithography
ov
11
,X
-xs-
Fig. 2. Coordinate
system
to define
pattern position deflections.
data
in terms
of stage
moves
and beam
In practice, the point P will correspond to a precise physical location (such as the gate electrode of a particular MOSFET). Because of the effects of geometrical misalignments and errors, the actual stage move and beam deflection parameters required to access P will be (x,, yJ and (xd, yd). The model that is assumed here is that
(2) and (3) Substituting
(2) and (3) into (1) gives the result on which this scheme is based:
(4)
Note that both stage and deflector terms are combined in one equation. As a result, both are calibrated simultaneously, and it is therefore unnecessary to confine the registration marks to lie within an area no bigger than the deflection field. The objective of the registration process is to calculate values for the unknown coefficients in the 2 x 5 matrix in (4). This is done by comparing the positions of the registration marks specified in the registration data with the positions at which the lithography instrument actually finds them on the wafer
G. Owen I A method for hybrid lithography
98
to be patterned. Having found the values of these coefficients, appropriate stage move and beam deflection parameters for exposing the pattern are computed from the inverted forms of (2) and (3). As it stands, the model will not account for nonlinear effects, such as lens or deflector distortions. Simple extensions which allow such effects to be taken into account are described in Section 6. 4. The registration scheme The chip to be written is surrounded by N registration marks, which may be placed anywhere in the vicinity of the chip. If each mark is to be measured once only, it is necessary that Na 5. (Each mark yields two pieces of information, in the form of a pair of measured coordinates: the values of 10 unknown coefficients are to be found.) Let the pattern data coordinates corresponding to the center of the ith mark be (Xi, Yi). Assume that, in order to position the beam over the center of the mark, the required stage parameters are (Xsi, ysi) and the required deflector parameters are (Xdi, ydi). The values of the registration coefficients a,, b,, ad, bd, and Ax are found in the following manner. Using (l), the quantity Xi can be formed, where Xl = G&i +
b,ysi + &l&i + bdydi + AX.
If there are N registration E = f
(xi
-
(-3
marks, a total squared error can be defined as
x:)‘.
(6)
i=l
The required values of the unknown i.e. they fulfill the condition
aE =_-_=_--~__~___~ aE aE aE a& db, au, dbd Combining
coefficients are those which minimize E,
aE
o
dAx
(7)
’
(5), (6), and (7) gives the result
C C
I 1 c
Xi-%
Xiysi
XiXdi
(8)
9
where
C Xii c
E
1
YsiXst
2
Xdi&i
2
ydixsi
1
c
Xdiysi
1
ydiysi
c
hi
z
“y”i
&ixdi
c
ysixdi
c
xii
1
y$&ii
&;ydi
$
f;ydi
$
XdlYdi
E
;di
&l
SI
Xdr
dr
&i
Nd’
.
(9)
G. Owen I A method for hybrid lithography
99
In these equations, the summations are made over the range 1 G i s N. The values of the remaining unknown coefficients are calculated in an analagous way by forming the error quantity (Yi - Y:), giving the result
.
(10)
5. An example
Figure 3 illustrates the pattern data of a chip measuring 3000 X 2000 pm’. It is surrounded by eight registration marks, labelled u-h. Beam deflections that could be used to find the marks are depicted as arrows and the corresponding stage positions are shown as dots. The measurement of the ten registration coefficients is carried out by accessing each registration mark in turn. To access mark a, the stage parameter are set to (xs = -354, y, = -354) and the beam is deflected to look for a mark in the vicinity of (& = 354, yd = 354). Thus, for this mark, x=0, x, = -354, &, = 354,
Y=O, ys = -354, yd = 354.
Similar sets of values apply for the remaining 7 marks. After all eight marks have been found, the vectors on the right-hand sides of (8) and (10) are calculated, as is the matrix [M] in (9). [M] is then inverted, and a,, b,, c,, d,, ad, bd, cd, dd, Ax, and Ay calculated.
(-3547354)
Fig. 3. A chip, measuring 3000 x 2000 pm’, surrounded by eight registration marks, shown as circles, and denoted by a, 6, c, d, e, f, g, and h. The arrows represent the beam deflections used to access each mark, and the dots labeled with coordinate pairs represent corresponding stage positions (i.e. the positions on the wafer at which the beam would land when undeflected).
G. Owen / A method for hybrid lithography
100
(1500,2500)
(lSOO,-500)
(-500,400)
Fig. 4. A symmetrical
arrangement
(3500,-500)
of registration
conditions
for the chip of Fig. 3.
A restriction exists on the allowable configurations of the registration marks. If it is assumed that the electron lithography instrument and the wafer to be patterned are both perfect, it can be shown that [M] is singular if, for all the registration marks, the values of X,, YS, X,,, and Yd satisfy the same linear equation (see Appendix A). If the instrument or the wafer are not perfect, the matrix is not singular, but it is still ill conditioned. For the symmetrical case of Fig. 4, the linear relationship is tx, + f Y, + 9x,
+ Yd = 1000.
(11)
For the case of Fig. 3, no such relationship exists, and the scheme is well conditioned. An arrangement of marks may be tested by taking any four and deriving an equation of the form of (11) which satisfies their coordinates. If all of the remaining marks also satisfy this equation, then the arrangement is ill conditioned. 6. Extensions of the scheme In practice, the optically printed pattern, the stage of the electron lithography instrument, or its deflection system may suffer from nonlinear distortions. As an example, assume that trapezoidal distortion must be corrected. It is then necessary to modify (4) to
US
b,
f?,
ad
bd
ed
AX
G
d,
fs
cd
dd
fd
Ay
1 . “;,’
yd
Xd yd ‘l-
(12)
G. Owen / A method for hybrid lithography
101
The trapezoidal distortion is accounted for by the additional terms in x,y, and &yd, and the additional coefficients e,, fs, e& and fd. The values of the registration coefficients are given by expressions similar to (8)-(lo), although, because of the greater number of unknowns, additional terms are added to the matrix [M] which increase its order to 7. For the same reason, the minimum allowable number of registration measurements also increase to 7. Further terms may be added in the same way if necessary. For example, to account for isotropic cubic and barrel distortions, these would have the form 3 xs, y,“, x,yz, and xfys for the stage and xi, y& xdy& and xiyd for the deflector. Terms which mix stage and deflector parameters, such as &Xd, &yd, y&, and ysyd can also be added: these particular terms would account for the effect of chip tilt on the characteristics of the deflector. In all these cases, the structure of the scheme remains unchanged, although the order of the matrix [M] increases by one for each pair of additional coefficients. Another straightforward extension of the scheme would allow it to be applied to electron lithography instruments with both magnetic and electrostatic deflection systems (see e.g. [15]). If the subscripts m and e refer to the magnetic and electrostatic systems respectively, then (4) is modified to
b, a,
b,
a,
be
ds
dn,
c,
de_
c,,,
Ay 1 AX
(13)
The determination of the unknown registration coefficients now involves making 7 registration mark measurements and inverting a matrix of order 7. 7. Conclusions The method for hybrid lithography described here is capable of patterning multifield chips onto distorted patterns which have been previously fabricated on nonplanar substrates. Substantial latitude in the number and positioning of the registration marks is permitted, and redundant marks may be used to increase the accuracy of the registration procedure. In its simplest form, the scheme uses a linear registration model: however, it is not difficult to incorporate more complex polynomial models. Appendix A For the matrix [M] to be singular, its determinant must be equal to zero. A general condition that forces this to be the case is that the values of (xsi, ysi,
102 xdi,
G. Owen / A method for hybrid lithography
and ydi) at each registration &i
=
pysi
+
axdi
+
mark all obey a linear relationship
Pydi
+
of the form
ET
(A.11
where CL, (Y, p, and E are constants. consequence of (A.l),
This may be proved
as follows. As a
(A.21 c
Xsiydr
=
p
1
1
xsi
/-b
c
ysi
Substituting (9) gives
=
ysiydi +
a
+ c
ac Xdi
Xdiydi +
p
1
+
p
ydi
cyii
+
+
E 1
Ydir
EN.
(A.2) into the first column of the matrix on the right-hand
side of
det[M] d
E xd, xdiYdi I I
1
ydixsi
1
ydiysi
E C &i
+
’
lC l l
ysi
0
(A-3)
CXdi Cydi
EN
0
&Ydi
In (A.3), only the columns of direct interest have been written out in full-the others are represented by dashed lines. The first determinant on the right-hand side of (A.3) must be equal to zero, since each term in the first column is a factor of Al. greater than the corresponding term in the second column. Similar arguments can be made for the three remaining determinants, and so it follows that de$M] = 0 if (A.l) is obeyed. Under these circumstances,
[M] will be singular.
G. Owen I A method for hybrid lithography
103
References [l] 0. C. Wells, T. E. Everhart and R. K. Matta, Automatic positioning of device electrodes using the scanning electron microscope, IEEE Trans. Election Devices ED-12 (1965) 556-563. [2] E. D. Wolf, W. E. Perkins and P. J. Coane, Device fabrication with the Stereoscan, in: Proc. 3rd Annual Stereoscan SEM Colloquium (Kent, Boston, MA., 1970) 99-107. [3] S. Miyauchi, K. Tanaka and J. C. Russ, Automatic pattern positioning of scanning electron beam exposure, IEEE Trans. Electron Devices ED-17 (1970) 450-457. [4] S. Magdo, M. Hatzakis and C. H. Ting, Electron beam fabrication of micron transistors, IBM J. Res. Develop. 15 (1971) 446-451. [5] F. S. Ozdemir, E. D. Wolf and C. .R. Buckey, Computer-controlled scanning electron microscope for high-resolution microelectronic pattern fabrication, IEEE Trans. Electron Devices ED-19 (1972) 624-628. [6] G. L. Varnell, D. F. Spicer and A. C. Rodger, E-beam writing techniques for semiconductor device fabrication, J. Vat. Sci. Technol. 10 (1973) 1048-1051. [7] N. Saitou, C. Munakata, Y. Miura and Y. Honda, Computer-controlled electron-beam microfabrication machine with a new registration system, J. Phys. E 7 (1974) 441-444. [8] D. E. Davis, R. D. Moore, M. C. Williams and 0. C. Woodard, Automatic registration in an electron-beam lithographic system, IBM J. Res. Develop. 21 (1977) 498-505. [9] 0. Cahen and J. Trotel, High performance step and repeat machine using an electron beam and laser interferometers, in: R. Bakish, ed., Electron and Zon Beam Science and Technology 4th International Conference (The Electrochemical Society, Princeton, NJ, 1970) 581-587. [lo] D. S. AIles, F. R. Ashley, A. M. Johnson and R. L. Townsend, Control system design and alignment methods for electron lithography, J. Vat. Sci. Technol. 12 (1975) 1252-1256. [ll] S. Asai, H. Inomata, A. Yanagisawa, E. Takeda and I. Miwa, Distortion correction and deflection calibration by means of laser interferometry in an electron-beam exposure system, J. Vat. Sci. Technol. 16 (1979) 1710-1714. [12] K. Takamoto, T. Okubo and T. Matsuda, Distortion correction and overlay accuracies achieved by the registration method using two-stage standard mark system, J. VW. Sci. Technol. B 4 (1986) 675-681. [13] L. D. Yau and L. R. Thibault, Direct electron lithographic and circuits, J. Vat. Sci. Technol. 15 (1978) 960-964.
fabrication
of silicon devices
[14] A. D. Wilson, A. Kern, J. Kirk and C. Dooly, Stitching with overlay in direct wafer writing using scanning electron beam, in: R. Bakish, ed., Electron and Zon Beam Science and Technology, 9th Zn~emational Conference (The Electrochemical Society, Princeton, NJ, 1980) 144-151. [15] C. T. Ho, M. S. Michail, W. Stickel and 0. C. Woodard, The high-performance beam deflection system of EL3, J. Vat. Sci. Technol. 19 (1981) 1069-1073.