- Email: [email protected]
A Method for Microprocessor External Digital Circuits Using Programmable Devices
Copyright @ IFAC Programmable Devices and Systems, Ostrava, Czech Republic, 2000
A METHOD FOR MICROPROCESSOR EXTERNAL DIGITAL CIRCUITS USING PROGRAMMABLE DEVICES Wieslaw Wajs, Micbal Kowalczyk, Knysztof Warejko
Institute of Automatics, University of Mining and Metallurgy, Krakow Poland [email protected], Tel. / fax. +4812 634 15 68
Abstract: A method for microprocessor external digital circuits using programmable device is proposed. Each node of the Local Operating Network (LON) is independently working device, and except network communication port, contains I/O port. The paper describes how to build a host interface to the Neuron Chip microprocessor that uses the Microprocessor Interface Program. The Microprocessor Interface Program establishes a fast direct link from the host processor to the Neuron Chip network processor without the Neuron Chip being involved in any application processing. The Neuron Chip parallel I/O object permits bi-directional data transfer at rates of up to 3.3Mbps. Copyright @2000 IFAC
Keywords: Interface, Digital Circuits, AID converters, Object modelling techniques
1.
magtrackl I/O objects can be used to decode a serial data stream from a card - reader device conforming to the use ISO 7811 format, such as credit - card readers. The wiegand I/O object can be used to decode a serial data stream from a Wiegand compatible access control card reader. The touch I/O object can be used to decode a serial data stream from a device compatible with Dallas Semiconductor's Touch I/O protocol.
INTRODUCTION
Microprocessor Motorola 3150 is the central processor unit of the node that is called "Neuron". "Neuron C" is programming language for this chip, and it is based on the ANSII C language. Except most of instructions available in ANSII C it allows random access to hardware resources of the node. The Neuron Chip based node can be used to decode asynchronous serial data coming into the Neuron Chip. The serial I/O object can be used to decode an asynchronous serial data stream into 8-bit characters with start and stop bits at up to 4800 bps. The edgelog I/O object can be used to decode a serial data stream into a series of times for the high and low phases of the data stream. The infrared I/O object can be used to decode a serial data stream from IR remote control devices. The magcard and
2.
ANALOG to DIGITAL CONVERSION
Processing low-level analog signals at high speed might require more robust signal conditioning and high-speed conversion circuitry. Analog to digital conversion techniques can be divided into two distinct classes: direct and indirect. In the direct conversion technique, the analog signal is
59
point. the counter stops incrementing. The N-bit binary number in the counter represents the digital output corresponding to the analog input signal. The counter is then reset and the entire sequence is repeated for the another conversion. The conversion speed of this technique is relatively low due to the inherently slow counting process required. For an Nbit converter, the worst case conversion time is 2tN clock cycles. The counting operation can also be performed by software. The use of software permits design modification at a much lower cost. Using an up-down counter may increase the average conversion speed of the stair-step counter converter. In a servo-type converter, the counter is allowed to count in both directions and track the input analog voltage. This translates the shorter conversion time for small changes in the analog input. For large changes the conversion time approaches that of the original stair-step converter. The tracking counter converter can also be implemented in software. Successive Approximation Converter is direct type conversion scheme. It is similar to the counting type AID converter. The successive approximation register bypasses the long and slow process of incrementing the count sequentially. This is accomplished by toggling each of the N-bits of the digital output one at a time, while monitoring the output of the comparator. Using these techniques, only N cycles are needed for a conversion. Voltage to Frequency Converters is an indirect conversion technique. It transforms the analog signal into the frequency domain. The frequency is then measured with a separate circuit or by a software procedure. The interface between the voltage - to frequency converter block and the frequency measurement blocks a two-wire connection that carries a waveform with the frequency proportional to the amplitude of the input analog signal. This type of conversion techniques is vel)' useful in cases where the analog sensor is physically distanced from the rest of the system. In such case the converter is situated next to source of the analog signal. A connecting pair of wires carries the frequency output to the main system for further processing. The analog signal no longer has to send for a long distance, thus avoiding signal degradation and interference. A variation on the Voltage to Frequency Converters method is the pulse width conversion method. In this technique, the amplitude of the analog signal determines the output pulse width of one shot circuit. The pulse width, as with the frequency in the Voltage to Frequency Converters case, is them measured and appropriately converted to a digital number. In the conversion techniques, a basic assumption was implied about the rate of change of the input
continuously compared to the output of a DfA converter. The DfA converter's input is changed based on the results of the comparison, until the DfA converter's output matches the analog input signal. The input to the DfA converter is then the desired digital output. The various direct conversion schemes differ in the way the input of the DfA converter is changed. With indirect conversion, the analog signal is converted into a time or frequency domain signal that is then measured by the digital logic and converted to a binary value. The following AID conversion schemes can be considered: DualSlope integrating converter, Counting converter, Successive approximation converter, Voltage- tofrequency converter. The actual implementation of this technique can vary significantly from one system to another depending on requirements of the system. Such factors as conversions speed, accuracy, resolution, and linearity and cost all affects the overall design of a particular AID conversion subsystem. A very popular form of the indirect converter, the dual slope-integrating converter incorporates an analog integrator. The input analog signal is first integrated over a fixed period of time. The integrator's input is then switched to the reference voltage, where it is allowed to integrate down while a digital counter is incrementing. The counter is stopped when the integrator's output reaches a preset voltage. The contents of the counter then represent the converted digital value. The dual-slope integrating converter has several important advantages. Because of the complementary nature of the two opposing slopes, the conversion accuracy is independent of the accuracy of both the clock frequency and the integrator capacitor. Due to the inherent nature of the build-in integrator, the output digital value represents an averaging of the analog input signal over the integration period. This makes the converter highly immune to input noise. Dualslope integrating converters are used for slower applications such as environmental monitoring of temperature or humidity. Counting converters is the simplest form of the direct conversion technique. The implementation flexibility of this scheme allows for wide design variations, form an entirely hardware based design to a combined hardware and software implementation. There are two basic types of counting converters: stair step and tracking. In the stair step scheme, the count and control functional block is an N-bit up counter whose counting operation is controlled by the compared output . At the start of the conversion cycle, the counter simply starts counting up from zero until the output of DfA converter equals the input analog signal. At the
60
analog signal. The input signal changes of greater than Y2 LSB during any of the Voltage to Frequency converter and Dual Slope integrating converter which inherently averages the input signal over the integration period. It is assumed that the input is constant, or that the change is so small that it is not recognised by the Analog to Digital converter (e.g. temperature). For a time varying analog signal, there is a need for circuitry that stabilises the input to the Analog to Digital converter while the conversion process is taking place. The simplest approach is to use a low pass filter that discriminates against higher frequencies that fall outside the converter's sampling rate. Analog multiplexers permit the use of only a single Analog to Digital converter, and it's associated a Sample and Hold, for acquiring analog signals from multiple sources. They perform in the analog domain what digital multiplexers do in the digital domain. In any Analog to Digital conversion design, there is a need for a point of reference against which the input signal must be compared. When measuring physical quantities, the analog input is either an absolute signal (e.g. voltage or current) or it is in the form of a varying ratio. In the case of an absolute signal, the converter must be able to measure absolute levels of input. For example, a device, which has a 0 to 0.25 volt output range, must be used with an Analog to Digital converter that can recognise an absolute voltage of 0.125 as the half scale value. 3.
integration periods can be controlled by the keyword (clock) in this object declaration. 4. PARALLEL I/O INrERFACE The Neuron Chip parallel I/O object permits bidirectional data transfer at rates of up to 3.3 Mbps. A Neuron Chip may communicate with any other microprocessor or microcontroller. The Microprocessor Interface Program running on the Neuron Chip provides an easy solution for connecting the Neuron Chip to a microcontroller.
.. ~
Neuron Chip
~
.....
ATMEL 89c2051 micro controller
Fig 1. Master/slave connection for the Neuron® Chip The physical interface to the parallel I/O object is accomplished through the eleven I/O pins of the Neuron Chip. No other I/O objects of the Neuron Chip may be used in conjunction with parallel I/O. 10.0 10.1 ~ 10.2 ~ 10.3 10.4 10.5 10.6 10.7 ...... CS 10.8 ....... 10.9 R/W 10.10 ..... ~ HS
Neuron Chip
NEURON CIDP MICROPROCESSOR
The Neuron Chip supports a dual slope integrating converter through its dual slope input object. One of the internal timer counters of the Neuron Chip is used to control and measure the integration process. This permits a conversion resolution of up to 16 bits at an integration period of 13.11 ms. It is realised at 10 MHz input clock. Faster conversion rates can be attained at the expose of bit resolution. For the dual slope input object the Neuron chip timer counter is set up as both an input and output device. The output signal is used to select the input source for the integrator: either the unknown analog input voltage, or a known reference voltage. The input signal to the timer counter is typically the output of a comparator which is comparing the integrator output to a reference voltage or zero voltage reference. Declaring the dual slope input object will configure a timer counter to perform two important functions: count only when the input signal is active, and the latch the count on the falling edge of the input signal. The maximum value for either of the
~ ~
CS R/W HS
...... ......
~
.....
10.0 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 10.10
ATMEL 89c2051 micro controller
Fig 2. Pin assignments for two nodes
61
and then sends its response (also packet of data) into the node. The structure of sending packets is divided into three following parts: head containing two bytes: address and packet length. Bits of address byte have following meaning: 2 most significant bits specify the place into which device is situated, next 4 bits describes device type, and if we have more than one device of the same type in the same place 2 less significant bits specify device number. The body of sending packet contains requests, commands and data that is sending either by node or external device, control part containing check sum of the packet. Each node has a list of devices that are present in the system. It takes addresses of devices from this list and sends packet of data with commands and requests to desired device. When transmission is finished node takes address of next device and communication starts again. When node is unable to establish communication with one of devices it tries for several times and then sends information about troubles. Each waiting for acknowledges signals are limited by timeout. When timeout is exceeded node breaks communication. and waits for some time and then starts it again. There is no possibility of system suspension. A central heating control system is the first one where the algorithm is working. Thermal comfort is ensured independently for every room, where temperature sensors and valves at heaters are installed (so we need to external devices - sensor and actuator). Every user has ability to set his own desired value temperature. Node gets actual temperature value from sensor device and upon control algorithm determines states of the valve sending desired data to the actuator device. A security and fire-fighting system is another place where that system is working. There are sensors sensible for movement and smoke into each room. External devices are continuously checking states of these sensors, and when they indicate alarms, devices send via parallel Bus information about alert states into node. Then node takes some preventing actions. It is planed to implement more complex algorithm for central heating systems - algorithm optimising energy consumption in the best possible way. Signals from movement sensors can be use as well for this purpose, especially in office rooms. That method allows more efficient control of energy consumption. It is also possible to use other abilities of the LonWorks technology. The DDE Server mechanism allows exchanging the random data among nodes and PC computer, and also among many computers
The Neuron C progranuning language provides several build in function that enable the use of the parallel I/O object without the need for detailed, hardware level knowledge of the handshaking protocol. For increasing design flexibility, the Neuron Chip provides several modes of operation for the parallel I/O object. One of the important restrictions is the quantity of 110 pins. We can typically program eleven lines that can be program as inputs or outputs. Limited number of I/O lines makes impossible to connect as many sensors and actuators directly into the node. Since, the number of devices is very limited. It is possible to build data Bus that is working as the extension of the node's I/O port with external devices connected into it Each of these devices is based on ATMEL 89c2051 microcontroller, and it is responsible for two main things: Bus service i.e. procedures for data exchange, and jobs for each of devices. The solution that is proposed can be described as a low cost automation system. It can be competitive for the end user. It means that the number of nodes has to reach a minimum value into Distributed Control System. Each line of node's I/O port can be declared as one-way line, and we can set 4 lines as data input lines, and also 4 lines as data output lines. In one cycle of transmission (sending the message or receiving the message) we can transmit half-byte (nibble) of information. Except data lines transmission is supported by 3 following control lines: r/w (read / write) - it is driven by node, and determines direction of data flow. When it is low then node sends data. When it is high node reads data transmitted by external device. The cs (chip select) is the line acknowledges that valid data have been send to the Bus or the node has already read the data. The line is also driven by node. The hs (handshake) line also confirms the read/write data status (as cs described above, but it's driven by external devices). Some additional line is not connected to node. It is busy line that external devices use to synchronise among them during simultaneous data reading. Transmission begins when node drives r/w signal into low. This change causes that external interrupt signal appears on each of Bus devices (INTI). All devices response at the same time because interrupt priority is set to the highest of all possible values. First byte of sending packet is receiving by all devices, because it's an address byte. Then it's compared with internal device's address. When it doesn't fit device leaves communication procedures, and waits for next packet. When it fits (there can only be one such device because each has its own unique address value) device reads rest of packet
62
via Internet. It allows remote building control, and it is much pleasant and easier to supervise a building by supervisor.
RERERENCES Parallel I/O Interface to the Neuron Chip (1995) LonWorks® Engineering Bulletin, Echelon Corporation, Palo Alto LonBuilder Microprocessor Interface Program (MIP) User Guide, (1995) LonWorks® Engineering Bulletin, Echelon Corporation 29500/078-0017-01, Palo Alto Wajs W. (1998) "Integracja Systemu LUMEL Cieplo z Siecict LONWORKS" PAK, Warszawa, no 12 pp. 461-463, (in polish) Wajs W. (1998) "Zastosowanie przetwornik6w KFAP S.A. w systemach opartych na technologii LONWORKS" PAK, Warszawa, no. 11 pp. 426-428, (in polish) Wajs W. (1998) "Introduction to the LonWorks Technology" in "Integrated Control Systems and Intelligence Control" TEMPUS JOINT EUROPEAN PROJECT S-JEP-11317-96 Krak6w W. (1998) "Systemy Sterowania Wajs Rozproszonego Laboratorium LONWORKS w AGH w Krakowie" TR Krak6w, (in polish)
63
A METHOD FOR MICROPROCESSOR EXTERNAL DIGITAL CIRCUITS USING PROGRAMMABLE DEVICES Wieslaw Wajs, Micbal Kowalczyk, Knysztof Warejko
Institute of Automatics, University of Mining and Metallurgy, Krakow Poland [email protected], Tel. / fax. +4812 634 15 68
Abstract: A method for microprocessor external digital circuits using programmable device is proposed. Each node of the Local Operating Network (LON) is independently working device, and except network communication port, contains I/O port. The paper describes how to build a host interface to the Neuron Chip microprocessor that uses the Microprocessor Interface Program. The Microprocessor Interface Program establishes a fast direct link from the host processor to the Neuron Chip network processor without the Neuron Chip being involved in any application processing. The Neuron Chip parallel I/O object permits bi-directional data transfer at rates of up to 3.3Mbps. Copyright @2000 IFAC
Keywords: Interface, Digital Circuits, AID converters, Object modelling techniques
1.
magtrackl I/O objects can be used to decode a serial data stream from a card - reader device conforming to the use ISO 7811 format, such as credit - card readers. The wiegand I/O object can be used to decode a serial data stream from a Wiegand compatible access control card reader. The touch I/O object can be used to decode a serial data stream from a device compatible with Dallas Semiconductor's Touch I/O protocol.
INTRODUCTION
Microprocessor Motorola 3150 is the central processor unit of the node that is called "Neuron". "Neuron C" is programming language for this chip, and it is based on the ANSII C language. Except most of instructions available in ANSII C it allows random access to hardware resources of the node. The Neuron Chip based node can be used to decode asynchronous serial data coming into the Neuron Chip. The serial I/O object can be used to decode an asynchronous serial data stream into 8-bit characters with start and stop bits at up to 4800 bps. The edgelog I/O object can be used to decode a serial data stream into a series of times for the high and low phases of the data stream. The infrared I/O object can be used to decode a serial data stream from IR remote control devices. The magcard and
2.
ANALOG to DIGITAL CONVERSION
Processing low-level analog signals at high speed might require more robust signal conditioning and high-speed conversion circuitry. Analog to digital conversion techniques can be divided into two distinct classes: direct and indirect. In the direct conversion technique, the analog signal is
59
point. the counter stops incrementing. The N-bit binary number in the counter represents the digital output corresponding to the analog input signal. The counter is then reset and the entire sequence is repeated for the another conversion. The conversion speed of this technique is relatively low due to the inherently slow counting process required. For an Nbit converter, the worst case conversion time is 2tN clock cycles. The counting operation can also be performed by software. The use of software permits design modification at a much lower cost. Using an up-down counter may increase the average conversion speed of the stair-step counter converter. In a servo-type converter, the counter is allowed to count in both directions and track the input analog voltage. This translates the shorter conversion time for small changes in the analog input. For large changes the conversion time approaches that of the original stair-step converter. The tracking counter converter can also be implemented in software. Successive Approximation Converter is direct type conversion scheme. It is similar to the counting type AID converter. The successive approximation register bypasses the long and slow process of incrementing the count sequentially. This is accomplished by toggling each of the N-bits of the digital output one at a time, while monitoring the output of the comparator. Using these techniques, only N cycles are needed for a conversion. Voltage to Frequency Converters is an indirect conversion technique. It transforms the analog signal into the frequency domain. The frequency is then measured with a separate circuit or by a software procedure. The interface between the voltage - to frequency converter block and the frequency measurement blocks a two-wire connection that carries a waveform with the frequency proportional to the amplitude of the input analog signal. This type of conversion techniques is vel)' useful in cases where the analog sensor is physically distanced from the rest of the system. In such case the converter is situated next to source of the analog signal. A connecting pair of wires carries the frequency output to the main system for further processing. The analog signal no longer has to send for a long distance, thus avoiding signal degradation and interference. A variation on the Voltage to Frequency Converters method is the pulse width conversion method. In this technique, the amplitude of the analog signal determines the output pulse width of one shot circuit. The pulse width, as with the frequency in the Voltage to Frequency Converters case, is them measured and appropriately converted to a digital number. In the conversion techniques, a basic assumption was implied about the rate of change of the input
continuously compared to the output of a DfA converter. The DfA converter's input is changed based on the results of the comparison, until the DfA converter's output matches the analog input signal. The input to the DfA converter is then the desired digital output. The various direct conversion schemes differ in the way the input of the DfA converter is changed. With indirect conversion, the analog signal is converted into a time or frequency domain signal that is then measured by the digital logic and converted to a binary value. The following AID conversion schemes can be considered: DualSlope integrating converter, Counting converter, Successive approximation converter, Voltage- tofrequency converter. The actual implementation of this technique can vary significantly from one system to another depending on requirements of the system. Such factors as conversions speed, accuracy, resolution, and linearity and cost all affects the overall design of a particular AID conversion subsystem. A very popular form of the indirect converter, the dual slope-integrating converter incorporates an analog integrator. The input analog signal is first integrated over a fixed period of time. The integrator's input is then switched to the reference voltage, where it is allowed to integrate down while a digital counter is incrementing. The counter is stopped when the integrator's output reaches a preset voltage. The contents of the counter then represent the converted digital value. The dual-slope integrating converter has several important advantages. Because of the complementary nature of the two opposing slopes, the conversion accuracy is independent of the accuracy of both the clock frequency and the integrator capacitor. Due to the inherent nature of the build-in integrator, the output digital value represents an averaging of the analog input signal over the integration period. This makes the converter highly immune to input noise. Dualslope integrating converters are used for slower applications such as environmental monitoring of temperature or humidity. Counting converters is the simplest form of the direct conversion technique. The implementation flexibility of this scheme allows for wide design variations, form an entirely hardware based design to a combined hardware and software implementation. There are two basic types of counting converters: stair step and tracking. In the stair step scheme, the count and control functional block is an N-bit up counter whose counting operation is controlled by the compared output . At the start of the conversion cycle, the counter simply starts counting up from zero until the output of DfA converter equals the input analog signal. At the
60
analog signal. The input signal changes of greater than Y2 LSB during any of the Voltage to Frequency converter and Dual Slope integrating converter which inherently averages the input signal over the integration period. It is assumed that the input is constant, or that the change is so small that it is not recognised by the Analog to Digital converter (e.g. temperature). For a time varying analog signal, there is a need for circuitry that stabilises the input to the Analog to Digital converter while the conversion process is taking place. The simplest approach is to use a low pass filter that discriminates against higher frequencies that fall outside the converter's sampling rate. Analog multiplexers permit the use of only a single Analog to Digital converter, and it's associated a Sample and Hold, for acquiring analog signals from multiple sources. They perform in the analog domain what digital multiplexers do in the digital domain. In any Analog to Digital conversion design, there is a need for a point of reference against which the input signal must be compared. When measuring physical quantities, the analog input is either an absolute signal (e.g. voltage or current) or it is in the form of a varying ratio. In the case of an absolute signal, the converter must be able to measure absolute levels of input. For example, a device, which has a 0 to 0.25 volt output range, must be used with an Analog to Digital converter that can recognise an absolute voltage of 0.125 as the half scale value. 3.
integration periods can be controlled by the keyword (clock) in this object declaration. 4. PARALLEL I/O INrERFACE The Neuron Chip parallel I/O object permits bidirectional data transfer at rates of up to 3.3 Mbps. A Neuron Chip may communicate with any other microprocessor or microcontroller. The Microprocessor Interface Program running on the Neuron Chip provides an easy solution for connecting the Neuron Chip to a microcontroller.
.. ~
Neuron Chip
~
.....
ATMEL 89c2051 micro controller
Fig 1. Master/slave connection for the Neuron® Chip The physical interface to the parallel I/O object is accomplished through the eleven I/O pins of the Neuron Chip. No other I/O objects of the Neuron Chip may be used in conjunction with parallel I/O. 10.0 10.1 ~ 10.2 ~ 10.3 10.4 10.5 10.6 10.7 ...... CS 10.8 ....... 10.9 R/W 10.10 ..... ~ HS
Neuron Chip
NEURON CIDP MICROPROCESSOR
The Neuron Chip supports a dual slope integrating converter through its dual slope input object. One of the internal timer counters of the Neuron Chip is used to control and measure the integration process. This permits a conversion resolution of up to 16 bits at an integration period of 13.11 ms. It is realised at 10 MHz input clock. Faster conversion rates can be attained at the expose of bit resolution. For the dual slope input object the Neuron chip timer counter is set up as both an input and output device. The output signal is used to select the input source for the integrator: either the unknown analog input voltage, or a known reference voltage. The input signal to the timer counter is typically the output of a comparator which is comparing the integrator output to a reference voltage or zero voltage reference. Declaring the dual slope input object will configure a timer counter to perform two important functions: count only when the input signal is active, and the latch the count on the falling edge of the input signal. The maximum value for either of the
~ ~
CS R/W HS
...... ......
~
.....
10.0 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 10.10
ATMEL 89c2051 micro controller
Fig 2. Pin assignments for two nodes
61
and then sends its response (also packet of data) into the node. The structure of sending packets is divided into three following parts: head containing two bytes: address and packet length. Bits of address byte have following meaning: 2 most significant bits specify the place into which device is situated, next 4 bits describes device type, and if we have more than one device of the same type in the same place 2 less significant bits specify device number. The body of sending packet contains requests, commands and data that is sending either by node or external device, control part containing check sum of the packet. Each node has a list of devices that are present in the system. It takes addresses of devices from this list and sends packet of data with commands and requests to desired device. When transmission is finished node takes address of next device and communication starts again. When node is unable to establish communication with one of devices it tries for several times and then sends information about troubles. Each waiting for acknowledges signals are limited by timeout. When timeout is exceeded node breaks communication. and waits for some time and then starts it again. There is no possibility of system suspension. A central heating control system is the first one where the algorithm is working. Thermal comfort is ensured independently for every room, where temperature sensors and valves at heaters are installed (so we need to external devices - sensor and actuator). Every user has ability to set his own desired value temperature. Node gets actual temperature value from sensor device and upon control algorithm determines states of the valve sending desired data to the actuator device. A security and fire-fighting system is another place where that system is working. There are sensors sensible for movement and smoke into each room. External devices are continuously checking states of these sensors, and when they indicate alarms, devices send via parallel Bus information about alert states into node. Then node takes some preventing actions. It is planed to implement more complex algorithm for central heating systems - algorithm optimising energy consumption in the best possible way. Signals from movement sensors can be use as well for this purpose, especially in office rooms. That method allows more efficient control of energy consumption. It is also possible to use other abilities of the LonWorks technology. The DDE Server mechanism allows exchanging the random data among nodes and PC computer, and also among many computers
The Neuron C progranuning language provides several build in function that enable the use of the parallel I/O object without the need for detailed, hardware level knowledge of the handshaking protocol. For increasing design flexibility, the Neuron Chip provides several modes of operation for the parallel I/O object. One of the important restrictions is the quantity of 110 pins. We can typically program eleven lines that can be program as inputs or outputs. Limited number of I/O lines makes impossible to connect as many sensors and actuators directly into the node. Since, the number of devices is very limited. It is possible to build data Bus that is working as the extension of the node's I/O port with external devices connected into it Each of these devices is based on ATMEL 89c2051 microcontroller, and it is responsible for two main things: Bus service i.e. procedures for data exchange, and jobs for each of devices. The solution that is proposed can be described as a low cost automation system. It can be competitive for the end user. It means that the number of nodes has to reach a minimum value into Distributed Control System. Each line of node's I/O port can be declared as one-way line, and we can set 4 lines as data input lines, and also 4 lines as data output lines. In one cycle of transmission (sending the message or receiving the message) we can transmit half-byte (nibble) of information. Except data lines transmission is supported by 3 following control lines: r/w (read / write) - it is driven by node, and determines direction of data flow. When it is low then node sends data. When it is high node reads data transmitted by external device. The cs (chip select) is the line acknowledges that valid data have been send to the Bus or the node has already read the data. The line is also driven by node. The hs (handshake) line also confirms the read/write data status (as cs described above, but it's driven by external devices). Some additional line is not connected to node. It is busy line that external devices use to synchronise among them during simultaneous data reading. Transmission begins when node drives r/w signal into low. This change causes that external interrupt signal appears on each of Bus devices (INTI). All devices response at the same time because interrupt priority is set to the highest of all possible values. First byte of sending packet is receiving by all devices, because it's an address byte. Then it's compared with internal device's address. When it doesn't fit device leaves communication procedures, and waits for next packet. When it fits (there can only be one such device because each has its own unique address value) device reads rest of packet
62
via Internet. It allows remote building control, and it is much pleasant and easier to supervise a building by supervisor.
RERERENCES Parallel I/O Interface to the Neuron Chip (1995) LonWorks® Engineering Bulletin, Echelon Corporation, Palo Alto LonBuilder Microprocessor Interface Program (MIP) User Guide, (1995) LonWorks® Engineering Bulletin, Echelon Corporation 29500/078-0017-01, Palo Alto Wajs W. (1998) "Integracja Systemu LUMEL Cieplo z Siecict LONWORKS" PAK, Warszawa, no 12 pp. 461-463, (in polish) Wajs W. (1998) "Zastosowanie przetwornik6w KFAP S.A. w systemach opartych na technologii LONWORKS" PAK, Warszawa, no. 11 pp. 426-428, (in polish) Wajs W. (1998) "Introduction to the LonWorks Technology" in "Integrated Control Systems and Intelligence Control" TEMPUS JOINT EUROPEAN PROJECT S-JEP-11317-96 Krak6w W. (1998) "Systemy Sterowania Wajs Rozproszonego Laboratorium LONWORKS w AGH w Krakowie" TR Krak6w, (in polish)
63