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A method for optimizing programmable logic arrays using the simulated annealing algorithm
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iiiiiiiiii~iiiii Microelectronics Journal, 26 (1995) 43-54
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A method for optimizing programmable logic arrays using the
simulated annealing algorithm J . M . Sfinchez 1 and J. Ballesteros 2 IDepartamento de Inform~tica y Autom[itica, Facultad de Fisicas, Universidad Complutense de Madrid, 28040 Madrid, Spain 2Departamento de lnform&ica, Escuela Polit~cnica, Universidad de Extremadura, C&eres, Spain
In this paper we present the programmable logic array (PLA) topological optimization problem using folding techniques. First of all, we consider a multiple unconstrained column folding ;md solve this problem using the Simulated Annealing (SA) algorithm. Afterwardswe extend this algorithm in order to solve several types of constrained foldingproblem. In this way, simple folding is considered as a special case of multiple constrained folding. Bipartite graphs are used to solve the multiple constrained folding problem. Finally, we give some experimental results found by executing the algorithm.
1. Introduction
p
rogrammable logic arrays (PLAs) are building blocks with a regular structure which have proved to be very suitable for VLSI design. Unfortunately, the regularity o f these blocks leads to poor use o f the silicon area and also produces significant delays in their interconnection lines. Therefore, several methods for area reduction have been proposed.
0026-2692/95/$7.00 (,© 1995 Elsevier Science Ltd
First o f all, a logical minimization o f the PLA is carried out in a previous phase o f the design. In this phase, the Boolean equations which represent the basic structure o f the PLA are minimized [1]. But in many cases this logical minimization is insufficient, and a second phase o f reduction must be applied. This second phase, known as topological optimization, consists o f reducing the silicon area by making use o f other techniques, such as partitioning and folding [2-5]. The present w o r k concentrates on the folding technique. This involves placing several columns (rows), called logical columns (rows), in one physical column o f the PLA. If more than two logical columns (rows) are placed in the same physical column (row), the folding is called multiple column folding (multiple row folding); otherwise it is called simple column folding (simple row folding). Both folding types can be
43
J.M. S nchez and J. Ballesteros/Optimizing programmable logic arrays
submitted to different kinds of constraints. Hatchel et al. [2] first presented the PLA folding problem, following which the problem has been considered from many different perspectives. For example, Lewandowsky [6] solves the simple column folding problem by applying the branch and bound algorithm. On the other hand, this problem is modelled in [4] and [7] by means of graphs, and is solved by applying heuristic methods. In this paper we consider only the multiple column folding problem, focussing our attention especially on multiple constrained column folding. We intend not only to optimize the area of the PLA, but also the space occupied by its external connections. The methodology used is based on the simulated annealing (SA) algorithm.
2. The simulated annealing algorithm The simulated annealing (SA) algorithm is based on a strong analogy between the statistical mechanics of annealing in solids and the solution of large combinatorial optimization problems [8]. It can be considered as a general approximation algorithm, with a polynomial upper bound on the computation time. The SA algorithm has an interesting feature which allows it to find high quality solutions which do not depend on the initial solutions [9]. The algorithm works as follows. For negative changes in the cost function (downhill moves), the algorithm accepts the new solution with a probability of 1. For positive changes (uphill moves), the new solutions have the probability
P(j/i) = exp(- ( f (j) - f (i))/c) where i is the present solution, j the next solution, c a cooling control parameter, andf(i) and f ( j ) the cost of solutions i and j respectively. Perhaps one of the most interesting aspects of the SA algorithm is that it can be applied to solve
44
procedure SA
bqin
Initiate So,Mo Calculate Co; k:=O; repeat
/* Initiation phase*/ /* Heating phase */
for I:=l toMk begin PERTURB (state -> state j); Evaluate change ij in function; ifij << t h m a c u e p t ~ e . if ¢xp(ij/C(k)) >> random (O,I) then accept; ilaccept then modify estate j; end; k:=k+l; Calculate Mk c(k+ l):--r c(k) until C(k)_near to zero
/* Calculate M~kov lenght chain*/ / * D c c r ~ temperature */
end;
Fig. l. The simulated annealing algorithm given in pseudoPascal.
a great variety of complex problems (such as optimization of PLAs) in VLSI design. The description of the simulated annealing algorithm in pseudo-Pascal is given in Fig. 1. A special characteristic of the SA algorithm guaranteeing an optimal global solution, is that if the c(k) parameter remains constant over a certain number of transitions, then the algorithm can be modelled as a finite set of homogeneous Markov chains with length Mk [8].
3. Representation of the PLA A PLA is a combinational logic circuit, usually represented by a personality matrix consisting of an input part (the A N D plane of the PLA) and an output part (the O R plane). The rows of the AND plane play the role of product terms in the combinational logic, while the columns represent input variables in the A N D plane or input part of the matrix, or output variables in the O R plane or output part of the matrix. A '1' in both an input column and a product term means that the column is a factor of the product term. A '1' in both an output column and a product term means that the product term is a term of the output. Physically, in the circuit implementation, a '1' represents a transistor, and a '0' an
Microelectronics Journal, Vol. 26, No. 1
| | ) 4 | i ? l t | O
0001011000 0010000100 0000100010 1000000001 0100000010 0011001000 Fig. 2. A PLA personality matrix with 6 input columns, 4 output columns and 6 product terms. empty element [2]. In Fig. 2 a personality matrix with 6 input columns, 4 output columns and 6 product terms is shown.
4. Multiple unconstrained column folding In this section we deal with multiple unconstrained column folding by means of the SA algorithm. Multiple column folding requires the physical columns to be split into several segments. Therefore, a path to route the input and output columns inside the array must be provided. This path is called a connection line. T o place these connection lines in the chip, Micheli et al. [3] put forward two architectures for consideration. In both architectures a connection line is associated with an index i which corresponds to a product term of the PLA. Input variables may connect to the PLA by its left boundary, and output variables by its right boundary. This last assumption implies that the n u m b e r o f product terms must be greater than or equal to that o f the m p u t and output columns. Most PLAs satisfy this condition. However, w h e n it is not satisfied, it may be possible to connect input and output columns to either the b o t t o m or the top of the PLA.
• the solution space to be optimized; • a neighbourhood structure among the solutions; • a cost function associated with each solution o f the space; • a cooling schedule to accelerate the algorithm convergence. 4.1 Solution space Let M be the personality matrix o f a PLA with n product terms, m input columns and s output columns. If we consider n as elements o f a permutation, then there will be n! permutations which correspond to n! different representations o f M. These representations are the solution space S of the optimization problem.
4.2 Neighbourhood structure For each matrix Mi, a solution subspace S i exists, obtained by permutating two rows of the matrix. T h e n u m b e r o f solutions o f Si will be n(n - 1)/2. These are called neighbour solutions. 4.3 Cost function Each c o l u m n , j , o f the PLA personality matrix M can be split into two parts: segment and connection. A segment Ij (1 ~ j ~ m + s) corresponds to the interval (tj', 3~), where tj' a n d ~ are the two external l s o f column j. A connection corresponds to the remaining part o f that column. For each row, i, a peak function p(i) in both planes o f PLA is defined as the n u m b e r of segments that cross row i [10]. Therefore an objective cost function of the PLA will be given by Pm(AND) + P m ( O R )
(1)
where In order to apply the SA algorithm to the multiple unconstrained column folding problem, we must define:
Pm(AND) = m a x i p i ( A N D )
Pm(OR) = maxipi(OR)
for 1 ~< i ~< n
45
J.M. S nchez and J. Ballesteros/Optimizing programmable logic arrays
However, as the SA algorithm is based on a gradual approximation to an optimal solution, it is advisable to choose a more refined cost function in order to estimate the cost of neighbour solutions. We propose the following cost function [11-13]: m+s
F = pm2(AND) + pm2(OR) +
(a/(m + s)) ~ Ij j=l
(2) The goal of the two quadratic terms is to place a higher penalty on solutions with a large value, Pm, in both planes of the PLA. Two quadratic terms have been introduced because they represent, separately, the Cost of the A N D and O R planes of the M matrix, because of the restriction that does not allow fold columns to belong to different planes. The tiaird term, which represents the average value of the length of the segments, is defined taking into account that all configurations with redficed segments will have less probability of being overlapped. The a parameter of this term is used to adjust the value of this third term in the proposed cost function. 4.4 Cooling schedule In order to obtain optimal or quasi-optimal global solutions within a reasonable time, a set of parameters must be provided. Those parameters which contribute to the convergence of the SA algorithm are: the initial value of the temperature, c; the decrement of c; the length, L, of the Markov chains; and the stop criterion.
The initial value of c is computed by heating the system until the accepted ratio (number of accepted solutions/number of explored solutions) approximates to 1. Thus all solutions will have the same accepted probability, and the process will not remain trapped in a local quasioptimal solution [8, 9]. The decrement of the control parameter c is computed by applying the c ( k + l ) = r * c ( k )
46
formula [7], where typical values of r are in the range 0.75 to 0.9 [8]. The length, L, of a Markov chain must not in practice be very great although theoretically a stationary distribution is only guaranteed when the length of a Markov chain is infinite [9]. However, if c decreases very slowly it is possible to reach equilibrium with a small number of transitions; that is, with a shorter length of the chain. In [9] a typical value of L =/Sn/b is proposed, where/Sn/ is the number of neighbour solutions and b a constant for adjusting the length of the chain. Finally, the stop :criterion has been selected taking into account our experimental results. These results recommend halting the algorithm when a maximum of 30 Markov chains have been generated Or when the accepted ratio reaches less than 0.05 [11, 12].
5. Personality matrix compacting After the SA algorithm has been executed, a personality matrix with minimum or quasiminimum cost is obtained. This matrix must later be compacted by applying a compacting algorithm similar to the optimum channel assignment algorithm [14]. The compacting of the PLA personality matrix is carried out in two phases. In the first phase, the A N D plane of the matrix is reduced into a compact space, while in the second the process is repeated with the O R plane. The compacting algorithm comprises several runs on both planes of the personality matrix. In each run, a non-overlapping segment list is created, taking into account that the distance between the top and bottom of a pair of adjacent segments should be minimal. The bottom of each segment represents the cutting point corresponding to physical columns of the PLA which are represented by the respective segments. When
Microelectronics Journal I/ol. 26, No. 1
C5
where m, n and s represent the column n u m b e r of the A N D plane, the row number, and the output number of the PLA respectively. T h e function f~ specifies the position o f an input connection line, while the function f is related to the position o f an output connection line.
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,'- ~ <--
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,
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(b)
Fig. 3. The effect of compaction on a plane of the PLA: (a) before compaction, (b) after compaction. all the segments associated with each column o f a given plane have been selected, the process ends [11]. Figures 3(a) and (b) represent, respectively, a plane o f the PLA befbre and after application o f the compacting algorithm.
6. Multiple constrained column folding T h e problem of multiple constrained column folding can be treated in a similar way to that of multiple unconstrained folding. In this case, it is necessary to provide additional special connection lines for access to the inner segments (logical columns) o f the PLA. These lines must specify the positions o f PLA inputs/outputs w h e n they are made by the left or right b o u n d aries. W e will associate these lines with an index, i, to refer to a specific PLA row. If n is the n u m b e r o f rows o f the PLA, then 1 ~< i ~< n. T h e input and output assignments to their corresponding connection lines will be made by means o f two f u n c t i o n s , f and f , called the direct functions of the input and output assignments. These functions are defined as f : [1,... ,ml ~ [1 . . . . ,n] f : [m + 1 , . . . , m + s ] --* [1 . . . . ,n]
(3)
T h e definition o f these functions imposes the condition that the row n u m b e r of the PLA will be greater than the input and output number. This condition holds for most PLAs, but w h e n this is not the case it is possible to connect the remaining input or output to the top or b o t t o m o f the PLA instead of to its lateral boundaries. This implies the introduction o f additional constraints. All these constraints must be expressed in terms o f the above functions. However, in order to handle a special type o f constraint, two further functions are introduced, f -1 a n d f -1 , called the inverse functions o f the input and output assignments. These new functions map each connection line with an input or output o f the PEA as follows:
f-l: [1,... ,n] --~ [0, 1 , . . . ,ml f-1 [1,... ,n] --* [0, m + 1 . . . . .
(4) m + s]
where m, n and s are the same as i n f a n d f . Taking the previous definitions into account, the constraints on column folding may be classified into two major groups: rigid and smooth constraints. In the first group, t h e f a n d f functions have a fixed value, while in the second f and f may be modified according to the smoothness of the given constraints [11-13]. In both approaches it is necessary to modify the concept o f a segment. In unconstrained folding, a segment corresponds to the part of the column o f the personality matrix between the two external l s o f the column. However, in constrained folding the segments must be
47
J.M. Sanchez and J. Ballesteros/Optimizing programmable logic arrays
defined according to the values o f ~ and ~. Therefore, iff~(j) < tj ( ~ ( j ) < tj), the segments are redefined as:
Ij
= [f~(j),jy]
(Ij
= [fs(j),d]);
(5)
that is, the segments must be enlarged from the top end. O n the contrary, if f ( J ) > d ( ~ ( j ) >fi), the segments must be enlarged from the b o t t o m end. W h e n f~ and ~ assume values between the tj and fi boundaries, the segments remain unchanged. 6.1 Rigid constraints Within this group three types of constraint are distinguishable: (a) ordered connection line assignment, (b) ordered connection line assignment with top-bottom I/O lines, and (c) topbottom I/O line assignment (also called simple folding). Similar constraints have been considered previously in [3] and [5].
6. 1.1 Ordered connection line assignment This is the simplest category o f constraints. Inputs are placed on the left boundary of the PLA and outputs on the right (Fig. 4(a)). For all inputs and outputs a fixed order is established, specified by the f,, and ~ functions as follows:
f~(j) = i, Vj: 1 . . . m, Vi: 1 . . . n
(6a)
~ ( j ) = i, Vj: m + 1 . . . m + s, Vi: 1 . . . n
(6b)
where i is an index for rows and j an index for columns. T h e values whichf~ a n d ~ adopt must not change during the optimization process. For this reason, moves must consist only of product terms interchanges. However,f~ a n d ~ might n o w influence the cost function, owing to the segment redefinition. This type o f assignment is o p t i m u m with respect to the PLA connection lines, but nevertheless is excessively rigid and in most cases yields unacceptable results.
OR
AND Cr
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(a) ° Ck
48
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Fig. 4. Ordered line assigmnents: (a) inputs on left, outputs on right; (b) as (a) but with additional input and output columns; (c) all inputs at top and bottom.
6. 1.2 Ordered connection line assignment with top-bottom I/0 lines In this case the inputs (or outputs) placed on the left (right) boundaries have a fixed order, as in the previous case. However, in this case there are a further two sets o f input/output columns. In the first, the columns are connected to the top of
Microelectronics Journal, Vol. 26, No. 1
the PLA (row 1 of the array), while in the second they are connected to row n (Fig. 4(b)). These constraints may be dealt with simply. I f j is an input [output] column of the top set, then we assign to r e ( j ) [ f ( j ) ] the row 1. If on the other hand j is an input [output] column of the bottom set, then w e assign to these functions the row n. These values must be established at the outset of the annealing process, and must remain unchanged throughout, so that the desired connection is guaranteed. The values o f ~ a n d f in the remaining PLA columns must also remain unchanged. This type of constraint may be very advantageous when the PLA is to be connected to other blocks placed above or below it. 6.1.3 Top-bottom I/0 line assignment This may be considered a particular case of the previous category, where the union of the top and bottom columns is equal to the whole set of input/output columns. Therefore, the only possible assignations a r e : f ~ ( j ) = 1 a n d f ( j ) = 1 (top set), o r f , ( j ) = n a n d f ( j ) = n (bottom set). Obviously, this may be viewed as a simple constrained folding. 'This new type of folding is usually superior to simple folding in offering greater reduction of the area needed to make the routing. This constraint is treated in the same way as cases (a) and (b). 6.2 Smooth constraints The constraints considered so far do not lead to an acceptable reduction of PLA area, although it is possible to reduce the area for the routing. This implies a need to establish a trade-off between the area saving corresponding to the internal structure of" the PLA and that corresponding to the external routing. In order to achieve this it is advisable to relax the constraints, and allow each input/output column to be assigned to more than one line position. Such assignments must be bounded by two line positions, with assignments outside these limits being forbidden.
The treatment of smooth constraints may be approached either by defining a global space of solutions, adding a penalty term to the previous cost function, or by defining a smaller subspace whose solutions (valid solutions) satisfy the given constraints. Wong [15] solves this problem by applying the first technique. We have used the second, to avoid spending time in the computation of solutions that will later be rejected. Further, this alternative does not require any penalty term to be added to the cost function, decreasing the computation time of this function. The only disadvantage is that in some cases a special mechanism (assignment mechanism) must be used for moving between valid solutions. We have considered the following types of smooth constraint: (a) bounded connection line assignment, and (b) bounded connection line assignment with top-bottom input/output lines. 6.2.1 Bounded connection line assignment Although it is not necessary to modify the cost function, we must assign each input or output to a set of connection lines in the PLA. Any assignation outside these limits will not comply with the constraints. In this group the imposed constraints are specified by four arrays: Pi, Ui, Po and Uo. Each component, Pi(j) and Ui(j), 1 <<.j <<,m, represents the first and the last position respectively which is assigned to input j of the PLA. The components Po(j) and Uo(j), m + 1 <~j <<,m + s, represent the same with respect to o u t p u t j of the PLA. This is illustrated in Fig. 5(a). 6.2.2 Bounded connection line assignment with top-bottom input/output lines In this group there are input/output columns connected by the top of the PLA [ f ~ ( j ) ~ ( j ) = 1], by the bottom [ f ~ ( j ) ~ ( j ) = n], or by the lateral boundaries. This last case is treated identically to the above group of smooth constraints and is illustrated in Fig. 5(b).
49
J.M. S nchez and J. Ballesteros/Optimizing programmable logic arrays
C! .
Pi(j)<~i<~Ui(j)
( !
~ |
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t (b) Fig. 5. Bounded connection line assignments: (a) without top and bottom input/output lines, (b) with top and bottom input/output lines.
7. The assignment mechanism T h e assignment mechanism has particular relevance owing to its centrality to the algorithm performance. T h e mechanism is based on a pair o f bipartite graphs built from the arrays discussed above. From the Pi, Ui, Po and Uo arrays a pair o f bipartite graphs Gi(A, I, Ei) and Go(A, O, Eo) are built. T h e set I o f the first graph contains the nodes uj which represent the inputsj o f the PLA. T h e set O o f the second graph contains the nodes uj which represent the outputs j o f the PLA. T h e set A contains the nodes vi which correspond to rows of the PLA. Each node uj belonging to I, ui belonging to O, is connected to a node vj belonging to A if
50
form+l
<~j<~m+s
T h e set o f edges in the graphs Gi and Go are therefore defined as follows:
Ei = [(ui, vi)/Pi(j) <~ i <~ Ui(j)] for 1 ~
(7a)
Eo = [(ui, vi/Po(j ) ~ i <~ Uo(j)] for m + 1 <~j<~m+s, 1 <~i<~n;
(7b)
q
'
c~
Cm'l I,,.
I,
I
and
Po(j)<~ i<~ Uo(j)
OR
AND
•
for l ~ < j ~ < m
that is, each node ui belonging to I[0] is connected to a node vi belonging to the set o f connection lines A, if the connection line i is within the range o f limits established by the vectors Pi and Ui [Po and Uo]. O n c e Gi and Go have been built, the next step is to simplify them. This simplification is also used to check the correctness o f the initial constraints. T h e simplification procedure is: each time a node Ui with degree 1 is found, the corresponding node vi belonging to the set A o f connection lines is accepted. T h e n the remaining edges of vi are deleted. This process is repeated until all nodes with degree 1 have been detected. If w h e n the process ends, a node uj with degree 0 is found, then the initial constraints have been incorrectly specified. After the reduction o f Gi and Go has been completed, two new bipartite graphs G/red and Gored are formed. From these simplified graphs an initial valid solution is established by setting the functions f~ and f to an arbirary value. The SA algorithm is then run. Let us consider an example. If the PLA represented by the personality matrix in Fig. 2 is submitted to the constraints Pi = (1,1,2,3,4,6), Ui=(1,2,3,6,6,6), P o = ( 1 , 2 , 4 , 6 ) and U o = (3,4,6,6), we obtain the input connection graph
Microelectronics Journal, Vol. 26, No. 1
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Fig. 7. As Fig. 6, but with alternative constraints; see text.
Fig. 6. The example PLA of Fig. 2: (a) input connection graph, (b) output connection graph, (c) resultant simplified input connection graph, (d) resultant simplified output connection graph.
Gi (A, I, Ei) and the output connection graph Go (A, O, Eo) represented in Figs. 6(a) and (b) respectively. As we can see, inputs 1 and 6 can only be assigned to the first and last connection lines respectively (both in the A N D plane) and
output 10 to connection line 6 (in the OR.
plane). From these graphs, we obtain the two new simplified graphs G/red and Gored shown in Figs. 6(c) and (d), after the redundant edges o f the first graphs have been removed. The thick lines in G/red and Gored correspond to the initial values assigned to f, a n d f respectively. As a further example, we now take the same PLA above, but with the following constraints corresponding to Section 6.2.2:
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J.M. Sanchez and J. Ballesteros/Optimizing programmable logic arrays
TABLE 1 Results corresponding to multiple unconstrained folding; n = row number, m = input number, s = output number, k = Markov chain number generated, F.R. = final reduction of personality matrix of the corresponding PLA n
PLA1 PLA2 PLA3 PLA4 PLA5 PLA6 PLA7
17 20 22 25 30 30 52
m+ s
10 30 36 42 40 42 42
R_EDUCTION k= 5
10
15
20
25
30
F.R.
70.0 46.7 77.8 57.1 60.0 61.9 69.0
70.0 33.3 52.8 45.2 55.5 47.6 69.0
60.0 33.3 44.4 42.9 50.0 42.9 54.8
40.0 23.3 44.4 38.1 32.5 38.1 52.4
40.0 20.0 38.9 38.1 25.0 38.1 50.0
40.0 16.7 38.9 38.1 25.0 38.1 50.0
40.0 16.7 36.1 38.1 25.0 38.1 50.0
Pi = ( 1 , - , 2 , - , 4 , - , 6), Ui = ( 1 , - , 3 , - , 6, 6), Po = ( - , 2 , 4 , - ) and Uo = ( - , 4 , 6 , - ) ; f~(2) = 1 , f ( 4 ) = 6 , f ( 7 ) = 6 and f ( 1 0 ) = 1 The graphs Gi, Go, G/red and Gored are shown in Figs. 7(a), (b), (c) and (d) respectively. T o assign input/output columns to connection lines a further procedure is required to be implemented. This procedure must be executed during the annealing process every time the system is perturbed. The aim o f this procedure is to assign random correct values to the previously defined functions according to the structure o f the simplified graphs. W h e n the number o f inputs or outputs is less than the number o f product terms and the algorithm finds a node such as f~-l(vi) = O, f-l(vi) = 0, the procedure needs little time. Only in the most complicated cases will it have to spend longer computing input or output assignments [11]. 8. E x p e r i m e n t a l results
In this work we have dealt with the multiple constrained and unconstrained column folding o f PLAs using the Simulated Annealing algorithm. Table 1 shows some experimental results obtained from the solution o f the multiple unconstrained column folding problem. These
52
results basically depend on the initial sparsity o f the PLA personality matrix and indicate that it is possible to obtain acceptable solutions when the number o f Markov chains is not very large. Several o f the PLAs in Table 1 have been folded with various types o f constraints. PLA7 [2], which is shown in Fig. 8(a), has been submitted to the following smooth constraints: Top inputs : 1, 2, 3. Bottom inputs: 4, 6, 8, 10, 12 Top outputs: 24, 25, 26, 27. Bottom outputs: 38, 39,40, 41, 42. inputs 5 7 911 13 14 15 16 17 18 19 20 21 22 23 Pl: 2 2 2 2 2 2 9 9 9 9 9 9203045 Ui: 9 9 9 9 915202020253040405050 Outputs 28 29 30 31 32 33 34 35 36 37 Po: 2 3 3 3 3 3 3 3 3 3 Uo : 2 30 30 30 30 30 30 40 40 50
The resultant reduced PLA is given in Fig. 8(b), which shows that m + s has been reduced from 42 to 23, thus producing a size reduction to 54% o f the original.
9. C o n c l u s i o n s
In this w o r k we have focussed our attention on multiple constrained column folding. In order to solve this problem we have used the same cost
Microelectronics Journal, Vol. 26, No. 1
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1} 13) 2) 42) 31) 37) 28) 21) 17)
Fig. 8. Minimization of example PLA 7 [2]: (a) given PLA, n = 52, m + s = 42; (b) reduced PLA with given constraints n = 52, m +s = 23.
function proposed for the multiple u n c o n strained folding problem, w i t h o u t adding any penalizing term, but w i t h a m o r e reduced solution space appropriate for all solutions that comply w i t h the constraints. +From this statem e n t o f the problem we have i m p l e m e n t e d a mechanism for assignment o f c o n n e c t i o n lines. This mechanism has been modelled from a pair o f bipartite graphs, called i n p u t - o u t p u t c o n n e c tion graphs.
References
[l] R. Brayton, G. Hachtel, C. McMullen and A. Sangiovanni-Vincentelli, Logic Minimization Algorithms .for VLSI Synthesis, Kluwer Academic Publishers, 1984. [2] G.D. Hachtel, A.R.. Newton and A. SangiovanniVincentelli, Some results in optimal PLA folding, I E E E Int. Conf. on Circuits and Computers, O c t . 1 9 8 0 , [3]
pp. 1023-1026. G. De Micheli and A. Sangiovanni-Vincentelli, Multiple constrained folding of programmable logic
53
J.M. Sanchez and J. Ballesteros/Optimizing programmable logic arrays
arrays: theory and applications, IEEE Trans. on Comp. Aided Design, Cad-2(3) (1983) 151-166. [4] J.M. S:inchez,J. Ballesteros and A. Vaquero, A graphbased method for PLAs folding, 7th lasted International Symposium, Switzerland, Feb. 1989, 136-139. [5] J. Hennessy, Partitioning Programmable Logic Arrays, IEEE I C C A D (1983) 180-181. [6] J. Lewandowski and C. Liu, A branch and bound algorithm for optimal PLA folding, IEEE 21st DAC, (1984) pp. 426-431. [7] J. Lecky, O.J. Murphy and I<. Absher, Graph theoretic algorithms for the PLA folding problem, IEEE Trans. Computer Aided Design, 8(9) (1989) 1014-1021. [8] S. Kirkpatrick, C.D. Gelatt and M.P. Vecchi, Optimization by simulated annealing, Science 220 (1983) 671-680. [9] A. Aarts and J. Korst, Simulated Annealing and Boltzmann Machines: A Stochastic Approach to Combinatorial Optimization and Neural Computing, John Wiley and Sons, Chichester, 1989.
54
110] J.F. Paillotin, Optimization of the PLA area, Proc. 18th Design Automation Conf. (1981) 406-410. [11] J. Ballesteros, Una contribuci6n a la optimizaci6n topol6gica de Arrays L6gicos Programables, Doctoral Thesis, Universidad Complutense de Madrid, April 1991. [12] J. Ballesteros and J.M. Sfinchez, Multiple constrained folding of programmable logic arrays by simulated annealing, IEEE Mediterranean Electrotechnical Conference, Ljubljana, May 1991, 977-980. [13] J.M. Sfinchez and J. Ballesteros, Simulated annealing for folding of programmable logic arrays, Coll. on Synthesis and Optimisation of Logic Systems, IEE Digest 1994/066, 7/1-7/4. [14] A. Hashimoto and J. Stevens, Wire routing by optimizing channel assignment within large apertures, 8th ACM/IEEE Design Automation Workshop, 1971, 214-224. [15] D.F. Wong, H.W. Leong and C.L. Liu, Simulated Annealing for VLSI Design, Kluwer AP, 1988.
iiiiiiiiii~iiiii Microelectronics Journal, 26 (1995) 43-54
i!i~i~ii!~iiii!
iiiiiii~iiiiii!~il
A method for optimizing programmable logic arrays using the
simulated annealing algorithm J . M . Sfinchez 1 and J. Ballesteros 2 IDepartamento de Inform~tica y Autom[itica, Facultad de Fisicas, Universidad Complutense de Madrid, 28040 Madrid, Spain 2Departamento de lnform&ica, Escuela Polit~cnica, Universidad de Extremadura, C&eres, Spain
In this paper we present the programmable logic array (PLA) topological optimization problem using folding techniques. First of all, we consider a multiple unconstrained column folding ;md solve this problem using the Simulated Annealing (SA) algorithm. Afterwardswe extend this algorithm in order to solve several types of constrained foldingproblem. In this way, simple folding is considered as a special case of multiple constrained folding. Bipartite graphs are used to solve the multiple constrained folding problem. Finally, we give some experimental results found by executing the algorithm.
1. Introduction
p
rogrammable logic arrays (PLAs) are building blocks with a regular structure which have proved to be very suitable for VLSI design. Unfortunately, the regularity o f these blocks leads to poor use o f the silicon area and also produces significant delays in their interconnection lines. Therefore, several methods for area reduction have been proposed.
0026-2692/95/$7.00 (,© 1995 Elsevier Science Ltd
First o f all, a logical minimization o f the PLA is carried out in a previous phase o f the design. In this phase, the Boolean equations which represent the basic structure o f the PLA are minimized [1]. But in many cases this logical minimization is insufficient, and a second phase o f reduction must be applied. This second phase, known as topological optimization, consists o f reducing the silicon area by making use o f other techniques, such as partitioning and folding [2-5]. The present w o r k concentrates on the folding technique. This involves placing several columns (rows), called logical columns (rows), in one physical column o f the PLA. If more than two logical columns (rows) are placed in the same physical column (row), the folding is called multiple column folding (multiple row folding); otherwise it is called simple column folding (simple row folding). Both folding types can be
43
J.M. S nchez and J. Ballesteros/Optimizing programmable logic arrays
submitted to different kinds of constraints. Hatchel et al. [2] first presented the PLA folding problem, following which the problem has been considered from many different perspectives. For example, Lewandowsky [6] solves the simple column folding problem by applying the branch and bound algorithm. On the other hand, this problem is modelled in [4] and [7] by means of graphs, and is solved by applying heuristic methods. In this paper we consider only the multiple column folding problem, focussing our attention especially on multiple constrained column folding. We intend not only to optimize the area of the PLA, but also the space occupied by its external connections. The methodology used is based on the simulated annealing (SA) algorithm.
2. The simulated annealing algorithm The simulated annealing (SA) algorithm is based on a strong analogy between the statistical mechanics of annealing in solids and the solution of large combinatorial optimization problems [8]. It can be considered as a general approximation algorithm, with a polynomial upper bound on the computation time. The SA algorithm has an interesting feature which allows it to find high quality solutions which do not depend on the initial solutions [9]. The algorithm works as follows. For negative changes in the cost function (downhill moves), the algorithm accepts the new solution with a probability of 1. For positive changes (uphill moves), the new solutions have the probability
P(j/i) = exp(- ( f (j) - f (i))/c) where i is the present solution, j the next solution, c a cooling control parameter, andf(i) and f ( j ) the cost of solutions i and j respectively. Perhaps one of the most interesting aspects of the SA algorithm is that it can be applied to solve
44
procedure SA
bqin
Initiate So,Mo Calculate Co; k:=O; repeat
/* Initiation phase*/ /* Heating phase */
for I:=l toMk begin PERTURB (state -> state j); Evaluate change ij in function; ifij << t h m a c u e p t ~ e . if ¢xp(ij/C(k)) >> random (O,I) then accept; ilaccept then modify estate j; end; k:=k+l; Calculate Mk c(k+ l):--r c(k) until C(k)_near to zero
/* Calculate M~kov lenght chain*/ / * D c c r ~ temperature */
end;
Fig. l. The simulated annealing algorithm given in pseudoPascal.
a great variety of complex problems (such as optimization of PLAs) in VLSI design. The description of the simulated annealing algorithm in pseudo-Pascal is given in Fig. 1. A special characteristic of the SA algorithm guaranteeing an optimal global solution, is that if the c(k) parameter remains constant over a certain number of transitions, then the algorithm can be modelled as a finite set of homogeneous Markov chains with length Mk [8].
3. Representation of the PLA A PLA is a combinational logic circuit, usually represented by a personality matrix consisting of an input part (the A N D plane of the PLA) and an output part (the O R plane). The rows of the AND plane play the role of product terms in the combinational logic, while the columns represent input variables in the A N D plane or input part of the matrix, or output variables in the O R plane or output part of the matrix. A '1' in both an input column and a product term means that the column is a factor of the product term. A '1' in both an output column and a product term means that the product term is a term of the output. Physically, in the circuit implementation, a '1' represents a transistor, and a '0' an
Microelectronics Journal, Vol. 26, No. 1
| | ) 4 | i ? l t | O
0001011000 0010000100 0000100010 1000000001 0100000010 0011001000 Fig. 2. A PLA personality matrix with 6 input columns, 4 output columns and 6 product terms. empty element [2]. In Fig. 2 a personality matrix with 6 input columns, 4 output columns and 6 product terms is shown.
4. Multiple unconstrained column folding In this section we deal with multiple unconstrained column folding by means of the SA algorithm. Multiple column folding requires the physical columns to be split into several segments. Therefore, a path to route the input and output columns inside the array must be provided. This path is called a connection line. T o place these connection lines in the chip, Micheli et al. [3] put forward two architectures for consideration. In both architectures a connection line is associated with an index i which corresponds to a product term of the PLA. Input variables may connect to the PLA by its left boundary, and output variables by its right boundary. This last assumption implies that the n u m b e r o f product terms must be greater than or equal to that o f the m p u t and output columns. Most PLAs satisfy this condition. However, w h e n it is not satisfied, it may be possible to connect input and output columns to either the b o t t o m or the top of the PLA.
• the solution space to be optimized; • a neighbourhood structure among the solutions; • a cost function associated with each solution o f the space; • a cooling schedule to accelerate the algorithm convergence. 4.1 Solution space Let M be the personality matrix o f a PLA with n product terms, m input columns and s output columns. If we consider n as elements o f a permutation, then there will be n! permutations which correspond to n! different representations o f M. These representations are the solution space S of the optimization problem.
4.2 Neighbourhood structure For each matrix Mi, a solution subspace S i exists, obtained by permutating two rows of the matrix. T h e n u m b e r o f solutions o f Si will be n(n - 1)/2. These are called neighbour solutions. 4.3 Cost function Each c o l u m n , j , o f the PLA personality matrix M can be split into two parts: segment and connection. A segment Ij (1 ~ j ~ m + s) corresponds to the interval (tj', 3~), where tj' a n d ~ are the two external l s o f column j. A connection corresponds to the remaining part o f that column. For each row, i, a peak function p(i) in both planes o f PLA is defined as the n u m b e r of segments that cross row i [10]. Therefore an objective cost function of the PLA will be given by Pm(AND) + P m ( O R )
(1)
where In order to apply the SA algorithm to the multiple unconstrained column folding problem, we must define:
Pm(AND) = m a x i p i ( A N D )
Pm(OR) = maxipi(OR)
for 1 ~< i ~< n
45
J.M. S nchez and J. Ballesteros/Optimizing programmable logic arrays
However, as the SA algorithm is based on a gradual approximation to an optimal solution, it is advisable to choose a more refined cost function in order to estimate the cost of neighbour solutions. We propose the following cost function [11-13]: m+s
F = pm2(AND) + pm2(OR) +
(a/(m + s)) ~ Ij j=l
(2) The goal of the two quadratic terms is to place a higher penalty on solutions with a large value, Pm, in both planes of the PLA. Two quadratic terms have been introduced because they represent, separately, the Cost of the A N D and O R planes of the M matrix, because of the restriction that does not allow fold columns to belong to different planes. The tiaird term, which represents the average value of the length of the segments, is defined taking into account that all configurations with redficed segments will have less probability of being overlapped. The a parameter of this term is used to adjust the value of this third term in the proposed cost function. 4.4 Cooling schedule In order to obtain optimal or quasi-optimal global solutions within a reasonable time, a set of parameters must be provided. Those parameters which contribute to the convergence of the SA algorithm are: the initial value of the temperature, c; the decrement of c; the length, L, of the Markov chains; and the stop criterion.
The initial value of c is computed by heating the system until the accepted ratio (number of accepted solutions/number of explored solutions) approximates to 1. Thus all solutions will have the same accepted probability, and the process will not remain trapped in a local quasioptimal solution [8, 9]. The decrement of the control parameter c is computed by applying the c ( k + l ) = r * c ( k )
46
formula [7], where typical values of r are in the range 0.75 to 0.9 [8]. The length, L, of a Markov chain must not in practice be very great although theoretically a stationary distribution is only guaranteed when the length of a Markov chain is infinite [9]. However, if c decreases very slowly it is possible to reach equilibrium with a small number of transitions; that is, with a shorter length of the chain. In [9] a typical value of L =/Sn/b is proposed, where/Sn/ is the number of neighbour solutions and b a constant for adjusting the length of the chain. Finally, the stop :criterion has been selected taking into account our experimental results. These results recommend halting the algorithm when a maximum of 30 Markov chains have been generated Or when the accepted ratio reaches less than 0.05 [11, 12].
5. Personality matrix compacting After the SA algorithm has been executed, a personality matrix with minimum or quasiminimum cost is obtained. This matrix must later be compacted by applying a compacting algorithm similar to the optimum channel assignment algorithm [14]. The compacting of the PLA personality matrix is carried out in two phases. In the first phase, the A N D plane of the matrix is reduced into a compact space, while in the second the process is repeated with the O R plane. The compacting algorithm comprises several runs on both planes of the personality matrix. In each run, a non-overlapping segment list is created, taking into account that the distance between the top and bottom of a pair of adjacent segments should be minimal. The bottom of each segment represents the cutting point corresponding to physical columns of the PLA which are represented by the respective segments. When
Microelectronics Journal I/ol. 26, No. 1
C5
where m, n and s represent the column n u m b e r of the A N D plane, the row number, and the output number of the PLA respectively. T h e function f~ specifies the position o f an input connection line, while the function f is related to the position o f an output connection line.
C6 CI
,, J%
(
C3 C2
Ni /%
,'- ~ <--
c,
/,
Cs
(~
.4..
_v_ ].
,
C4
(a)
(b)
Fig. 3. The effect of compaction on a plane of the PLA: (a) before compaction, (b) after compaction. all the segments associated with each column o f a given plane have been selected, the process ends [11]. Figures 3(a) and (b) represent, respectively, a plane o f the PLA befbre and after application o f the compacting algorithm.
6. Multiple constrained column folding T h e problem of multiple constrained column folding can be treated in a similar way to that of multiple unconstrained folding. In this case, it is necessary to provide additional special connection lines for access to the inner segments (logical columns) o f the PLA. These lines must specify the positions o f PLA inputs/outputs w h e n they are made by the left or right b o u n d aries. W e will associate these lines with an index, i, to refer to a specific PLA row. If n is the n u m b e r o f rows o f the PLA, then 1 ~< i ~< n. T h e input and output assignments to their corresponding connection lines will be made by means o f two f u n c t i o n s , f and f , called the direct functions of the input and output assignments. These functions are defined as f : [1,... ,ml ~ [1 . . . . ,n] f : [m + 1 , . . . , m + s ] --* [1 . . . . ,n]
(3)
T h e definition o f these functions imposes the condition that the row n u m b e r of the PLA will be greater than the input and output number. This condition holds for most PLAs, but w h e n this is not the case it is possible to connect the remaining input or output to the top or b o t t o m o f the PLA instead of to its lateral boundaries. This implies the introduction o f additional constraints. All these constraints must be expressed in terms o f the above functions. However, in order to handle a special type o f constraint, two further functions are introduced, f -1 a n d f -1 , called the inverse functions o f the input and output assignments. These new functions map each connection line with an input or output o f the PEA as follows:
f-l: [1,... ,n] --~ [0, 1 , . . . ,ml f-1 [1,... ,n] --* [0, m + 1 . . . . .
(4) m + s]
where m, n and s are the same as i n f a n d f . Taking the previous definitions into account, the constraints on column folding may be classified into two major groups: rigid and smooth constraints. In the first group, t h e f a n d f functions have a fixed value, while in the second f and f may be modified according to the smoothness of the given constraints [11-13]. In both approaches it is necessary to modify the concept o f a segment. In unconstrained folding, a segment corresponds to the part of the column o f the personality matrix between the two external l s o f the column. However, in constrained folding the segments must be
47
J.M. Sanchez and J. Ballesteros/Optimizing programmable logic arrays
defined according to the values o f ~ and ~. Therefore, iff~(j) < tj ( ~ ( j ) < tj), the segments are redefined as:
Ij
= [f~(j),jy]
(Ij
= [fs(j),d]);
(5)
that is, the segments must be enlarged from the top end. O n the contrary, if f ( J ) > d ( ~ ( j ) >fi), the segments must be enlarged from the b o t t o m end. W h e n f~ and ~ assume values between the tj and fi boundaries, the segments remain unchanged. 6.1 Rigid constraints Within this group three types of constraint are distinguishable: (a) ordered connection line assignment, (b) ordered connection line assignment with top-bottom I/O lines, and (c) topbottom I/O line assignment (also called simple folding). Similar constraints have been considered previously in [3] and [5].
6. 1.1 Ordered connection line assignment This is the simplest category o f constraints. Inputs are placed on the left boundary of the PLA and outputs on the right (Fig. 4(a)). For all inputs and outputs a fixed order is established, specified by the f,, and ~ functions as follows:
f~(j) = i, Vj: 1 . . . m, Vi: 1 . . . n
(6a)
~ ( j ) = i, Vj: m + 1 . . . m + s, Vi: 1 . . . n
(6b)
where i is an index for rows and j an index for columns. T h e values whichf~ a n d ~ adopt must not change during the optimization process. For this reason, moves must consist only of product terms interchanges. However,f~ a n d ~ might n o w influence the cost function, owing to the segment redefinition. This type o f assignment is o p t i m u m with respect to the PLA connection lines, but nevertheless is excessively rigid and in most cases yields unacceptable results.
OR
AND Cr
Cr
(a) ° Ck
48
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AND
~Cr
-I llk,rlm
T
°
"
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,...,
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Fig. 4. Ordered line assigmnents: (a) inputs on left, outputs on right; (b) as (a) but with additional input and output columns; (c) all inputs at top and bottom.
6. 1.2 Ordered connection line assignment with top-bottom I/0 lines In this case the inputs (or outputs) placed on the left (right) boundaries have a fixed order, as in the previous case. However, in this case there are a further two sets o f input/output columns. In the first, the columns are connected to the top of
Microelectronics Journal, Vol. 26, No. 1
the PLA (row 1 of the array), while in the second they are connected to row n (Fig. 4(b)). These constraints may be dealt with simply. I f j is an input [output] column of the top set, then we assign to r e ( j ) [ f ( j ) ] the row 1. If on the other hand j is an input [output] column of the bottom set, then w e assign to these functions the row n. These values must be established at the outset of the annealing process, and must remain unchanged throughout, so that the desired connection is guaranteed. The values o f ~ a n d f in the remaining PLA columns must also remain unchanged. This type of constraint may be very advantageous when the PLA is to be connected to other blocks placed above or below it. 6.1.3 Top-bottom I/0 line assignment This may be considered a particular case of the previous category, where the union of the top and bottom columns is equal to the whole set of input/output columns. Therefore, the only possible assignations a r e : f ~ ( j ) = 1 a n d f ( j ) = 1 (top set), o r f , ( j ) = n a n d f ( j ) = n (bottom set). Obviously, this may be viewed as a simple constrained folding. 'This new type of folding is usually superior to simple folding in offering greater reduction of the area needed to make the routing. This constraint is treated in the same way as cases (a) and (b). 6.2 Smooth constraints The constraints considered so far do not lead to an acceptable reduction of PLA area, although it is possible to reduce the area for the routing. This implies a need to establish a trade-off between the area saving corresponding to the internal structure of" the PLA and that corresponding to the external routing. In order to achieve this it is advisable to relax the constraints, and allow each input/output column to be assigned to more than one line position. Such assignments must be bounded by two line positions, with assignments outside these limits being forbidden.
The treatment of smooth constraints may be approached either by defining a global space of solutions, adding a penalty term to the previous cost function, or by defining a smaller subspace whose solutions (valid solutions) satisfy the given constraints. Wong [15] solves this problem by applying the first technique. We have used the second, to avoid spending time in the computation of solutions that will later be rejected. Further, this alternative does not require any penalty term to be added to the cost function, decreasing the computation time of this function. The only disadvantage is that in some cases a special mechanism (assignment mechanism) must be used for moving between valid solutions. We have considered the following types of smooth constraint: (a) bounded connection line assignment, and (b) bounded connection line assignment with top-bottom input/output lines. 6.2.1 Bounded connection line assignment Although it is not necessary to modify the cost function, we must assign each input or output to a set of connection lines in the PLA. Any assignation outside these limits will not comply with the constraints. In this group the imposed constraints are specified by four arrays: Pi, Ui, Po and Uo. Each component, Pi(j) and Ui(j), 1 <<.j <<,m, represents the first and the last position respectively which is assigned to input j of the PLA. The components Po(j) and Uo(j), m + 1 <~j <<,m + s, represent the same with respect to o u t p u t j of the PLA. This is illustrated in Fig. 5(a). 6.2.2 Bounded connection line assignment with top-bottom input/output lines In this group there are input/output columns connected by the top of the PLA [ f ~ ( j ) ~ ( j ) = 1], by the bottom [ f ~ ( j ) ~ ( j ) = n], or by the lateral boundaries. This last case is treated identically to the above group of smooth constraints and is illustrated in Fig. 5(b).
49
J.M. S nchez and J. Ballesteros/Optimizing programmable logic arrays
C! .
Pi(j)<~i<~Ui(j)
( !
~ |
L
':I I
1 Cm'l I,. ql
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e~
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t
t
o I Cm'l~
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¢
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t (b) Fig. 5. Bounded connection line assignments: (a) without top and bottom input/output lines, (b) with top and bottom input/output lines.
7. The assignment mechanism T h e assignment mechanism has particular relevance owing to its centrality to the algorithm performance. T h e mechanism is based on a pair o f bipartite graphs built from the arrays discussed above. From the Pi, Ui, Po and Uo arrays a pair o f bipartite graphs Gi(A, I, Ei) and Go(A, O, Eo) are built. T h e set I o f the first graph contains the nodes uj which represent the inputsj o f the PLA. T h e set O o f the second graph contains the nodes uj which represent the outputs j o f the PLA. T h e set A contains the nodes vi which correspond to rows of the PLA. Each node uj belonging to I, ui belonging to O, is connected to a node vj belonging to A if
50
form+l
<~j<~m+s
T h e set o f edges in the graphs Gi and Go are therefore defined as follows:
Ei = [(ui, vi)/Pi(j) <~ i <~ Ui(j)] for 1 ~
(7a)
Eo = [(ui, vi/Po(j ) ~ i <~ Uo(j)] for m + 1 <~j<~m+s, 1 <~i<~n;
(7b)
q
'
c~
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OR
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for l ~ < j ~ < m
that is, each node ui belonging to I[0] is connected to a node vi belonging to the set o f connection lines A, if the connection line i is within the range o f limits established by the vectors Pi and Ui [Po and Uo]. O n c e Gi and Go have been built, the next step is to simplify them. This simplification is also used to check the correctness o f the initial constraints. T h e simplification procedure is: each time a node Ui with degree 1 is found, the corresponding node vi belonging to the set A o f connection lines is accepted. T h e n the remaining edges of vi are deleted. This process is repeated until all nodes with degree 1 have been detected. If w h e n the process ends, a node uj with degree 0 is found, then the initial constraints have been incorrectly specified. After the reduction o f Gi and Go has been completed, two new bipartite graphs G/red and Gored are formed. From these simplified graphs an initial valid solution is established by setting the functions f~ and f to an arbirary value. The SA algorithm is then run. Let us consider an example. If the PLA represented by the personality matrix in Fig. 2 is submitted to the constraints Pi = (1,1,2,3,4,6), Ui=(1,2,3,6,6,6), P o = ( 1 , 2 , 4 , 6 ) and U o = (3,4,6,6), we obtain the input connection graph
Microelectronics Journal, Vol. 26, No. 1
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Fig. 7. As Fig. 6, but with alternative constraints; see text.
Fig. 6. The example PLA of Fig. 2: (a) input connection graph, (b) output connection graph, (c) resultant simplified input connection graph, (d) resultant simplified output connection graph.
Gi (A, I, Ei) and the output connection graph Go (A, O, Eo) represented in Figs. 6(a) and (b) respectively. As we can see, inputs 1 and 6 can only be assigned to the first and last connection lines respectively (both in the A N D plane) and
output 10 to connection line 6 (in the OR.
plane). From these graphs, we obtain the two new simplified graphs G/red and Gored shown in Figs. 6(c) and (d), after the redundant edges o f the first graphs have been removed. The thick lines in G/red and Gored correspond to the initial values assigned to f, a n d f respectively. As a further example, we now take the same PLA above, but with the following constraints corresponding to Section 6.2.2:
51
J.M. Sanchez and J. Ballesteros/Optimizing programmable logic arrays
TABLE 1 Results corresponding to multiple unconstrained folding; n = row number, m = input number, s = output number, k = Markov chain number generated, F.R. = final reduction of personality matrix of the corresponding PLA n
PLA1 PLA2 PLA3 PLA4 PLA5 PLA6 PLA7
17 20 22 25 30 30 52
m+ s
10 30 36 42 40 42 42
R_EDUCTION k= 5
10
15
20
25
30
F.R.
70.0 46.7 77.8 57.1 60.0 61.9 69.0
70.0 33.3 52.8 45.2 55.5 47.6 69.0
60.0 33.3 44.4 42.9 50.0 42.9 54.8
40.0 23.3 44.4 38.1 32.5 38.1 52.4
40.0 20.0 38.9 38.1 25.0 38.1 50.0
40.0 16.7 38.9 38.1 25.0 38.1 50.0
40.0 16.7 36.1 38.1 25.0 38.1 50.0
Pi = ( 1 , - , 2 , - , 4 , - , 6), Ui = ( 1 , - , 3 , - , 6, 6), Po = ( - , 2 , 4 , - ) and Uo = ( - , 4 , 6 , - ) ; f~(2) = 1 , f ( 4 ) = 6 , f ( 7 ) = 6 and f ( 1 0 ) = 1 The graphs Gi, Go, G/red and Gored are shown in Figs. 7(a), (b), (c) and (d) respectively. T o assign input/output columns to connection lines a further procedure is required to be implemented. This procedure must be executed during the annealing process every time the system is perturbed. The aim o f this procedure is to assign random correct values to the previously defined functions according to the structure o f the simplified graphs. W h e n the number o f inputs or outputs is less than the number o f product terms and the algorithm finds a node such as f~-l(vi) = O, f-l(vi) = 0, the procedure needs little time. Only in the most complicated cases will it have to spend longer computing input or output assignments [11]. 8. E x p e r i m e n t a l results
In this work we have dealt with the multiple constrained and unconstrained column folding o f PLAs using the Simulated Annealing algorithm. Table 1 shows some experimental results obtained from the solution o f the multiple unconstrained column folding problem. These
52
results basically depend on the initial sparsity o f the PLA personality matrix and indicate that it is possible to obtain acceptable solutions when the number o f Markov chains is not very large. Several o f the PLAs in Table 1 have been folded with various types o f constraints. PLA7 [2], which is shown in Fig. 8(a), has been submitted to the following smooth constraints: Top inputs : 1, 2, 3. Bottom inputs: 4, 6, 8, 10, 12 Top outputs: 24, 25, 26, 27. Bottom outputs: 38, 39,40, 41, 42. inputs 5 7 911 13 14 15 16 17 18 19 20 21 22 23 Pl: 2 2 2 2 2 2 9 9 9 9 9 9203045 Ui: 9 9 9 9 915202020253040405050 Outputs 28 29 30 31 32 33 34 35 36 37 Po: 2 3 3 3 3 3 3 3 3 3 Uo : 2 30 30 30 30 30 30 40 40 50
The resultant reduced PLA is given in Fig. 8(b), which shows that m + s has been reduced from 42 to 23, thus producing a size reduction to 54% o f the original.
9. C o n c l u s i o n s
In this w o r k we have focussed our attention on multiple constrained column folding. In order to solve this problem we have used the same cost
Microelectronics Journal, Vol. 26, No. 1
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Fig. 8. Minimization of example PLA 7 [2]: (a) given PLA, n = 52, m + s = 42; (b) reduced PLA with given constraints n = 52, m +s = 23.
function proposed for the multiple u n c o n strained folding problem, w i t h o u t adding any penalizing term, but w i t h a m o r e reduced solution space appropriate for all solutions that comply w i t h the constraints. +From this statem e n t o f the problem we have i m p l e m e n t e d a mechanism for assignment o f c o n n e c t i o n lines. This mechanism has been modelled from a pair o f bipartite graphs, called i n p u t - o u t p u t c o n n e c tion graphs.
References
[l] R. Brayton, G. Hachtel, C. McMullen and A. Sangiovanni-Vincentelli, Logic Minimization Algorithms .for VLSI Synthesis, Kluwer Academic Publishers, 1984. [2] G.D. Hachtel, A.R.. Newton and A. SangiovanniVincentelli, Some results in optimal PLA folding, I E E E Int. Conf. on Circuits and Computers, O c t . 1 9 8 0 , [3]
pp. 1023-1026. G. De Micheli and A. Sangiovanni-Vincentelli, Multiple constrained folding of programmable logic
53
J.M. Sanchez and J. Ballesteros/Optimizing programmable logic arrays
arrays: theory and applications, IEEE Trans. on Comp. Aided Design, Cad-2(3) (1983) 151-166. [4] J.M. S:inchez,J. Ballesteros and A. Vaquero, A graphbased method for PLAs folding, 7th lasted International Symposium, Switzerland, Feb. 1989, 136-139. [5] J. Hennessy, Partitioning Programmable Logic Arrays, IEEE I C C A D (1983) 180-181. [6] J. Lewandowski and C. Liu, A branch and bound algorithm for optimal PLA folding, IEEE 21st DAC, (1984) pp. 426-431. [7] J. Lecky, O.J. Murphy and I<. Absher, Graph theoretic algorithms for the PLA folding problem, IEEE Trans. Computer Aided Design, 8(9) (1989) 1014-1021. [8] S. Kirkpatrick, C.D. Gelatt and M.P. Vecchi, Optimization by simulated annealing, Science 220 (1983) 671-680. [9] A. Aarts and J. Korst, Simulated Annealing and Boltzmann Machines: A Stochastic Approach to Combinatorial Optimization and Neural Computing, John Wiley and Sons, Chichester, 1989.
54
110] J.F. Paillotin, Optimization of the PLA area, Proc. 18th Design Automation Conf. (1981) 406-410. [11] J. Ballesteros, Una contribuci6n a la optimizaci6n topol6gica de Arrays L6gicos Programables, Doctoral Thesis, Universidad Complutense de Madrid, April 1991. [12] J. Ballesteros and J.M. Sfinchez, Multiple constrained folding of programmable logic arrays by simulated annealing, IEEE Mediterranean Electrotechnical Conference, Ljubljana, May 1991, 977-980. [13] J.M. Sfinchez and J. Ballesteros, Simulated annealing for folding of programmable logic arrays, Coll. on Synthesis and Optimisation of Logic Systems, IEE Digest 1994/066, 7/1-7/4. [14] A. Hashimoto and J. Stevens, Wire routing by optimizing channel assignment within large apertures, 8th ACM/IEEE Design Automation Workshop, 1971, 214-224. [15] D.F. Wong, H.W. Leong and C.L. Liu, Simulated Annealing for VLSI Design, Kluwer AP, 1988.