A microprogram-based 3-D image generation system using the Am29300 family

Microprocessing and Microprogramming ELSEVIER

Microprocessing and Microprogramming 40 (1994) 65 75

A microprogram-based 3-D image generation system using the Am29300 family A.A. Wardak*, G.A. King, R.L. Rhodes h!f))rmation Systems Division, Southampton Institute o[" Higher Education, East Park Terrace, Southampton S09 4WW, UK

Abstract The design and implementation of an Am29300 microprogrammable computer board, used as a coprocessor to a general-purpose MC68020 microcomputer board, is described. The main purpose is to allow those image processing program modules which are most time-consuming and highly repetitive to be executed by optimised special-purpose microcoded programs on a microprogrammable computer board. High performance microprogrammable processors, from the Advanced Micro Devices (AMD) Am29300 family series, are used in the design. The AMD board gives the user the freedom to microprogram the hardware according to needs, and this feature enables the program to be tailor-made for specific applications. This produces improved performance compared with fixed instruction set computers. The AMD board is used for the multiplication of two (4 x 4) matrices; back-faces removal; and clipping, all of which are involved in three-dimensional (3-D) image generation. Results of a comparative performance analysis with a number of 32-bit processors are presented. The Am29300 microprogrammable system has been tested by displaying various 3-D objects on the screen. Both hardware design and software implementation is discussed followed by application examples. Key words: Microprogrammable computer; 3-D image generation; Microprogramming

1. Introduction

In general, a m i c r o p r o g r a m is the prime m o v e r of a processor's control unit. It is a sequence of microinstructions stored in a high-speed m e m o r y which is often referred to as ' m i c r o p r o g r a m - m e m o r y ' , or 'control-store'. M i c r o p r o g r a m m i n g , a technique first proposed by Wilkes [1], makes use of m e m o r y

as a logic element for designing the control section of a digital system [2 4]. M i c r o p r o g r a m m i n g is used in 'bit-slice' microprocessors to synthesize a m i c r o c o m p u t e r system with a particular architecture, user defineable instructions, and word-length [5]. A m i c r o p r o g r a m m a b l e processor provides the system designer with the flexibility to choose the digital building blocks in defining a special-purpose

* Corresponding author.

0165-6074/94/$7.00 ~ 1994 Elsevier Science B.V. All rights reserved. SSDI 0165-6074(93)E0019-R

66

A.A. Wardak et al./ Microprocessing and Microprogramming 40 (1994) 65 75

architecture, and gives the ability to control parallel events simultaneously. In this paper, the design and implementation of a 32-bit Am29300 microprogrammable coprocessor system is described. It is used as an extension to an existing MC68020 single-board computer in order to perform high-speed mathematical and logical operations. It has been microprogrammed for specific 3-D image generation applications, where improved performances have been produced, compared with fixed instruction set computer. The Am29300 microprogrammable coprocessor board speeds up the highly repetitive and time-consuming processing functions such as: the multiplication of two (4 x 4) matrices; back-faces removal; clipping; and other necessary transformations. All these processing functions, which are used within the 3-D image generation system require floating-point mathematics. Applications are not restricted only to the 3-D image generation as the system can be used for speeding up the highly repetitive and computational-intensive processes involved in any real-time system.

2. System hardware description The Am29300 microprogrammable coprocessor board (Am29300 MICROCB) is interfaced to a host (an MC68020 single-board computer) via a buffered 96-way connector. The Am29300 MICROCB consists of the Am29331 Sequencer, Am29325 Floating-Point Processor, Am29332 Integer ALU, Am29334 Register Files, the host interfacing circuitry, the relevant hardware for microcodes and pipeline registers, and the general controlling logic (see Fig. 1). The Am29325 is a high-speed, single-precision, floating-point processor. It performs 32-bit singleprecision, floating-point addition, subtraction, and multiplication operations in a single clock cycle [6]. The Am29325 Floating-Point Processor has

a three-bus, 32-bit architecture, where the I/O mode is user-selectable. In this application, it is configured in full 32-bit two input bus mode with all functions and internal registers under microcode control. The Am29332 is a 32-bit wide ALU, which supports one-, two-, three-, and four-byte data for arithmetic and logic operations. It also supports multi-precision arithmetic and shift operations. For logical operations, it can support variable-length fields up to 32-bits. The device also supports a two bit-at a-time modified Booth's algorithm for highspeed multiplications. The Am29331 is a 16-bit wide, high-speed, singlechip sequencer designed to control the execution sequence of the microinstructions that are stored in the microprogram memory. The instruction set is designed to resemble high-level language concepts, and handle sequential execution, conditional and unconditional branches, subroutines, and loops [8]. The Sequencer has multi-way branch instructions that select one of the 16 consecutive addresses as the branch target in a single cycle. Two separate busses (A-bus, and D-bus) are provided to bring a branch address directly into the chip from two sources. The Am29334 is a high-speed, 64-word by 18-bit dual access, four port, register file, designed to provide high-speed storage to other members of the Am29300 family. Two Am29334 Register Files are connected in parallel to provide 64 RAM locations, each 32-bits long. These 64 long-word locations act as a shared memory for the three processors (the host, the Am29325 Floating-Point, and the Am29332 Integer ALU) and also as general-purpose working registers. The shared memory is enough for performing many of the dedicated function processes. The general arrangement is shown in Fig. 1. The general-purpose registers of the Am29300 MICROCB are memory mapped into the MC68020 computer off-board address space as shown in Table 1. A valid address along with the data strobe (DS) and address strobe (AS) will

A.A. Wardak et al.; Microprocessing and Microprogramming 40 (1994; 65 75

HOST(F~641828Single-Boa~Co~puter) ~ - ' ~ ~ C O N T F , b

l~-'-3

(96-~y

DIN61Z41 Connector)

D~XI~ i

N EG~

IVA : ERher Host (~o8828) or 1~29388MIC~B has access

RESET

to shared ~gister Files

tJE RE ContPo]]]egist~r CLX~_J Ql-Q7 ~-

113j ~

NS,8-MS,3

t8

~2

_

H/A

%

D~-DA31 DBS-DB31 (2 × 1~129334)

AH29331 T1-T6 18-15 Sesoencer DO-D11 Y~-Y18 TT-Tll ~-$3

Register Files YAS-YA31 YBS-YB31

6"

AS-A18

MicroprogramBeMor9

(Nine 82S181PROE) 72

Pipeline Registers

-DA31 DBS-DB31

GS CONTROLS/

~-131

~-$31

F~GS CONTROLS

(Nine 74273 D-TgF)

Floating-Point Ppoces$o~

9 15 / Fig. 1. The block-diagram of the Am29300 microprogrammable coprocessor board.

67

68

A.A. Wardak et al./Microprocessing and Microprogramming 40 (1994) 65 75

FFFFSm

Table 1 Am29300 M I C R O C B registers memory m a p Registers

R8

FFFF~4

Memory locations (Register file)

R1

FFFF8881] R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R 10 R 11 R 12 R 13 R 14 R 15 R 16

SFFFF0000 $FFFF0004 $FFFF0008 $FFFF000C SFFFF0010 $FFFF0014 $FFFF0018 SFFFF001C $FFFF0020 $FFFF0024 $FFFF0028 $FFFF002C $FFFF0030 $FFFF0034 $FFFF0038 SFFFF003C $FFFF0040

x y z aI1 a21 a31 a41 a12 a22 a32 a42 al 3 a23 a33 a43

R2

I

I

~4

FFFF8186

CONSULI~IS~R

74LS273

RESET activate either the control signal REGEN or CONTEN, which will enable the Register Files and the Control Register (see Fig. 2) respectively. By combining the MC68020 R/Vv" signal with REGEN, the active LOW write enable (WE) and read enable (RE) strobes are produced to control the register write enables and the direction of the data bus buffers. The MC68020 single-board computer drives the Am29300 MICROCB, supplies the required data, and then selects one of the microsubroutines through the Control Register. The Control Register, which is clocked by the control signal, CONTEN, presents a control-word to the Am29331 Sequencer. The most significant bit of the control-word sets the TO flag for conditional branching, and the other bits select one of the 4 multi-way sets (M00-M03) which will subsequently select upto 16 microsubroutines.

I

FFFF~FC

1~ (68828)

CLR

,50

OCC --+ e (~quencer)

b D3

D3 (68828) D3 (~828)

_ , ~,3 (~luencer) Q5 _.~ ~,2 (Sequencer)

b

_~ M,8 (Sequencer)

De (f~828l

D1 (68~)

._~ 1t8,1 (Sequencer)

D7 C~

Fig. 2. Layout of the control register.

A horizontal microinstruction format (72-bits long) is implemented, where each bit is used to uniquely control a separate control-line. The system hardware is initialised, synchronised and controlled by microcodes, which are placed in

69

A.A. Wardak et al./ Microproce.s'sing and Microprogramming 40 !'1994) 65 75

~EQU~NCER-FIELD FPlJ/INT~Lt{FIELD REGISTER-FILE FIELD

NICBOIKSTBUCTI~NO.~ NIC~I~TRUCTIO~ NO.I i

I

~

7FF 11

I

I

I

MIC!~OIN$1~(~TI~NO,TFI'h

~{

SF~ENCER-FIELD

I{8

FF

~

FLORTI~-POINT / INTEGERALl{PBOCE~OR~-FIELD

AIAJ-POSITIO~ (EPBOMNO,5)

F~-CONTBOL (EP~ NO,4)

F~-I~TP~TIO~ (EPBOMNO,6)

2 ~ ~-~ ~ ~ ~F IEEF.~ FT1 FT8 18 17 I~ F4 P3 P2 F1 1~ PEOJ/~ I~Dl ]~I~ 14 13 12 11

1

01

11

1

11

11111111 J

0

L

J

EF

8

0

0801

L

FF

OZ

REGISTER-FILEFIELD RECISTER-AREAD (EFBOMNO,?) XX~

7

RECISTER-DREAD (E'P{~ NO,8)

REGISTER-BVEITE (EI)]~ ~,9)

A ~ A~3 A ~ A~I A ~ X X ARB5A ~ ARB]AR~ ARB1AR~ X WEMB~B5 ~B4 ~B3 ~B2 AWB1AWBO r

88 I

8

8

8

8

0 8 08

8

8

8

It

8

1 1 0 J

83

1

8

0

1

1

I

1

1 J

4F

Fig. 3. The microinstruction format implemented for this architecture.

70

A.A. Wardak et al./ Microprocessing and Microprogramming 40 (1994) 65 75

EPROMs. The implemented microinstructions consist of 3 main fields (Fig. 3): the Sequencer's Field (Sequencer-Instructions, Sequencer-Data, and Sequencer-Test); the Floating-Point or Integer Processor's Field (FPU-Control, FPU-Instruction, and ALU-Position); and the Register File's Field (REG-A Read, REG-B Read, and REG-B Write). The microinstructions are sequenced by the Am29331 Microprogram Sequencer, which handles sequential execution, conditional and unconditional branches, subroutines, and loops under microcode control. The mathematical and logical instructions are executed by the Floating-Point and Integer Processors respectively, which are instructed by microcodes. The output of the microprogram memory is loaded into the Pipeline Registers, which store the next microinstructions while the current microinstructions are being executed. The output from the Pipeline Registers is distributed to the relevant sections of the Am29300 MICROCB and these constitute the control signals.

3. Host-coprocessor interaction The system software was developed using the high-level language 'C', the MC68020 assembly language, and the microcoding [9-11]. The initialisation and synchronisation of the system hardware, and the execution of the microsubroutines are described as follows. Initially, when the RESET switch is pressed, all the Pipeline Registers including the Control Register are cleared. The Pipeline Registers present the instruction $00 to the Am29331 Sequencer which sets the conditional branching flag LOW. The conditional branching flag in this case is TO, which is one of the 16 external test inputs to the Am29331 Sequencer [6]. The Sequencer continuously monitors the state of TO, which is set LOW or H I G H by

the host processor through the Control Register. If TO is set HIGH (pass), then the Sequencer branches to the address specified by its D-inputs concatenated with its M-inputs; and if TO is set LOW (fail), then the Sequencer again enters in the busy loop. Accessing the shared memory (Register Files) is controlled through the microcode bit (MC68020/ Am29300), which allows only one processor at a time. During the initial stage, this microcode bit is set H I G H to allow the host processor to transfer the required data into the Register Files for processing. Once the required data for a particular subroutine is completely entered, then TO is set HIGH and the multi-way branch conditions are also appropriately set through the Control Register. As a result, the Sequencer picks up the beginning address of a particular microsubroutine from the region of the base addresses. The MC68020/Am29300 microcode bit then allows either the Floating-Point Processor or the Integer ALU to perform the required operations. On completion of the microsubroutine the Am29300 MICROCB sends an interrupt request to the host processor to signal the end of the task and also allow the host to read the processed data from the Register File. Figure 4 illustrates the initialisation and synchronisation of the system.

4. Microprogramming application examples 4.1 Rotation

Rotation of a point about an axis involves the multiplication of two matrices, which is one of the highly repetitive and most time-consuming mathematical operations in 3-D image generation. The algorithm, to multiply a (1 × 4) vector and a (4 x 4) matrix, which is used in the rotation of 3-D images

A . A . W a r d a k et all It Microprocessing and M i c r o p r o g r a m m i n g 40 (1994) 65 75

Table 2 The microprogram a matrix

Resel the ~m29396NICROCB

Y Condlti~nalbra~cklngflag s cleared CBF := LOt})

i Data is writtento the sharedBor.9) 5g !be Host (H/A :: HI~H) I

i

IBaseaddress is set foe 16 target iaddresses (~ :: IX}l)

H/~: EitherHost (l~) or ~ 2 9 ~ fllCP~CB has accessIo the sharedRegistePFiles CBF : A conditionalbea~kimjflag, which is one of the externaltest-in~tsto the

for the

SEI~UENCF~FIELD

71

multiplication

of a v e c t o r

and

F~TING-POINT FIELD I~IST~-FILE FIELD

ADDR~$ SEQ-INST SEQ-YE~T SEQo~qTA FPU A~ FPU READ R~D CO#~'ROLPOSIT, INST. ~ A ~5-B

~ITE ~G-B

828

86

~

FF

BF

FF

82

m

83

4F

M~3B9 ~quescee (19) that is set LOt' or HI~ t}~oughthe Control P~Jister

821

96

00

FF

BF

FF

82

01

64

$6

822

96

88

FF

iF

FF

02

02

~

5!

: Baseaddress from which16 unconditional ~mps can be achieved (i,e M : ~(h : lob, illL 1ZS, 13h, 14h, ..... 1Fh )

823

96

96

FF

BF

FF

88

OF

10

4F

824

96

88

FF

BF

FF

96

OF

I[

4F

"::' implies set to

i Set +.beconditionalbranchingflag ! ICBF :: HI(~) throughcontrolRegister]

825

~

88

FF

BF

FF

88

OF

~

4F

826

96

96

FF

BF

FF

82

88

~

56

827

88

88

FF

BF

FF

82

81

~

51

928

96

96

FF

BF

FF

82

82

~

52

~9

88

96

FF

BF

FF

96

18

11

58

02A

96

~

FF

BF

FF

88

19

12

59

62D

~

88

FF

BF

FF

00

18

~

58

82C

B6

88

FF

DF

FF

82

96

OB

51 52

82D

Pick up the targetaddress rr~ the Base addresses region

+

I ~

88

FF

BF

FF

82

91

6C

62E

96

88

FF

BF

FF

82

82

9D

53

82F

96

88

FF

BF

FF

88

11

12

51

639

96

88

FF

BF

FF

88

11

13

51

931

I~

88

FF

BF

FF

88

11

8E

51

832

48

88

32

3F

FF

FF

FF

FF

FF

833

E8

88

= 88

3F

FF

FF

FF

FF

FF

Jumpto the beginningof the micros~br~tineand start x~catlngthe microsubro~tine

(H/~ :: L~)

[12, 13], is presented as follows: Intterupt688~ at the end of ~icresubrouticoH/A :: H GH

[ x ' . v ' z' l ] = [ x

y z 1]

I i il 21 31 41

4 ~YES

Fig. 4. S y n c h r o n i s a t i o n and initialisation Am29300microcb.

of the

host

and

a22 a32 a42

a23 a33 a43

The elements x, y, z and a l l , a21 . . . . a44 are written into the Register File by the host processor in the format shown in Table 1, for calculating the new values of x', y', and z'. The microcode to perform the multiplication of the vector and the matrix is now described. For clarity, some steps, which have been used in developing the microcode of Table 2 are explained as

72

A.A. Wardak et al. / Microprocessing and Microprogramming 40 (1994) 65-.75

follows: ($FFFF0000) x ($FFFF000C) ($FFFF003C) ~ x * all

(1)

($FFFF0004) - ($FFFF0010) ($FFFF0040) ~ y - a21

(2)

According to the first statement, the Am29325 Floating-Point Processor reads the two operands from the two registers R0 and R3 respectively, multiplies them together, and writes the result back into the register R15. Similarly, the second expression implies, that the Am29325 Floating-Point Processor reads the two operands from the registers R1 and R4 respectively, then subtracts the second operand from the first and writes the result back into the register R16. The same approach has been used to write the microcode for the multiplication of the vector and the matrix as shown in Table 2. The microprogram has been tested extensively and proved to be working correctly. For more clarity, the implementation of the first microinstruction of Table 2 has been presented in detail in Fig. 3.

Registers

Memory locations (Register file)

R0 R1 R2 R3 R4 R5 R6 R7 R8

$FFFF0000 $FFFF0004 $FFFF0008 $FFFF000C $FFFF0010 $FFFF0014 $FFFF0018 $FFFF001C $FFFF0020

Ax Ay Az Bx By Bz Cx Cy Cz

The following steps describe the way the backface detection test has been encoded in microprogramming. As an example, the steps which are required to calculate the first part of the expression, BFRTF, is presented as follows: ($FFFF0010) × ($FFFF0020) ($FFFF0024) ~ ByCz ($FFFF0014) × ($FFFF001C) --. ($FFFF0028) ~ BzCy ($FFFF0024) x ($FFFF0028) ($FFFF002C) ~ ByCz - BzCy

4.2 Back-face removal The computation of the mathematical expression, BFRTF, used for back-face detection is also a highly repetitive and time-consuming process in 3-D image generation. Thereby, it has been encoded in microprogramming for fast executiontime. The expression, BFRTF, can be written as follows: B F R T F = Ax(ByCz - BzCy) + Ay(BzCx - BxCz) + Az(BxCy - ByCx). The coefficients values are written into the Register File in the following format:

($FFFF0000) x ($FFFF002C) ($FFFF0030) ~ Ax(ByCz - BzCy) The final value of the expression, BFRTF, is computed by the Am29325 Floating-Point Processor and then read by the host processor to determine the state of the concerned face. The algorithm has been practically implemented in removing the back-faces of various 3-D objects and has been demonstrated, working correctly. Table 3 represents the microprogram implementation for the above mathematical expression. The Am29300 MICROCB has been also used for partially encoding the clipping algorithm and mapping the projected values into the viewport values.

A.A. Wardak et al.; Microprocessing and Microprogramming 40 (1994) 65 75

Table 3 The microcode implementation of the expression used for backface removal r

;

FLOATI~-POINTFIED REGISTER-FILEFIEL£

SE~a~ENCER FIELD

RDDRES5 SEO-II~T SEQ-TEST SEQ-I~TR FPU RLU FPU CONTROLPOSlY. l~Y.

I~F~D RERD RRITE I~EG-A P~G-H REG-B

64~

BO

9@

FF

BF

FF

02

~

49

04!

BQ

~

FF

BF

FF

Q2

Q7

4A

942

~

99

F[

BF

FF

91

~

4B

@43

B~

@Q

FF

BF

FF

62

98

4C

@44

BO

@@

FF

BF

FF

~2

~

49

• 15

B@

0@

FF

BF

FF

02

g3

08

4E

e46

~

0@

FF

BF

FF

@1

9D

9E

4F

B47

BO

QO

FF

BF

FF

91

OF

59

048

~

BO

FF

BF

FF

g3

07

51

~9

~

~

FF

BF

FF

02

S4~

~

00

FF

BF

FF

BI

it

12

53

64~

~O

00

FF

BF

FF

13

54

~4C

I~

90

FF

BF

FF

10

55

94D

~0

~O

FF

BF

FF

00

15

14

56

84£

40

~O

4E

3F

FF

FF

FF

FF

FF

~F

E6

~

3F

FF

FF

FF

FF

FF

5. P e r f o r m a n c e

04

analysis

The technique used for calculating the performance analysis of the Am29300 MICROCB is based on the MC68020 processor interrupt mechanism. The Am29300 M I C R O C B signals the completion of the task by sending an interrupt request to the MC68020 processor. The MC68020 processor, host to the Am29300 MICROCB is kept in a busy loop (only during carrying out the performance analysis), by executing the following assembly language instruction: loop

dbra

counter,

loop

The following mathematical expression, BFRTF, was chosen for evaluating the performance factor. B F R T F = Ax(ByCz - BzCy) + Ay(BzCx - BxCz) + A z ( B x C y - ByCx).

73

It is found that the time taken by the Am29300 MICROCB to execute the expression BFRTF, is the same as the time taken by the MC68020 processor to execute the instruction, "loop: dbra counter, loop", 10 times. From the execution-time tables, given in the MC68020 and MC68881 user's manuals [10, 11], the MC68020 processor executes the instruction, 'loop: dbra counter, loop', at 9 clock cycles (at 12 MHz). As a result, the Am29300 MICROCB takes 1 0 x 9 = 90 clock cycles of the MC68020 processor to compute the expression, BFRTF. However, the MC68020 processor itself, requires 1080 clock cycles to compute the given expression (720 for 9 FP multiplications, 216 for 3 FP subtractions, and 144 for 2 FP additions). Therefore, the Am29300 MICROCB has been shown to be 12 times faster than the MC68020 single-board computer. The figure 12 for the performance factor has been calculated while the cache of the MC68020 processor was disabled (only during carrying out the performance analysis) and the effect of transferring data to the Am29300 Register File was not taken into consideration. Therefore, the final performance factor between the Am29300 MICROCB and the MC68020 processor after considering the mentioned factors, is 8. For the detailed analysis of the performance factor, the reader is referred to Wardak [14]. It has been reported that the MC68040 processor is 4 times faster than the MC68020 [15] and 3 times faster than the MC68030 [16,17]. As a result, the Am29300 MICROCB should be 6 times faster than the MC68030, and 2 times faster than the MC68040 processor. Similarly, the performance analysis for the MC68020 processor in comparison to some other 32-bit processors has been reported by Cooper et al. [18]. Using Cooper's data, the Am29300 MICROCB should be 10 times faster than the Intel 80386, and 14 times faster than the AT&T 32100 processor.

74

A.A. Wardak et al./Microprocessing and Microprogramming 40 (1994) 65 75

6. Conclusions The Am29300 M I C R O C B was highly successful as a n accelerator for 3-D image g e n e r a t i o n applications a n d speedup factors defined as objectives were reached. However, its application is n o t restricted only to the 3-D image generation, it can be used for all highly repetitive a n d t i m e - c o n s u m i n g processes involved in a n y real-time system. The same approach, which has been i m p l e m e n t e d for m i c r o p r o g r a m m i n g this p a r t i c u l a r coprocessor b o a r d can be generalised a n d a d o p t e d for all microp r o g r a m m a b l e chips of this nature. The relevant m i c r o s u b r o u t i n e s have been verified a n d work correctly as d e m o n s t r a t e d by displaying various transf o r m a t i o n s of 3-D objects on the screen.

References [1] M.V. Wilkes and J. B. Stringer, Microprogramming and the design of the control circuit in an electronics digital computer, Proc. Cambridoe Phil. Soc. 49(2) (1953) 230 238. [2] J.R. Mick, Microprogramming for the hardware engineer, Proc. DISE Workshop on Microprocessors and Education,

Colorado State University, Fort Collins, CO. (Aug. 16-18, 1976) 6-14. [3] T.G. Rauscher and P.N. Adams, Microprogramming: A tutorial and survey of recent developments,IEEE Trans. Comput. C-29(1) (Jan. 1980) 2 19. [4] S. Dasgupta, The organization of microprogram stores, ACM Comput. Survey 11(1)(March 1979) 39-65.

[5] C. Paul, What is microprogramming, Electronic Products (Nov. 3, 1986). [6] Advanced Micro Devices, 32-Bit Microprogrammable Products Am29C300/Am29300 1988 Data Book, AMD Inc., Sunnyvale, CA, USA, 1988. [7] F. Phillip, Microcodable blocks yield flexiblesystem, Electronic Engineerin9 Times (July 7, 1986). [8] R.M. Perlman, Floating-point array processor improves computational power, EDN (USA), Part 2 (Jan. 23, 1986) 195 203. [9] B.W. Kernighan and D.M. Ritchi, The C Programmin9 Languaye (Bell Laboratories, Murray Hill, NJ, PrenticeHall of India, 1988). [10] MC68020 32-bit Microprocessor User's Manual (PrenticeHall, Englewood Cliffs, NJ, 1985). [11] MC68881 Floating-Point Coprocessor User's Manual (Motorola, 1985). [12] J. D. Foley, A.V. Dam, S.K. Feiner and J.F. Hughes, Computer Graphics: Principles and Practice (Addison-Wesley, Reading, MA, 1990) Ch. 5. [13] R. Salmon and M. Slater, Computer Graphics: Systems & Concepts (Addison-Wesley,Reading, MA, 1987) Ch. 13. [14] A. Wardak, A three-dimensional image generation system using a microprogrammable computer, PhD Thesis, University of Bradford, Department of Electrical Engineering, United-Kingdom, 1991 Ch. 5. [15] R.W. Edenfield, M.G. Gallup, W.B. Ledbetter, R.C. McGarity, E.E. Quintana and R.A. Reininger, The 68040 processor Part 1, Design and implementation, IEEE Micro (Feb. 1990) 66-79. [16] T.L. Johnson, A comparison of MC68000 family processors, BYTE (Sept. 1986) 205-218. [17] T. Thompson, 040 Motorola's 68040 microprocessor, BYTE (Feb. 1990) 96A-96C. [18] T.C. Cooper, W.D. Bell, F.C. Lin and N.J. Rasmuseen, A benchmark comparison of 32-bit microprocessors, IEEE Micro 6(4) (Aug. 1986) 53 58.

A.A. Wardak el al./Microprocessing and Microprogrammmg 40 (1994) 65 75

Abdullah Wardak was a lecturer at the Kabul University, Afghanistan from 1978 to 1983, where he received his BSc in Electrical and Electronics Engineering in 1978. He received his MSc in Electronic Control Engineering in 1987 from Salford University, UK. He received his P h D in 1991 from Bradford University, U K , where his research was the generation of 3D Scenes in realtime using a microprogrammable computer. Currently, he is a senior lecturer in the Information Systems Division, S o u t h a m p t o n Institute, UK. His field of interest is 3D image generation in real-time, signal-processing and computer architecture.

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Graham King is Head of the lnformatics Research Centre and Associate Professor in Computer Systems Engineering at S o u t h a m p t o n Institute. He was employed in the Department of Electrical Engineering Science at tile University of Essex U K during 1971 before joining Leith Nautical College Edinburgh UK, where he was lecturer in electronics between 1972 and 1974. A subsequent move to Southampton as lecturer and then reader led to his present post. A graduate of the Open University U K his research interests led to a higher research degree in 1989. His research is primarily concerned with data compression, digital signal and image processing.