A model for length of saturation velocity region in double-gate Graphene nanoribbon transistors

A model for length of saturation velocity region in double-gate Graphene nanoribbon transistors

Microelectronics Reliability 51 (2011) 2143–2146 Contents lists available at ScienceDirect Microelectronics Reliability journal homepage: www.elsevi...

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Microelectronics Reliability 51 (2011) 2143–2146

Contents lists available at ScienceDirect

Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel

A model for length of saturation velocity region in double-gate Graphene nanoribbon transistors M.H. Ghadiry a,⇑, M. Nadi S. b, M.T. Ahmadi c, Asrulnizam Abd Manaf a a

School of Electrical and Electronic Engineering, Engineering Campus, Universiti Sains Malaysia, Penang, Malaysia Department of Computer Engineering, Ashtian Branch, Islamic Azad University, Ashtian, Iran c Department of Electronic Engineering, Faculty of Electrical Engineering, Universiti Teknologi Malaysia, 81310 Skudai, Johor Darul Takzim, Malaysia b

a r t i c l e

i n f o

Article history: Received 11 April 2011 Received in revised form 5 July 2011 Accepted 5 July 2011 Available online 6 August 2011

a b s t r a c t Length of saturation region (LVSR) as an important parameter in nanoscale devices, which controls the drain breakdown voltage is in our focus. This paper presents three models for surface potential, surface electric field and LVSR in double-gate Graphene nanoribbon transistors. The Poisson equation is used to derive surface potential, lateral electric field and LVSR. Using the proposed models, the effect of several parameters such as drain–source voltage, oxide thickness, doping concentration and channel length on the LVSR is studied. Ó 2011 Elsevier Ltd. All rights reserved.

1. Introduction Demand for higher performance in memory and logic applications caused continuous shrinking in devices’ dimensions. Based on ITRS predictions, to continue the miniaturization, MOSFET channel length needs to be scaled down in atomic size to meet the Moor’s law requirements [1]. However, there are some uncertainties about the behaviour of the existing Si devices under the extreme scaling. Therefore, new material-based device concepts such as nanowire FETs and CNT FETs, have been suggested. Among those, Carbon Nanotube (CNT) FETs, because of their excellent electronic properties, have been comprehensively explored and notable research concentration especially on their high carrier mobility and conductance has been reported [1,2]. However, there are still some unresolved issues about controlling the chirality of CNTs, making them questionable to be used in realistic applications [1–3]. Recently, experimental studies [4,5] have showed it is possible to fabricate Graphene nanoribbon (GNR) transistors and the potential of GNR as an alternative approach to overcome the CNT’s chirality issues has been investigated. As a result, many researchers have been attracted to this field and provided several models for GNR’s properties [1,5–11]. Nevertheless, there is lack of work modelling its behaviour near the drain junction and its breakdown voltage. The velocity saturation region length (LVSR) of FET transistors or the width of the drain region where impact ionisation and carrier velocity saturation occurs is one of the most important parameters in nanoscale devices. It controls the lateral drain breakdown voltage [12,13], substrate current, hot-electron generation [14,15], and drain current at the drain region [16–18]. In a FET ⇑ Corresponding author. E-mail address: [email protected] (M.H. Ghadiry). 0026-2714/$ - see front matter Ó 2011 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2011.07.009

transistor, if the applied drain voltage is higher than the drain saturation voltage, the electric field near the drain junction will be higher than the critical field strength, which results in carrier velocity saturation. In addition, high electric field near the drain junction causes impact ionisation and substrate current generation [19]. Although several models are available for saturation region of silicon-based MOSFETs [13–15,17–23], there is still plenty of room for research in modelling of this region for GNR transistors. In order to gain insights into reliability issues of these devices, close analysis of this region is necessary. In addition, these kinds of models open the way to design power transistors based on Graphene. Since there is no experimental data yet for the length of saturation region in Graphene-based transistors, analytical modelling seems to be a powerful tool in this case to provide some estimation. Therefore, firstly, we provide simple analytical models for surface potential and electric field distribution of double gate GNRFET (DG-GNRFET). Secondly, we extract the LVSR model from the proposed surface potential model. This paper is organised as follows: Section 2 derives and explains the proposed model and demonstrates the applied GNRFET; Section 3 shows the results and discusses them and finally Section 4 concludes this paper. 2. The proposed model for LVSR A schematic cross-section of DG-GNRFET is shown in Fig. 1, where tOX is the oxide thickness of front and back gates with dielectric constant of eOX. The tG, eG, W and L are the thickness, dielectric constant, width and length of the GNR respectively. Generally, to model the potential distribution, Poisson’s equation is solved [20].

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Solving Eq. (6) with boundary conditions of Eqs. (8) and (9) yields

Vð0Þ ¼ V 0 ¼

     CG C OX 1 1 V g2 þ V g1 þ 1 þ qN d t G þ C G C OX 2C G þ C OX CG

ð10Þ

In this paper we study the device at zero gate bias condition, VGS1 = VGS2 = 0, therefore, Eq. (10) can be reduced to

V0 ¼ Fig. 1. Schematic cross section of a double-gate GNRFET.

qNd ðtG C OX þ eG Þ C OX ð2C G þ C OX Þ

ð11Þ

The boundary conditions for Eq. (7) are expressed as

r2 Wðx; yÞ ¼

qNd

eG

;

0 6 x 6 tG ;

06y6L

ð1Þ

where w(x, y) is the potential at any point (x, y) in the GNR, q is the electric charge magnitude, and Nd is the doping concentration of GNR. Ignoring the built-in potential of the source/drain channel junction [20], the boundary conditions of Eq. (1) is defined as w(0, 0) = 0 and w(0, L) = VDS. In addition, as the electric flux along the front and back GNR/oxide interface is continuous, the potential function must satisfy

 @ Wðx; yÞ eOX Wð0; yÞ  V g1 ¼  @x x¼0 eG tOX

ð2Þ

and

 @ Wðx; yÞ eOX V g2  WðtG ; yÞ ¼  @x x¼tG tOX eG

V FB

ð3Þ

ð4Þ

where, vF  106 m/s is the Fermi velocity of Graphene, VT = KBT/q is the thermal voltage, ni is the intrinsic carrier concentration of Graphene. According to [20,24], w(x, y) can be decomposed into two parts:

Wðx; yÞ ¼ VðxÞ þ Uðx; yÞ

ð12Þ

Uð0; LÞ ¼ V DS  V 0

ð13Þ

 @Uðx; yÞ eOX Uð0; yÞ ¼  @x x¼0 t OX eG

ð14Þ

 @Uðx; yÞ eOX UðtG ; yÞ ¼  @x x¼tG t OX eG

ð15Þ

The solution of Eq. (7) can be obtained by the separation of variables method [24]. The solution at the surface is given by the following exponential series

Uð0; yÞ ¼

where Vg1 = VGS1  UFB1, Vg2 = VGS2  UFB2, VGS1 and VGS2 are gate– source voltages for front and back gates respectively and UFB1 and UFB2 are front and back flat band voltages respectively. Flat band voltage VFB in GNR with a bandgap EG = hVF/3wG [9] can be calculated using

hv F ¼  V T ln ðNd =ni Þ 6qwG

Uð0; 0Þ ¼ V 0

ð5Þ

1 X

An expðkn yÞ þ Bn expðkn yÞ

ð16Þ

n¼1

where

An ¼

ðV DS  V 0 Þ expðkn LÞ þ V 0 expð2kn LÞ 1  expð2kn LÞ

Bn ¼ V s  An

ð17Þ ð18Þ

and kn is potential variations parameter defined as



CG tG kn ¼ 2C OX

"  2 # C OX 2 tanðt G kn Þ ðtG kn Þ  CG

ð19Þ

As tG is a small value (in order of 109), tan(tGkn) can be approximated to tGkn. Thus, kn is given by

1 kn ¼ tG

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2C OX 1þ CG

ð20Þ

where V(x) is the 1D solution of the Poisson equation

@ 2 VðxÞ qNd ¼ @x2 eG

ð6Þ

which accounts for long-channel effects and U(x, y) is the solution of Poisson equation which deals with 2D short channel effects. Using Eqs. (5) and (6) in (1), U(x, y) satisfies the Laplace equation

@ 2 Uðx; yÞ @ 2 Uðx; yÞ þ ¼0 @x2 @y2

ð7Þ

As Eq. (5) shows, the boundary conditions of w(x, y) can be also written into two parts. Therefore, by separating Eq. (2) and (3) the boundary conditions can be expressed as

   @VðxÞ eOX Vð0Þ  V g1 ¼ @x x¼0 eG t OX

ð8Þ

and

   @VðxÞ eOX V g2  VðtG Þ ¼  @x x¼tG t OX eG

ð9Þ

Fig. 2. Comparison of the results extracted from 2D numerical simulator and model.

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In order to get a simple solution of U(0, y), it can be approximated to only the first term (n = 1) of the series in Eq. (16) according to [20]. Thus Eq. (16) reduces to Eq. (21) taking into account that we approximated exp(x)  0 for x > 3. This approximation is justified if y and L > 3k, which is relevant in this study.

Uð0; yÞ ¼ ðV DS  V 0 ÞekðyLÞ  V 0 eky

ð21Þ

thus, using Eq. (5) the surface potential along y can be written as

Wð0; yÞ ¼ V 0 þ ðV DS  V 0 ÞekðyLÞ  V 0 eky

ð22Þ

In addition, the lateral electric field along the channel can be expressed as derivation of Eq. (22) over y.

ky

Eð0; yÞ ¼ k½ðV DS ¼ V S ÞekðyLÞ þ V 0 d

ð23Þ

By taking y = L  LD, w(0, y) = VSat, and solving Eq. (22) for LD, we have

1 LD ¼ L  ln k

ðV DS V S Þ 2kðLLd Þ e ekL

V Sat  V 0

 V0

! ð24Þ

which can be solved numerically. In Eq. (24), VSat and LD are drain saturation voltage and length of saturation velocity region respectively.

(a)

(b)

(c)

(d)

(e)

(f)

Fig. 3. The effect of several parameters on the profile of surface potential, electric field distribution and length of saturation velocity region. Typical parameters are Nd = 5  1025 m3, L = 20 nm, tox = 1 nm, and tG = 0.4 nm.

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The proposed equations simply explain the relations of surface potential, electric field and length of saturation region with tOX, tG, VDS and L. 3. Results and discussion In this section, the profile of surface electric field and potential variation is shown. In addition, the effect of several parameters such as drain-source voltage, oxide thickness, channel length and doping concentration on the length of saturation region is studied. For the purpose of model verification, we compared the calculated values using the proposed model with the simulated results by MEDICI for a Si-based device. As shown in Fig. 2, good agreement can be seen between the simulation results and model at different doping concentrations, oxide thicknesses and distances from drain. Once the surface potential model is verified, the LVSR model is proved too because it is the solution of the surface potential for w(0, y) = VSat. Fig. 3a and b shows, the potential and electric field distribution along the nanoribbon surface is similar to the profile of surface potential in an abrupt junction [21]. Fig. 3c indicates that increasing the doping concentration in the channel region results in a significant increase in the electric field near the drain junction. Doping concentration has been set to be in order of 1025 m3 to be an influential factor in the electric field and length of saturation region. Fig. 3d shows, expanding the oxide thickness causes decrease in LVSR because by doing so, higher saturation voltage and lateral electric filed is resulted, and thus LVSR is shortened. It is worth mentioning that the calculation of LVSR is done for VDS > VSat. Therefore, wherever VDS < VSat, there is a missing point in the charts. For example in Fig. 3b and f, LVSR cannot be calculated for a few VDSes. Fig. 3e shows the dependence of LD on L. As can be seen in this figure and Eq. (24), there is a direct relation between L and LD. Finally, Fig. 3f shows by applying higher doping concentration, the saturation voltage increases and LD decreases. 4. Conclusion Three analytical models for surface potential, electric field and LVSR of double-gate GNR transistors were proposed. In addition, the behaviour of the double gate GNR transistors in the saturation region was investigated using the proposed models. Furthermore, using the presented models, the effects of device parameters such as ribbon thickness, doping concentration and channel length were examined. As it was expected from small geometry of the device, high lateral electric field was seen near the drain junction, being an issue for reliability of these devices. In addition, LVSR was found to be more than half of the given channel length in some cases. In future, the breakdown voltage of these transistors will be modelled and possibility of making power devices studied.

Acknowledgements This work has been supported by PhD fellowship scheme with No. 1/11 and Grant numbered 04/PELECT/60310023 from School of Electrical and Electronic Engineering, Universiti Sains Malaysia. In addition, the authors would like to thank Dr. Mahmoud Pesaran for his helpful comments on using Matlab tool.

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