A model for the etch-stop location on reverse-biased pn junctions

A

ELSEVIER

PHYSICAL

SensorsandActuatorsA 66 ( 1998) 259-267

A model for the etch-stop location on reverse-biased pn junctions Daniel Lapadatu *, Gjermund Kittilsland, Martin Nese, Svein M. Nilsen, Henrik Jakobsen SermNor

m-n. Kmrdsrdd~vien

7, PO Box 196, N-31 92 Horten,

Nomq

Received6 July 1997;revised 17September1997;accepted19September1997

Abstract This paper reports a model to predict where the silicon anisotropic electrochemical etching terminates on reverse-biased pn junctions. The model explains why the etching process terminates well before the metallurgical junction. The effects of the substrate doping, the type of junction (step or graded), the etching temperature and voltage bias, as well as the technique used (three and four electrodes) are analysed and compared with the experimental data. Some limitations and deviations from this theory are also pointed out. 0 1997 Elsevier Science S.A. All rights reserved. Kqwords:

Etch-stop location;Etch-stopmodel;Electrochemicaletch-slop

1. Introduction One of the most suitable and successful etch-stop techniques is the electrochemical etch-stop (ECES) , achieved by reverse biasing a pn junction [ I-51. In its basic form, i.e., in the two-electrode configuration, a pn junction is reverse biased during etching by externally connecting a voltage source across the n-layer, known as the working electrode, and an inert counter electrode, usually platinum, immersed in the etchant. If the n-side of the wafer is protected from the etchant by a hermetically sealed etch holder or jig, and biased anodically with respect to the passivation potential, Vppp,N,the etching will only occur in the psubstrate. In a three-electrode ECES set-up [ 1,2], a reference electrode is introduced for more accurate control over the potential of the etchant. A fourth electrode can be used to contact the p-type substrate in order to gain direct control over the pn junction bias voltage [ 31. The four-electrode approach allows etch-stopping on lower-quality wafers ( larger leakage current) and a better control of the membrane thickness, as demonstrated in Ref. [ 31. Ideally, by employing the ECES technique, one must be able to remove by etching the entire p-type material. However, it is clear from the published results [ 3,5-121 that the ECES does not terminate at the metallurgical junction. but rather in the p-type substrate. In most of the applications, an accurate control of the fabricated membrane thickness is com’ Correspondingauthor. Tel.: +47 33 03 5 1 81. Fax: f47 33 03 51 05. E-n-& daniel.lapadatu~sensonor.no 0923-3237/98/$19.000 1998ElsevierScienceS.A. All rights reserved. PIlSO924-4247(97)01687-7

pulsory. Therefore, an understanding of the premature stop of the etching process and the prediction of its exact location are of major importance in the MEMS field.

2. Theoretical

model

Qualitative explanations of the premature stop of the electrochemical etching of silicon in alkaline solutions have been given in several publications. Leakage diode currents, floating potential of the substrate toward anodic values, wafer taper [ 7,10,12], the bipolar effects in the n-layer/p-substrate/liquid system [ 81 u’ere reported to generate premature etch-stop. In the four-electrode configuration, although these effects are alleviated and membranes with thickness much closer to expected values were achieved, it has still been observed that the etching terminates before the metallurgical junction and even before the pn junction depleted region

[4,8,91. We propose an improved model, valid only for the fourelectrode configuration, based on the bipolar effect [ 81 and our earlier reported conclusions [ 131 that n- and p-type silicon wafers immersed in alkaline solutions exhibit a degenerated shallow electronic layer at their interface with the liquid phase. Therefore, if the p-type substrate is biased at the open circuit potential (OCP) or slightly anodic with respect to the OCP, a depleted region will exist right under the silicon/liquid interface, separating the bulkp-type material from

the shallow n+ layer.

260

In the following sections, unless otherwise specified, only the four-electrode configuration is considered. All the potentials are referred to the OCP for convenience. A wafer containing a metallurgical pn junction immersed in alkaline solutions, p-substrate exposed to the etchant, consists of the following succession of layers: the n-layer (either epitaxial or diffused, biased at V,), the pn junction depleted region, the p-substrate (biased at V,) , the depleted region under the silicon/liquid interface and an n ’ shallow degenerated layer. It should be observed that in the usual ECES set-up the metallurgical junction is reverse biased, whereas the induced junction is forward biased. If the thickness of the neutral p-substrate is larger than the diffusion length of the electrons, the metallurgical diode and the induced interface diode can be considered as separate devices. However. if the thickness of the neutral p-layer becomes shorter than the diffusion length of the electrons? an npn bipolar transistor is built up right under the silicon/liquid interface, as demonstrated in Ref. [ 81. In such situations a large current, injected by the silicon/liquid interface, can flow through the reverse-biased pn junction. Hence. the typical current peak exhibited in all the records of the etching process. Fig. 1 presents the geometry of the induced npn transistor before the etch-stop: the emitter is the shallow n+ layer together with the charged layers residing in the liquid phase, the base is the p-substrate and the collector is the n-layer. Observe that the induced transistor is operated with a common emitter (the voltages are all applied with respect to the liquid phase), As long as the etching proceeds, the thickness of the remaining neutral p-type material, M’~,decreases steadily. At a certain moment I$‘,,enters the range of the electron diffusion length and the built-in npn transistor activates, as demon-

t n+ inverted

liquid d&eted region Fig. 2. The geometry of the induced bipolar npn transistor after the cut-off of the aubstratr supply (etch-stop onset).

Hiith biased base.

strated in Ref. [ 81. We differ from Ref. [ 81 in adding that the emitter is made up of the n’ shallow electronic layer in the usual four-electrode configuration. The bipolar effect can explain quite well the anodic shift of the substrate potential and the premature etch-stop in a three-electrode configuration. However, in the four-electrode configuration the etching will proceed as long as the substrate bias remains close to the 00. Ignoring the ohmic losses, which can be minimized by a careful design, the substrate will keep its potential close to the OCP until the situation depicted in Fig. 3: when the two depleted regions touch each other the bias of the substrate is cut off and the depleted p-type material is suddenly connected to an anodic potential, via the n-layer. The etching terminates. It can be observed in Fig. 2 that a non-transistor structure exists between the p-type substrate and the liquid next to the lateral ( 111) walls. However, due to the p-type substrate biasing close to the OCP, the associated ‘non-transistor’ current is negligibly small and therefore it will be ignored in the following sections. In the four-electrode configuration, the transistor’s base is biased with a potential VP slightly anodic with respect to the OCP (the liquid-phase potential). The emitter current (crossing the silicon/liquid interface) is equal to the sum of the collector current (crossing the pn junction) and the base current (injected through the substrate bias contact). The emitter current density, JE, can be written as follows [ 14,151:

(1) region Fig. 1, The geometry of the induced bipolar npn transistor before etch-stop (etching proceeds).

with bidsed base,

where Lilp is the diffusion length of the electrons in the substrate, JEBO,%is the saturation current of the emitter junction for an infinitely long base (therefore independent of the base

D. Lnpndmr

et al. /Seusurs

arId Actuators

thickness), k is Boltzmann’s constant, T is the absolute temperaturc, q the absolute value of the electron charge and IZ is a factor that lies between one and two, depending on the contribution of the diffusion and recombination currents in the emitter-base depleted region. The collector current density, J,, can be written as the saturation current of the reverse-biased pn junction J,,, plus the injected current, which is the emitter current multiplied by its efficiency, y, and the transport factor, Q~ [ 14,151: Jc = ( yc+Je + JdO) M

(21

where M is the multiplication factor, being one unless the breakdown of the reverse-biased pn junction is incipient. The transport factor cu, approaches one when the base thickness approaches zero [ 14,151: cu,=sech

[L1 %

(3)

nP

The emitter efficiency y also approaches one when the base thickness approaches zero [ 14,151: y=

(4)

where Jpo and JnO are respectively the hole and electron saturation currents of the emitter junction. Apart from the effect of the bdse thickness, the chemistry of silicon etching shows that there are no holes injected in the emitter [ 2,4,16], so that Jti, = 0 and y= 1. However, due to high surface recombination at the silicon/liquid interface, y is somehow lower than unity. Neglecting the saturation current of the pn diode, the collector current can be written as~follows: J, = iw~+y LnP I,,,,,exp wp

[ 1 2k 1llkT

(5)

Eqs. ( 1) and (5) are valid if ~~~~ < L,,. If not, the transistor doesnot exist andthe structuremustbetreatedastwo separate diodes. The emitter current, described by Eq. ( I), is usually monitored during the etching process,resulting in J-r plots similar to those shown in Fig. 3. Prior to the etch-stop onset, i.e., \l’p> LnP,the transistor is not active, therefore the current hasa smallvalue dictated by the substratepotential, which is kept closeto the OCP. Once the transistor is activated, i.e., ~~~~ < LnP,the emitter current will start to increase,aspredicted by Eq. ( 1). However, the exponential term which includes the substratebias remains constant in the four-electrode configuration, resulting in a ramping of the current toward the passivationvalue, without exhibiting a peak. Fig, 3 shows some typical J-t plots obtained in the four-electrode configuration: etch-stop on a single pn junction (no ‘peak’ exhibited) and etch-stop on two different pn junctions (a higher plateauexhibited). For the three-electrodeconfiguration, the suddenincreasein the current is mainly dictated by the exponential term, in which

A 66 (1998)

259-267

261

0.6

0

-0.1 -,_~ 350

370

390

410

430 450 t [min]

470

490

510

530

Fig. 3. Typical J-i plot of silicon etching process in alkaline solutions. 20 wt.% TMAH, 90°C diffused junctiona. Etch-stop performed over one junction (no current ‘peak‘) or two different junctions [current exhibits a ‘peak’).

the substratepotential starts to float toward more anodic values. In the four-electrode configuration, both junctions are biasedat constant potentials (neglecting the possibleohmic losses) and, despite the increasein the current, passivation will not occur aslong asthe substratepotential remainsclose to the OCP! Therefore, although the transistoris still present, asshownin Fig. 1, it doesnot interfere in the etching process. However, it should be observedfrom Fig. 2 that the substrate supply is cut off at the moment the emitter-base depleted region reachesthe collector-base depletedregion. The punch-through of the transistorwill result in a floating basepotential and a zero thicknessof the neutral baseregion. It may be shownthat the substratepotential in sucha situation increasessuddenlyto almost V, and the etch-stopis achieved instantly. Fig. 2 clearly illustratesthat at the momentof the etch-stop there is still somep-type material left. For the four-electrode configuration, the thicknessof the remainingp-type material (called hereafter the ‘stop-zone’) is given by A~=~L’~,~+.Q~,~~

(6)

where ~~jp is the width of the metallurgical pn junction depleted legion extended in the p-substrate(depending on the reverse bias, doping level of both n- and p-layers and temperature) and ,ydrnnx is the width of the induced depleted region beneath the interface (depending on the substrate doping and temperature). From semiconductor physics I.14,151. the width of the above-mentioned depleted regions can be computed as follows. The width of the depleted layer created by inversion (due to the initial large difference between the Fermi levels of ptype silicon and the redox level of the alkaline solutions) is given by (7)

where IV, and fzi are the doping level of the substrate (p-type) and the intrinsic carrier concentration, respectively, and esi is the silicon permittivity. The extent of the metallurgical junction depleted layer in the substrate material depends on the junction profile. For a step junction it is given by /2~..:

Nn

(8) where NA, N,, are respectively the doping level of the psubstrate and of the n-epilayer. The extent of the metallurgical junction depleted layer in the substrate material for a graded junction is given by

(9) where u is the net dopant concentration gradient at the junction location, Wtl is the width of the entire depleted region, symmetrically extended in both n- and p-type materials, when no external voltage is applied over the junction. From the following equation, by successive iterations the value of W,, can be computed: (10) which is Eq. (9) written for no bias. However, it should be pointed out that Eqs. (9) and ( 10) are just approximations, obtained by assuming the diffusion profile as a linearly graded junction, These approximations will lose their significance when

3. Model predictions:

four-electrode

configuration

In this section, the effects of the different parameters are evaluated according to the model described above, for the four-electrode configuration. From Eq. (6), combined with Eqs. (7) and (8), (9) respectively, it can be seen that the stop-zone is dependent on: (i) the doping level of the p-type substrate, N,; (ii) the doping level and/or profile of the n-type layer, N,, or n; (iii) the junction reverse bias, VN - VP; (iv) the etching temperature, T. In addition, for the three-electrode configuration, the etchant composition and pH will play an important role. However, in the case of the four-electrode configuration there should be no influence introduced by the etchant composition, as long as the biasing potentials are set as usually: V, > V,,,, > V p&N and Vp,.PB- V,= OCP, where V,,P.Pand Vpp,,, are the passivation potentials for p- and n-type silicon, respectively. This will result in instant passivation when the two depleted layers touch each other, cutting off the substrate bias and allowing a large anodic shift of the substrate potential.

Eqs. (7) and (8). (9) respectively show that increasing the doping level of the substrate will result in a decrease of both the induced depleted region (the emitter-basejunction) and the extent of the pn depleted region into the p-substrate. The theoretical extent of the stop-zone is plotted versus the substrate doping level for step junctions in Fig. 4, and graded junctions in Fig. 5, with the n-epilayer doping level and the surface concentration of the n-diffused layer, respectively, as parameters. Briefly, the extent of the stop-zone scales according to the following rule:

In this situation, the exact extent of the depleted region for a diffused profile can be computed only by solving numerically the Poisson’s equations for the given doping profile. To complete the model. the temperature dependence of the intrinsic carrier concentration must be taken into account, since the etching is usually performed between 60 and 95°C:

( 12) where ~~~~~ is the intrinsic carrier concentration at room temperature and Eg is the silicon energy forbidden gap at room temperature, r,,. The energy forbidden gap also depends on temperature, but not significantly in the range of interest, i.e., 60 to 95°C.

0 i.OOE+14

l.ooE+i5

l.ooE+16

Na Fig. 4. The effects of the substrate junctions (ND, the epilayer doping a bias L/N - V,* = I .5 V.

l.OoE+17

l.OOE+18

[cm -9 doping on the stop-zone width fw step concentration, as parameter), 90°C and

1

‘1 6

ll~llill

--1.ooE+I6 -2.OOE+16 *5.0OE+16 -x-l.OOE+I'

*Na

= lel8

cm-3

!d

0.5

l.OOE+I4 l.O0E+14

I.OOE+15

I.OOE+16

I.OOEc17

I.OOE+l8

I.OOE+l9

Na [cm -31 Fig. 5. The effecta of the substrate doping on the stop-zone width for graded junctions ( Cs, the surface concentration. as parameter). 90°C and a bias r/N - 1’,, = 1.5 V. The implantation dose is Q,,,, =2 X 10” cm-‘.

I.OOE+15

l.OOE+l6

l.OOE+17

l.OOE+W

Nd [cm -31 Fig. 6. The effects of the n-layer doping level on the stop-zone width for step junctions (ArA, the substrate doping level, as parameter), 90°C and a biaa 1/, - LIP = 1.5 V.

(13) In order to compute the effect of the substrate doping on the width of the graded pn junctions, the following algorithm has been used: the same implantation dose was considered, Q,,=2X IO” cm-“, but different surface concentrations of the diffused layer, resulting in different concentration gradients CIat the junction location. The limited plot ranges shown in Fig. 5 arose from the following considerations: ( i) For low substrate doping levels and high surface concentrations of the diffused layer, the junction location was deeper than the usual thickness of the wafer. Therefore, these values have been discarded. ( ii) For large substrate doping levels, low surface concentrations of the implanted atoms were, of course, not enough to produce a pn junction.

The n-layer doping level and junction profile do not affect the width of the induced depleted layer under the interface, as shown by Eq. (7). However, the n-layer does affect the extent of the pn metallurgical junction depleted region into the p-substrate. For step junctions (as obtained by using epilayers), increasing the dopant concentration of the n-layer will result in a slight increase of the extent of the junction depleted layer into the p-material. Briefly, the expected scaling dependency of the stop-zone width is given by the following formula. deduced from Eq. ( 8 1: ht-

dm

( 14)

In Fig. 6, for step junctions. the theoretical extent of the stopzone is plotted versus the n-layer doping level, with the substrate doping as parameter. For graded junctions and constant implantation dose, increasing the surface concentration of the n-layer will result in an increase of the concentration gradient at the junction

r -.a 3 d

\ I i\i i !iit;-A-+jjj

K

-5.OOE+I'

((

2.5 2 1.5 1 0.5 0 l.WE+16

l.OOE+l'

l.WE+18

l.OOE+19

Cs [cm -31 Fig. 7. The effects of the n-layer doping level on the stop-zone width for graded junctions (A’,, the substrate doping. as parameter), 90°C and a bias 1i.r - \i, = I.5 V. The implantation dose is Q,,, = 2 X 10” cm- ‘.

location. This in turn will result in a slight decrease of the extent of the junction depleted layer into the p-material. Briefly, the expected scaling dependency of the stop-zone width is given by the following formula, deduced from Eqs. (9) and (IO):

In Fig. 7, for graded junctions, the theoretical extent of the stop-zone is plotted versus the n-layer surface concentration, with the substrate doping as parameter. The opposite trend compared to the step junctions comes from the constant implantation dose. Also for the graded junctions, the depleted region extends symmetrically in both n- and p-materials, whereas for the step junctions it extends mainly in the p-substrate. 3.3. IZfects of the reverse bias The reverse bias of the junction does not affect the thickness of the induced depleted layer. However, it does affect the extent of the pn metallurgical junction depleted region into the p-material: on increasing the reverse bias of the pn

264

D. Lnpndnru

et ai. /Semors

and Aciurrrurs

A 66 (19981 259-267

2.5 2.25 2 p a

1.75

:

1.25

-Q-Na=4.5e15cm-3

1.5

I 0.75 0.5 0.25

60

65

70

75

0 0

0.25

0.5

0.75

1

Vn-Vp

1.25

1.5

1.75

80

85

90

95

100

T [“Cl

2

M

Fig. 8. The effects of the applied reverse bias on the stop-zone width for&, the substrate doping level, as parameter. n-epilayer doping level iVD=7.5X10’hcm-‘,and90”C.

Fig. IO. The effects of the etching temperature epilayer (N,=7.5~ IO” cm-“), p-substrate abiasV,-VP=l.5V.

on the stop-zone width for n(NA=4.5X 10” cme3), and

2.25

1.25 1 60

0

0.25

0.5

0.75

1

1.25

1.5

1.75

2

junction, the extent of the stop-zone increases. Briefly, the expected scaling dependency is given by the following formulae, resulting from Eqs. (8) and (9): ( 16)

for step junctions and At-

[V,-

Vp]l”

70

75

80

a5

90

95

100

T [“Cl

Vn-VP IV Fig. 9. The effects of the applied reverse bias on the stop-zone width forN,\, the substrate doping level, as parameter. n-diffused layer with C, = 2 X 10” cm-j, and 90°C. The implantation dose is Q,,, = 2 X lo’& cm-‘.

A*-)Jm

65

( 17)

for graded junctions. In Figs. 8 and 9 the extent of the stop-zone is plotted versus the applied reverse bias for step and graded junctions, respectively. Observation: it must be pointed out that low values of the reverse-bias potential will not ensure the existence of an electrochemical etch-stop! The potential of the n-layer must be higher than the passivation potential, which depends on the etching conditions (temperature, etchant concentration, illumination. and so on). Therefore the plots shown in Figs. 8 and 9 have no meaning for the voltage range where passivation cannot occur!

The effect of temperature cannot be straightforwardly inferred from Eqs. (7)) (8) and (9)) since the intrinsic carrier

Fig. I I. The effects of the etching temperature on the stop-zone width for ndiffused layer (C,= 2X 10” cm-‘), p-substrate as parameter, and a bias VN- V,,= 1.5 V. The implantation dose is Q,,=2X IO” cm-‘.

concentration n, depends on temperature as well, as shown by Eq. (12). Using Eq. ( 12) in Eqs. (7) to (9). and plotting the extent of the stop-zone versus temperature, for fixed substrate and n-layer concentrations, the plots shown in Figs. 10 and I1 have been obtained. It can be concluded that an increased etching temperature will result in a slight decrease of the stopzone extent. In Fig. 10, the contributions of the induced and the metallurgical junction depleted layers are plotted for comparison. It should be mentioned that the above discussed temperature dependence is not related to the temperature shift of the passivation potential [ 1.17-191. The shift of the passivation potential due to changes in the etching temperature is irrelevant in the four-electrode configuration as long as the n-type layer bias exceeds \‘,,pp.Nfor the corresponding working conditions. If this condition is not satisfied, the etching will proceed through the n-type material as well. However, for the three-electrode configuration, the temperature anodic shift of the passivation potential [ 1,17-191 will play an important role: the assumed floating potential of the p-substrate has to move towards more anodic values. Therefore higher etching temperature will result in later passivation or, equivalently, thinner membranes.

D. Lqrtduiu

Table 1 Simulated,

measured

and experimental

Substrate doping [cm-‘]

Junction profile

3.8 x 3.0x 3.0x 3.8X 3.8 x 3.0x 4.5 x 4.5 x 4.5 x 1.0 x

graded graded graded graded step step step step graded step

10’” lo’s IO’” lOI IV5 10’” 10’” lOIS IO’” IO”

4. Experimental

er 01. /Sensors

rind Actiwtors

265

259-267

results Simulated junction depth [ wnl

SRP measured junction

Measured thickness

Experimental stop-zone

Theoretical stop-zone

Ir*ml

[wl

Ir*.ml

II*ml

18.99iO.l 1957~0.1 21.71iO.l 23.2710.1 1.950.1 1.9-tO.l 1.36fO.l 1.86kO.l 21.71F0.1 2.3iO.l

1s.9+0.15 39.5+0.15 21.6kO.15 23.2,O.U 1.8+0.15 1.5+0.15 1.3F0.15 1.8,0.15 21.610.15 2.310.15

20.37 i 0.05 21.05+0.05 23.22+ 0.05 24.65 kO.05 3.08 * 0.05 3.15io.05 250+0.05 3.OOiO.05 23.10+0.05 2.52 & 0.05

1.47io.15 1.55 kO.15 1.62t0.15 1.45io.15 1.28,0.15 1.35,0.15 1.2oio.15 1.2OiO.15 1.5OiO.15 0.22kO.15

1.46 1.58 1.63 1.55 1.24 1 .-to 1.14 1.14 1.45 0.2 1

results

100 mm, ( 100) p-type silicon wafers have been used to fabricate pn junctions with different profiles and depths. The substrate doping ranged between 3.0 and 5.4X lOI cmW3. The pn junctions were created by: (i) implantation (implantation doseQ,,, = 2 X 1015cm-*), followed by a drive-in processto different junction depths: 1.4, 1.9, 2.3, 20, 22,24 p,m; (ii) epitaxy with a doping level N,=7.5 X IO” cmm3and a final layer thicknessof 1.4, 1.9 and 2.3 pm. The etching was carried out in 20 wt.% TMAH, at 90°C with 1.5 V reverse biason the pn junction and the p-substrate held closeto the OCP. The presenceof light in the four-electrode configuration is known to produce membraneswith non-uniform thickness [ 91, due to its photogeneratedvoltage and current, together with associated ohmic losses. Therefore, the etching processeswere performed in complete darkness. Seven different batches,each batch containing more than 10 wafers, were usedfor the following evaluations. The resulting thicknessesof the realized membraneswere measuredon each wafer at five points by FTIR. A resolution of8cm-’ was usedand furthermore 50 measurementswere averaged.The measuredthicknesshasbeenextracted by averaging three different FFT algorithms. The resulting error is estimatedto be lessthan 0.05 pm. To verify the accuracy of the modei, the exact position of the metallurgical pn junction is required. Three different methods were used to evaluate the junction location: (i) processsimulationsby meansof Silvaco’s SUPREM3; (ii) spreading resistanceprofiling (SRP) ; and (iii) secondary ion massspectroscopy (SIMS), all performed on eachwafer. The SIMS happenedto be inconclusive for the doping level of the substrateused(too low values,resulting in signallevels in the noise rangeof the equipment used). The error in evaluating the junction location was0.15 Km for the SRP measurementsand 0.1 p,m by using the

SUPREM simulator.

A 66 (1998)

Table 1 collects someof the data presentedasthe average of the measurements. The standarddeviation is typically 0.02 p,rn within each batch and doesnot exceed 0.04 Frn over all consideredsamples. Data publishedby other authors,with severalvalues for psubstrateand n-layer doping levels, reverse-biasvoltagesand etching temperature [3,5,8-l 11, confirm the validity of the presentedmodel within the error limits set by the spreadof the substrateresistivity. In addition, limitations of the model presentedabove can arise in certain conditions due to ohmic losses.Prior to full etch-stop. the thickness of the substrate is considerably reduced, resulting in a higher electrical resistanceof the membrane.Due to the current increaseat the onset of the etch-stop, some ohmic lossesin the biasing voltage are expected, resulting in prematureetch-stop and thicker membranes.Higher doped, buried p-type layers right underthe pn junction will minimize the ohmic losses.This will alsoresult in a reduced stop-zone due to the local increasedsubstrate concentration.

5. Considerations

on three-electrode configuration

In this particular configuration, the theoretical approachis far more complicated due to the floating potential of the substrate.This affects the stability of the silicon/liquid interface, subjected now to severe changes.It is expected that etchant composition and its pH will play an important role in defining the stop-zone. However, a brief, qualitative attempt is madehere to clarify someof the etching characteristics. For a transistor with a floating base,the emitter and collector currents must be equal.Therefore, solving Eq. (2) for the emitter current resultsin the following expression: J,=Jc=

L44 1 - ycY# Jdo

Eqs. (3) and (4) show that both factors err and y approach unity when the thickness of the transistor base decreases

during etching. Hence,accordingto Eqs. ( 1) and ( 18)) the

current passing through the silicon/liquid interface will increase very fast when \ttp approaches zero. Eqs. ( 1) and ( 18) can be worked out together to express the potential of the substrate, VP, for a given basethickness, +I’~.Because the resulting equation is polynomial with a degree (in + 2) /nl (which lies between two and three), it cannot besolved in closedform (except for In = 2. i.e., recombination dominatesover the diffusion component in the current expression). However, the behaviour of the substrate potential when the base thickness approacheszero can be predicted qualitatively by examining the resulting equation: the floating potential of the base,VP, startsto drift anodically as theetching proceedsandthe substratethicknessdecreases. When the transistor builds up quickly (i.e.. IV,, entersthe rangeof the electron diffusion length, typically a few tensof microns), the anodicshift of the substratepotential will accelerate and, eventually, trespassthe passivationpotential. The etching stops. Due to the anodic shift of the substratepotential, the exponential term in the emitter current is dominant (seeEq. ( 1) ) , resulting in sharper,more pronounced current peaks.Comparatively, for the four-electrode configuration, the exponential term plays a secondaryrole, since the substratepotential is maintainedfixed, although smalleffects are to be expected due to ohmic lossesin someparticular structures.

6. Conclusions A new model to predict accurately the extent of the stopzone when using the four-electrode configuration has been presented.According to this modelthe substratedoping is by far the most important parameterthat influencesthe amount of remaining unetched p-type material. The extent of the stop-zonecan be reducedby: (i) increasing,even locally, the substratedoping level; (ii) using stepjunctions; (iii) reducing the reverse bias of the pn junction, but not below the passivationpotential of the n-type silicon; and (iv) increasingthe etching temperature. The model is in very good agreementwith our experimental data and with resultspublishedby other authors.

Acknowledgements The authorswould like to thank SoleconLaboratories.San Jose,CA, USA, for the spreadingresistanceprofiling measurements.Trond Westgaard, Berit Sundby Avset and Svein Petter B;ickstr@mfrom SINTEF, ElectronicsandCybernetics Microsystems Department,Oslo, Norway, are acknowledged for performing the FTIR measurements.ChalmersUniversity, SIMS Laboratories, Gotheburg, Sweden, is also acknowledged for the secondary ion mass spectroscopy measurements.

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Biographies Daniel Lcphtzl was born in Tumu Magurele? Romania, on August 17. 1967. He received the MSc. degreein electri-

D. Lupd~m

et al. /Sensors

cal engineering in 1992 and the Ph.D. degree in 1996, both from the Catholic University of Leuven, Leuven, Belgium. Presently, he is a member of the Technology Development Department of SensoNor asa, Horten, Norway. His work covers mainly the design and fabrication aspects of silicon sensors for automotive industry and medical applications. He has been a member of IEEE since 199 1. Gjetmd Kittilslrml was born in Akershus, Norway, in 1963. He received the MSc. degree in electrical engineering in 1986 and the Lic.Eng. degree in solid-state electronics in 1989, both from Chalmers University of Technology, Gothenburg, Sweden. Since 1992 he has been a member of the R&D staff at the Department of Technology Development. SensoNor asa. Horten, Norway. His main research areas are wafer bonding and micromachining of silicon and glass materials. Mar?in Nose was born in Horten, Norway, in 1965, and received the MSc. degree in applied physics in 1989 from the Norwegian Institute ofTechnology in Trondheim. In 1990 he joined Center for Industrial Research (SI) in Oslo to work with silicon sensor technology. In 1993 he joined SINTEF (Foundation for Scientific and Industrial Research) as a senior scientist, where he was involved in design and fabrication of silicon sensors. From 1996 he has been working at

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SensoNor asa in Horten as project manager for development of silicon micromechanical sensor systems for industrial and automotive applications. Stein Mdler NilseM has been a development engineer at SensoNor asa since 1994. He received the MSc. degree in electrical engineering in 1980 and a Teknologie doktor (Ph.D) degree in 1994. both from Chalmers University of Technology, Gothenburg, Sweden. From 1982 to 1994 he did research work in design and fabrication of III-V semiconductor devices for applications within radio astronomy, including low-noise HEMT transistors, mixer diodes and heterostructure varactors at Chalmers University of Technology, where he was also responsible for the process equipment in the III-V semiconductor process laboratory. Hem% Jakobsen was born in 1943 in Norway. He graduated from the University of Oslo in 1969 with an MSc. degree in physics. From 1969 to 1973 he was a researcher in the field of microelectronics at SI, Oslo. In 1970-l 97 1 he was granted a scholarship at the University of Berkeley. He was head of the Microelectronics Department at SI from 1973 to 1977. He was involved in technology development atAME between 1978 and 198 1, and was divisional manager of the components division of AME between 1982 and 1985. Since 1985, he has been the technology manager at SensoNor asa.