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A MODFET process for micrometer scale strained layer islands
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Solid-State Electronics Vol. 37, No. 2, pp. 231-235, 1994 Copyright © 1994 Elsevier Science Ltd Printed in Great Britain, All rights reserved 0038-1101/94 $6.00 + 0.00
Pergamon
A M O D F E T PROCESS FOR M I C R O M E T E R SCALE STRAINED LAYER ISLANDS K. Y. HUR, W. J. SCHAFF, L. F. EASTMANand R. C. COMPTON School of Electrical Engineering, Cornell University, Ithaca, NY 14853, U.S.A. (Received 22 June 1993; in revised form 29 July 1993)
Abstract--Previous studies have demonstrated that the density of misfit dislocations can be reduced by growth of strained layers on patterned substrates. In this paper, a new process sequence for the fabrication of pseudomorphic modulation-doped field effect transistors (MODFETs) on pattened GaAs substrates is presented. Semi-insulating GaAs substrates were patterned and dry etched using chemically assisted ion beam etching (CAIBE) to define a series of mesas prior to epitaxial layer growth. Double-doped, pseudomorphic MODFET layers were then grown on the substrates by molecular beam epitaxy. Using a planarization technique based on SiO2/photoresist, MODFETs with vacuum-passivated T-gates which bridge across up to 20 mesas were fabricated. Current-voltage measurements of these MODFETs show high output currents and good pinch-off characteristics.
INTRODUCTION
In pseudomorphic MODFETs, the output power is limited by the breakdown voltage and maximum output current. To increase the breakdown voltage, MODFET layer structures utilize a double-recessed gate trench and a charge screen layer consisting of lightly doped GaAs and AIGaAs layers above the InGaAs channel[l]. The electron sheet densities in the channel increase with higher InAs mole fractions or thicker channels. However, due to the formation of the misfit dislocation densities, strained channel thicknesses for conventional pseudomorphic MODFETs are limited by the critical layer thickness[2]. One way that has been proposed to increase the thickness of the strained layer is to use patterned substrates. The epitaxial growth of strained layer structures on patterned substrates has received considerable attention over the past several years[3-6]. During growth on patterned substrates, misfit dislocations that are formed at the strained layer interface cannot propagate through the mesa edges. This decreases the dislocation density and so increases the critical layer thicknesses. Previously, pseudomorphic InGaAs/GaAs lasers with low threshold currents[4], SiGe p - n junction diodes with improved device performance[5], and InGaAs/GaAs photodetectors with enhanced quantum efficiencies[6] have been fabricated on patterned substrates. Patterned substrate techniques are especially attractive for pseudomorphic MODFET applications because of the possible growth of thicker strained layers. However, MODFET fabrication processes based on wet etching are unsuitable for the patterned substrate technology. Uniform dimension control in micrometer-scale structures by wet etching is difficult due to the variable undercut etching characteristics. 231
Furthermore, implementation of a reliable planarization process compatible with the sub-micrometer gate lithography and recess etch is required. In this paper, a MODFET fabrication process on patterned substrates that utilizes dry etching and dielectric planarization is described.
SUBSTRATE ETCH AND GROWTH
Pseudomorphic MODFETs with n-gate configurations were fabricated. Each gate finger crosses over a group of up to 20 strained layer mesas that are separated by 2 #m-wide and 1.3 pm-deep SiO2-filled trenches. The gate periphery for the widest device is 200/~m and the mesa areas are as small as 10 x 12 # m 2. A 1.3 #m-thick photoresist layer was used as a mask layer to protect the mesa tops from the ion beam induced damage during CAIBE. The etch rate selectivity between GaAs and photoresist in the CAIBE is better than 10:1. Post-etch photoresist strip was performed in an ultrasonic bath of organic stripper to remove all of the organic residues on the substrate. To reduce the CAIBE surface damage on the mesa sidewalls and the etched facets, the samples received a mild native oxide removal in 1:5 NH4OH:H20 and etched in 3:1:150 NH4OH :H202:H20 prior to loading into the molecular beam epitaxy (MBE) chamber. The surface preparation causes edge rounding near the top of the mesas. However, this cleaning/surface preparation step is critical for the MBE growth since any organic residues or surface damage will result in material contamination and devices with poor performance characteristics. Two types of double-doped pseudomorphic MODFET structures, one with a 120,~, In0.2Ga0.sAs channel and one with a 120 A linearly
232
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graded, In~Ga~_ xAs channel, where x is graded from 0.16 up to 0.27 and then down to 0.19 (triangular), were grown (Fig. 1). Typical unetched Hall mobilities of 5113cm2/V-s and sheet carrier densities of 5.87 x 10~2cm 2 at 300 K were measured. To estimate the expected improvements in the sheet density by increasing the indium content, the electron concentration profiles in the InGaAs channels for the MODFET structures were calculated using a onedimensional self-consistent Poisson/Schroedinger charge-control simulator[7]. Figure 2(a, b) show the conduction band diagrams and the electron concentrations in the InGaAs quantum wells of the graded and uniform 20% indium structures, shown in Fig. 1, at Vg~= 0. The electron concentration profile for the MODFET structure with the uniform indium composition consists of two asymmetric peaks near the interfaces. For the graded structure, the electron distribution profile is improved by pushing the two peaks toward the center of the well thereby resulting in one wide peak. This graded structure is thought to have better transport properties due to the single peak in the center of the quantum well[8]. Both structures have a sheet density of approx. 3.9 × 10~2cm-2 at Vg~=0. However, the electron distribution profile is found to be quite sensitive to the indium composition in the well. For a 120 A-wide InGaAs channel, increasing the indium content from 20 to 30% increases the sheet density from 3.9 × 10~2cm 2 to approx. 4.7 x 10~2cm 2 at Vg~=0 (20% improvement). For the 30% indium structure [Fig. 2(c)] the channel thickness of 120]~ is well beyond the critical layer thickness.
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Fig. 2. One-dimensional simulation results of the 120/~-wide, (a) linearly graded, InxGal_.,As channel (x = 0.16 --* 0.27 ---*0.19), (b) uniform In0.2Gao.sAschannel, and (c) uniform Ino.sGa07Aschannel MODFET structures. The graded structure shows the maximum electron concentration in the center of the quantum well. DEVICE FABRICATION
SI GaAs Substrate Fig. 1. Layer structures for the double-doped MODFETs grown on the patterned GaAs substrate.
After MBE growth, ohmic contacts for the source and drain of the MODFET were deposited on the mesa tops by evaporation of 100/?k Ni, 300/1, Ge, 600/~ Au, 1000A Ag, and 1000/~, Au, followed by rapid thermal annealing at 450 ° for 15 s in Ar/H2
Strained layer islands ambient. To assess the quality of the device layers after the growth, pre-etched test structures with mesa areas ranging from 25 to 10,000/xm 2 were employed to measure the variation in open channel current with mesa size. The open channel current densities on small area mesas were low due to the residual damage on the sidewalls. On intermediate area mesas, the current densities were improved and remained at a maximum current density. On the higher indium sample, although the current densities decrease slightly as mesa areas are further increased, the data is inconclusive. The increase in sheet density and output currents on M O D F E T s with thicker channels needs further study. Because the substrates were patterned and etched prior to M B E growth with trenches as deep as approximately 1.3/xm, a robust and reliable planarization technique is needed for subsequent M O D F E T process steps. A high degree of planarization is required to link the sub-micrometer gate fingers across the individual mesas and to interconnect the source and drain terminals on each mesa. A conformal, plasma enhanced chemical vapor deposited (PECVD) SiO 2 was used because of its low permittivity compared to the other P E C V D films such as SiN, and SiC. This will help minimize the added gate-tosource fringing capacitance due to the dielectric. A single deposition of thick SiO2 was found to be inadequate due to the formation of voids in the deep trenches which then open up during the etchback step of the planarization process, lnstead, multiple PECVD SiO2 deposition and fluorine-based (CHF3:O2), low-power, reactive ion etch-back steps are utilized. This technique uses a layer of photoresist on top of the SiO 2 film. In C H F 3 : O 2 RIE, the SiO2 etches at least twice as fast as the photoresist. The SiO2 on the mesas is etched back while the SiO2 in the trenches is protected by the residual photoresist. This reduces the overall height difference between the trench floor and the mesa top, thereby increasing the degree of planarity. Approximately three PECVDRIE steps are needed to planarize trench depths of 1 t t m to 1.3 t~m. A final layer of the thin SiO2 film (approximately 2000 A) remains in between the mesas as well as on top of the mesas. Figure 3 shows a cross section of the planarized trench after three etch-back steps. For deeper trenches, more etch back steps are required. In addition to the trench planarization described above, the SiO2 film also provides device passivation and serves as a supporting structure for the gate bottom. Conventional F E T techniques utilize trilayer electron beam resists to define a mushroom-shaped gate cross-section to lower the gate resistance. This requires a complex exposure and resist development procedure. In contrast, the vacuum-passivated T-gate technique[9] consists of two separate, gate bottom and gate top layers that are patterned independently from each other. This enables the gate bottom to be patterned as small as possible while the gate top can
233
be quite wide to give smaller resistance. Because the gate bottom directly influences the high frequency performance of the device, the linewidths must be patterned as small as possible while preserving the aspect ratio of the device. In our vacuum-passivated technique, the final SiO2 planarization layer serves as the gate bottom layer, patterned in a single layer of P M M A resist by electron beam lithography. This thin SiO2 layer was then etched using the P M M A resist as mask with a low-power, fluorine-based RIE to define an opening for the gate bottom. Due to the rounding of the mesa edges during the surface preparation step, a slight over-etch was employed. This over-etch for the gate bottom process is necessary to completely remove the SiO 2 on the rounded mesa edges and to obtain good pinch-off characteristics. The gate top was then patterned in bilevel electron beam resist with a wider linewidth. Prior to the metallization, the gate openings are recessed by a 3 : 1 : 75 H 3PO4: H202"H20 etch solution to remove the G a A s cap layer. A combination of 5 0 0 A Ti, 500 ~ Pt, and 3000 A Au was deposited on top of the AIGaAs to form the Schottky gate contact. After the metallization, the recessed voids are completely sealed off, thereby forming a gate structure with vacuum-passivation. Typical gate footprints are approximately 0.3 # m (Fig. 4). A thick metal consisting of 500 ~ Ti and 3000 ]k Au was evaporated as the final fabrication step in this process to form a coplanar waveguide footprint that also links the source
Fig. 3. Cross section of a planarized trench. The wet etch surface preparation prior to the growth rounds the edges. The SiO2 etch-back completely fills 2 pm by 1.3 #m deep trench without the formation of voids.
234
K.Y. HUR et al.
(a)
Fig. 4. Vacuum-passivated, 0.3/~m T-shaped gate with 400 ~ recess. The two small holes on the sides of the gate bottom are vacuum sealed during the gate metal evaporation after the recess.
contacts a n d the drain contacts of the mesas. Figure 5 ( a , b ) show the SEM pictures of the completed MODFET.
RESULTS
F o r the uniform a n d graded p s e u d o m o r p h i c M O D F E T layers with the average indium mole fractions o f 20%, the electrical characteristics were similar. However, the graded M O D F E T s showed smaller knee voltages with lower on-resistance. This is an indication of better t r a n s p o r t properties in the graded channel structure as a result of the u n i f o r m a n d symmetric electron distribution in the center of the q u a n t u m well. In b o t h M O D F E T structures, the m a x i m u m open channel currents of approximately 750 m A / m m a n d the o u t p u t currents of 360 m A / m m at V~ = 0V were m e a s u r e d (Fig. 6). This current is c o m p a r a b l e to previous results for similar layers with c o n v e n t i o n a l p s e u d o m o r p h i c M O D F E T [ 1 0 ] . In addition, low o u t p u t c o n d u c t a n c e s are d e m o n s t r a t e d in the I V characteristics. G o o d pinch-off characteristics of the device suggest t h a t each of the 20 mesas has been properly recessed with c o n t i n u o u s gates over the SiO2-planarized trenches. Peak extrinsic transconductances of 380 m S / m m were m e a s u r e d for these M O D FETs. The r.f. properties show a typical current-gain cutoff frequency o f 50 G H z and m a x i m u m power gain frequency of 110 GHz. These frequencies along with t r a n s c o n d u c t a n c e s can be improved with shorter
(b) Fig. 5. The overview (a) and close-up (b) SEM of the MODFET structure near the planarized trenches. The ohmic contacts are visible through the SiO 2 openings. The gate fingers are placed on a group of islands that are isolated by the planarized SiO:.
gate lengths. Devices on more highly lattice-mism a t c h e d layers to d e m o n s t r a t e the predicted imp r o v e m e n t of Fig. 2(c) were not a t t e m p t e d because the optimal growth conditions for 30% indium contents are not well established.
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Strained layer islands SUMMARY
The fabrication technique described in this p a p e r allows the development of pseudomorphic M O D F E T s o n p a t t e r n e d substrates with possibly thicker channels or higher i n d i u m mole fractions for I I I - V c o m p o u n d s e m i c o n d u c t o r materials. Due to the deep trench isolation performed prior to the layer growth, this technique m a y also be employed for I n P - b a s e d F E T s to reduce the sidegating p r o b l e m s associated with the excess gate leakage. F u r t h e r i m p r o v e m e n t s in o u t p u t currents are expected with the use of this p a t t e r n e d substrate technique on I n P - b a s e d p s e u d o m o r p h i c M O D F E T structures. However, before this technique can be applied to the highly strained structures, c o m p r e h e n sive empirical material studies are required to determine the optimal growth conditions a n d mesa dimensions.
Acknowledgements--This work is supported by the National Science Foundation, the Defense Advanced Research Projects Agency, the Joint Services Electronics Program, and the U.S. Army Research Office. Device fabrication was performed at the National Nanofabrication facility at Cornell, which is supported by the National Science Foundation (ESC-8619049), Cornell University, and Industrial Affili-
235
ates. The authors would like to thank P. Mandeville for technical discussions. REFERENCES
I. J. C. Huang, G. Jackson, S. Shanfield, W. Hoke, P. Lyman, D. Atwood, P. Saledas, M. Schindler, Y. Tajima, A. Platzker, D. Masse and H. Statz, 1991 IEEE M T T - S Int. Microwave Symp. Digest, Boston, Mass. (1991). 2. J. W. Matthews and A. E. Blakeslee, J. Cryst. Growth 27, 118 (1974). 3. E. A. Fizgerald, G. P. Watson, R. E. Proano, D. G. Ast, P. D. Kirchner, G. D. Pettit and J. M. Woodall, J. appl. Phys. 65, 2220 (1989). 4. H. Jaeckel, H. P. Meier, G. L, Bona, W. Walter, D. J. Webb and E. van Gieson, Appl. Phys. Lett. 55, 1059 (1989). 5. T. I. Kamins, K. Nauka, R. D. Jacowitz, S. S. Laderman, J. L. Hoyt, D. B. Nobel and J. F. Gibbons, Electron. Materials Conf. (1991). 6. W. Q. Li, P. K. Bhattacharya and R. L. Tober, Appl. Phys. Lett. 58, 1931 (1991). 7. P. J. Tasker, M. Foisy and L. Nguyen, High-Speed Electronics and Device Scaling, SP1E, Vol. 1288, p. 212 (1990). 8. T. K. Yoo, P. Mandeville, H. C. Park, W. J. Schaff and L. F. Eastman, Appl. Phys., Lett. 61, 1942 (1992). 9. D. K. Atwood, Electron-Beam, X-Ray, and Ion-Beam Technology, SPIE, Vol. 1263, p. 209 (1990). 10. H. C. Park, Ph.D. thesis, Cornell Univ. (1993).
Solid-State Electronics Vol. 37, No. 2, pp. 231-235, 1994 Copyright © 1994 Elsevier Science Ltd Printed in Great Britain, All rights reserved 0038-1101/94 $6.00 + 0.00
Pergamon
A M O D F E T PROCESS FOR M I C R O M E T E R SCALE STRAINED LAYER ISLANDS K. Y. HUR, W. J. SCHAFF, L. F. EASTMANand R. C. COMPTON School of Electrical Engineering, Cornell University, Ithaca, NY 14853, U.S.A. (Received 22 June 1993; in revised form 29 July 1993)
Abstract--Previous studies have demonstrated that the density of misfit dislocations can be reduced by growth of strained layers on patterned substrates. In this paper, a new process sequence for the fabrication of pseudomorphic modulation-doped field effect transistors (MODFETs) on pattened GaAs substrates is presented. Semi-insulating GaAs substrates were patterned and dry etched using chemically assisted ion beam etching (CAIBE) to define a series of mesas prior to epitaxial layer growth. Double-doped, pseudomorphic MODFET layers were then grown on the substrates by molecular beam epitaxy. Using a planarization technique based on SiO2/photoresist, MODFETs with vacuum-passivated T-gates which bridge across up to 20 mesas were fabricated. Current-voltage measurements of these MODFETs show high output currents and good pinch-off characteristics.
INTRODUCTION
In pseudomorphic MODFETs, the output power is limited by the breakdown voltage and maximum output current. To increase the breakdown voltage, MODFET layer structures utilize a double-recessed gate trench and a charge screen layer consisting of lightly doped GaAs and AIGaAs layers above the InGaAs channel[l]. The electron sheet densities in the channel increase with higher InAs mole fractions or thicker channels. However, due to the formation of the misfit dislocation densities, strained channel thicknesses for conventional pseudomorphic MODFETs are limited by the critical layer thickness[2]. One way that has been proposed to increase the thickness of the strained layer is to use patterned substrates. The epitaxial growth of strained layer structures on patterned substrates has received considerable attention over the past several years[3-6]. During growth on patterned substrates, misfit dislocations that are formed at the strained layer interface cannot propagate through the mesa edges. This decreases the dislocation density and so increases the critical layer thicknesses. Previously, pseudomorphic InGaAs/GaAs lasers with low threshold currents[4], SiGe p - n junction diodes with improved device performance[5], and InGaAs/GaAs photodetectors with enhanced quantum efficiencies[6] have been fabricated on patterned substrates. Patterned substrate techniques are especially attractive for pseudomorphic MODFET applications because of the possible growth of thicker strained layers. However, MODFET fabrication processes based on wet etching are unsuitable for the patterned substrate technology. Uniform dimension control in micrometer-scale structures by wet etching is difficult due to the variable undercut etching characteristics. 231
Furthermore, implementation of a reliable planarization process compatible with the sub-micrometer gate lithography and recess etch is required. In this paper, a MODFET fabrication process on patterned substrates that utilizes dry etching and dielectric planarization is described.
SUBSTRATE ETCH AND GROWTH
Pseudomorphic MODFETs with n-gate configurations were fabricated. Each gate finger crosses over a group of up to 20 strained layer mesas that are separated by 2 #m-wide and 1.3 pm-deep SiO2-filled trenches. The gate periphery for the widest device is 200/~m and the mesa areas are as small as 10 x 12 # m 2. A 1.3 #m-thick photoresist layer was used as a mask layer to protect the mesa tops from the ion beam induced damage during CAIBE. The etch rate selectivity between GaAs and photoresist in the CAIBE is better than 10:1. Post-etch photoresist strip was performed in an ultrasonic bath of organic stripper to remove all of the organic residues on the substrate. To reduce the CAIBE surface damage on the mesa sidewalls and the etched facets, the samples received a mild native oxide removal in 1:5 NH4OH:H20 and etched in 3:1:150 NH4OH :H202:H20 prior to loading into the molecular beam epitaxy (MBE) chamber. The surface preparation causes edge rounding near the top of the mesas. However, this cleaning/surface preparation step is critical for the MBE growth since any organic residues or surface damage will result in material contamination and devices with poor performance characteristics. Two types of double-doped pseudomorphic MODFET structures, one with a 120,~, In0.2Ga0.sAs channel and one with a 120 A linearly
232
K.Y. Hug
graded, In~Ga~_ xAs channel, where x is graded from 0.16 up to 0.27 and then down to 0.19 (triangular), were grown (Fig. 1). Typical unetched Hall mobilities of 5113cm2/V-s and sheet carrier densities of 5.87 x 10~2cm 2 at 300 K were measured. To estimate the expected improvements in the sheet density by increasing the indium content, the electron concentration profiles in the InGaAs channels for the MODFET structures were calculated using a onedimensional self-consistent Poisson/Schroedinger charge-control simulator[7]. Figure 2(a, b) show the conduction band diagrams and the electron concentrations in the InGaAs quantum wells of the graded and uniform 20% indium structures, shown in Fig. 1, at Vg~= 0. The electron concentration profile for the MODFET structure with the uniform indium composition consists of two asymmetric peaks near the interfaces. For the graded structure, the electron distribution profile is improved by pushing the two peaks toward the center of the well thereby resulting in one wide peak. This graded structure is thought to have better transport properties due to the single peak in the center of the quantum well[8]. Both structures have a sheet density of approx. 3.9 × 10~2cm-2 at Vg~=0. However, the electron distribution profile is found to be quite sensitive to the indium composition in the well. For a 120 A-wide InGaAs channel, increasing the indium content from 20 to 30% increases the sheet density from 3.9 × 10~2cm 2 to approx. 4.7 x 10~2cm 2 at Vg~=0 (20% improvement). For the 30% indium structure [Fig. 2(c)] the channel thickness of 120]~ is well beyond the critical layer thickness.
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SI GaAs Substrate Fig. 1. Layer structures for the double-doped MODFETs grown on the patterned GaAs substrate.
After MBE growth, ohmic contacts for the source and drain of the MODFET were deposited on the mesa tops by evaporation of 100/?k Ni, 300/1, Ge, 600/~ Au, 1000A Ag, and 1000/~, Au, followed by rapid thermal annealing at 450 ° for 15 s in Ar/H2
Strained layer islands ambient. To assess the quality of the device layers after the growth, pre-etched test structures with mesa areas ranging from 25 to 10,000/xm 2 were employed to measure the variation in open channel current with mesa size. The open channel current densities on small area mesas were low due to the residual damage on the sidewalls. On intermediate area mesas, the current densities were improved and remained at a maximum current density. On the higher indium sample, although the current densities decrease slightly as mesa areas are further increased, the data is inconclusive. The increase in sheet density and output currents on M O D F E T s with thicker channels needs further study. Because the substrates were patterned and etched prior to M B E growth with trenches as deep as approximately 1.3/xm, a robust and reliable planarization technique is needed for subsequent M O D F E T process steps. A high degree of planarization is required to link the sub-micrometer gate fingers across the individual mesas and to interconnect the source and drain terminals on each mesa. A conformal, plasma enhanced chemical vapor deposited (PECVD) SiO 2 was used because of its low permittivity compared to the other P E C V D films such as SiN, and SiC. This will help minimize the added gate-tosource fringing capacitance due to the dielectric. A single deposition of thick SiO2 was found to be inadequate due to the formation of voids in the deep trenches which then open up during the etchback step of the planarization process, lnstead, multiple PECVD SiO2 deposition and fluorine-based (CHF3:O2), low-power, reactive ion etch-back steps are utilized. This technique uses a layer of photoresist on top of the SiO 2 film. In C H F 3 : O 2 RIE, the SiO2 etches at least twice as fast as the photoresist. The SiO2 on the mesas is etched back while the SiO2 in the trenches is protected by the residual photoresist. This reduces the overall height difference between the trench floor and the mesa top, thereby increasing the degree of planarity. Approximately three PECVDRIE steps are needed to planarize trench depths of 1 t t m to 1.3 t~m. A final layer of the thin SiO2 film (approximately 2000 A) remains in between the mesas as well as on top of the mesas. Figure 3 shows a cross section of the planarized trench after three etch-back steps. For deeper trenches, more etch back steps are required. In addition to the trench planarization described above, the SiO2 film also provides device passivation and serves as a supporting structure for the gate bottom. Conventional F E T techniques utilize trilayer electron beam resists to define a mushroom-shaped gate cross-section to lower the gate resistance. This requires a complex exposure and resist development procedure. In contrast, the vacuum-passivated T-gate technique[9] consists of two separate, gate bottom and gate top layers that are patterned independently from each other. This enables the gate bottom to be patterned as small as possible while the gate top can
233
be quite wide to give smaller resistance. Because the gate bottom directly influences the high frequency performance of the device, the linewidths must be patterned as small as possible while preserving the aspect ratio of the device. In our vacuum-passivated technique, the final SiO2 planarization layer serves as the gate bottom layer, patterned in a single layer of P M M A resist by electron beam lithography. This thin SiO2 layer was then etched using the P M M A resist as mask with a low-power, fluorine-based RIE to define an opening for the gate bottom. Due to the rounding of the mesa edges during the surface preparation step, a slight over-etch was employed. This over-etch for the gate bottom process is necessary to completely remove the SiO 2 on the rounded mesa edges and to obtain good pinch-off characteristics. The gate top was then patterned in bilevel electron beam resist with a wider linewidth. Prior to the metallization, the gate openings are recessed by a 3 : 1 : 75 H 3PO4: H202"H20 etch solution to remove the G a A s cap layer. A combination of 5 0 0 A Ti, 500 ~ Pt, and 3000 A Au was deposited on top of the AIGaAs to form the Schottky gate contact. After the metallization, the recessed voids are completely sealed off, thereby forming a gate structure with vacuum-passivation. Typical gate footprints are approximately 0.3 # m (Fig. 4). A thick metal consisting of 500 ~ Ti and 3000 ]k Au was evaporated as the final fabrication step in this process to form a coplanar waveguide footprint that also links the source
Fig. 3. Cross section of a planarized trench. The wet etch surface preparation prior to the growth rounds the edges. The SiO2 etch-back completely fills 2 pm by 1.3 #m deep trench without the formation of voids.
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K.Y. HUR et al.
(a)
Fig. 4. Vacuum-passivated, 0.3/~m T-shaped gate with 400 ~ recess. The two small holes on the sides of the gate bottom are vacuum sealed during the gate metal evaporation after the recess.
contacts a n d the drain contacts of the mesas. Figure 5 ( a , b ) show the SEM pictures of the completed MODFET.
RESULTS
F o r the uniform a n d graded p s e u d o m o r p h i c M O D F E T layers with the average indium mole fractions o f 20%, the electrical characteristics were similar. However, the graded M O D F E T s showed smaller knee voltages with lower on-resistance. This is an indication of better t r a n s p o r t properties in the graded channel structure as a result of the u n i f o r m a n d symmetric electron distribution in the center of the q u a n t u m well. In b o t h M O D F E T structures, the m a x i m u m open channel currents of approximately 750 m A / m m a n d the o u t p u t currents of 360 m A / m m at V~ = 0V were m e a s u r e d (Fig. 6). This current is c o m p a r a b l e to previous results for similar layers with c o n v e n t i o n a l p s e u d o m o r p h i c M O D F E T [ 1 0 ] . In addition, low o u t p u t c o n d u c t a n c e s are d e m o n s t r a t e d in the I V characteristics. G o o d pinch-off characteristics of the device suggest t h a t each of the 20 mesas has been properly recessed with c o n t i n u o u s gates over the SiO2-planarized trenches. Peak extrinsic transconductances of 380 m S / m m were m e a s u r e d for these M O D FETs. The r.f. properties show a typical current-gain cutoff frequency o f 50 G H z and m a x i m u m power gain frequency of 110 GHz. These frequencies along with t r a n s c o n d u c t a n c e s can be improved with shorter
(b) Fig. 5. The overview (a) and close-up (b) SEM of the MODFET structure near the planarized trenches. The ohmic contacts are visible through the SiO 2 openings. The gate fingers are placed on a group of islands that are isolated by the planarized SiO:.
gate lengths. Devices on more highly lattice-mism a t c h e d layers to d e m o n s t r a t e the predicted imp r o v e m e n t of Fig. 2(c) were not a t t e m p t e d because the optimal growth conditions for 30% indium contents are not well established.
Vg s (v) 500 0.5
0.0
05
250
-1 0 -15 0 0.0
i
i
15
i
t 20 30
Vds (V) Fig. 6. Current voltage characteristics for a 200/lm-wide, 20-mesa In0zGa08As channel MODFET. The top curve is V~, = 0.5 V and each curve represents a - 0 . 5 V step.
Strained layer islands SUMMARY
The fabrication technique described in this p a p e r allows the development of pseudomorphic M O D F E T s o n p a t t e r n e d substrates with possibly thicker channels or higher i n d i u m mole fractions for I I I - V c o m p o u n d s e m i c o n d u c t o r materials. Due to the deep trench isolation performed prior to the layer growth, this technique m a y also be employed for I n P - b a s e d F E T s to reduce the sidegating p r o b l e m s associated with the excess gate leakage. F u r t h e r i m p r o v e m e n t s in o u t p u t currents are expected with the use of this p a t t e r n e d substrate technique on I n P - b a s e d p s e u d o m o r p h i c M O D F E T structures. However, before this technique can be applied to the highly strained structures, c o m p r e h e n sive empirical material studies are required to determine the optimal growth conditions a n d mesa dimensions.
Acknowledgements--This work is supported by the National Science Foundation, the Defense Advanced Research Projects Agency, the Joint Services Electronics Program, and the U.S. Army Research Office. Device fabrication was performed at the National Nanofabrication facility at Cornell, which is supported by the National Science Foundation (ESC-8619049), Cornell University, and Industrial Affili-
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ates. The authors would like to thank P. Mandeville for technical discussions. REFERENCES
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